SET - 1

R10

Code No: R21054

a) Explain weighted and Non weighted codes.

b) Subtract (EEE)16 from (ECE)16 using twos complement method.

2.

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1.

om

II B. Tech I Semester, Supplementary Examinations, Dec 2013

DIGITAL LOGIC DESIGN
(Com. to CSE, IT)
Time: 3 hours
Max. Marks: 75
Answer any FIVE Questions
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~

(8M+7M)

a) State and explain the Boolean theorems.

b) Realize the following Boolean expression using universal gates.
( AB 1 + C 1 D + EF )

tu
pd

(5M+10M)

a) Obtain the POS simplified form for the function Y(A,B,C,D) = (0,1,2,4,5,6,12,13,14)
using K- map.
b) Simplify the following expression using K-map method.
Y(A,B,C,D) = m(0,2,5,7,8,10,13,15)
(5M+10M)

4.

a) Realize ripple adder using ones and twos complement method and explain its working.
b) Present the design approach of half subtractor.
(10M+5M)

5.

a) Realize the function f(A,B,C,D) = (1,2,5,8,10,14)+d (6,7,15) using

i) 8:1 MUX and
ii) 4:1 MUX
b) Draw and explain the logic diagram of priority encoder.

tu

kf
as

3.

a) Design a PAL for the following logical functions.

Y2=ABC+AB+AC, Y3=AB+BC+CA
Y1=AB+ACB,
b) Compare PLA, PAL and PROM with various performance parameters.

.jn

6.

8.

(9M+6M)

a) Design a characteristic equation of a T-flip flop with neat state diagrams.

b) What is meant by latch and flip-flop? Give the differences between them.

(10M+5M)

a) Design, draw and explain the working principle of Johnson counter.

b) Present the design considerations of buffer register.

(10M+5M)

7.

(10M+5M)

*******

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SET - 2

R10

Code No: R21054

om

II B. Tech I Semester, Supplementary Examinations, Dec 2013

DIGITAL LOGIC DESIGN
(Com. to CSE, IT)
Time: 3 hours
Max. Marks: 75
Answer any FIVE Questions
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~
a) Describe the various number systems required for digital logic design, in brief.
b) Convert the following octal numbers into decimal numbers.
i) (24.6)8
ii) (372.23)8
iii) (547.33)8

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es
.c

1.

(6M+9M)

a) Perform the realization of basic logic gates using universal gates. Develop the relevant
Verilog source code for the same.
b) Realize Ex-OR gate using minimum number of NAND gates.
(10M+5M)

3.

a) Simplify the following using K- map and implement the same using NAND gates.
Y(A,B,C)= (0,2,4,5,6,7)
b) Simplify the following using K- map and implement the same using NOR gate.
Y(A,B,C,D)= (0,2,5,7,8,10,13,15)
(8M+7M)

4.

a) Design, draw and explain the operation of four-bit serial adder.

b) Present the design approach of ripple adder. Draw the circuit diagram.

5.

a) Perform the realization of full subtractor using decoder and logic gates.
b) Elaborate the applications of encoder and decoder logic circuits.

(10M+5M)

(5M+10M)

a) Compare the difference between RAM and ROM.

b) Design the logic diagram using PLA with following functions.
Y1= AB+AC+ABCD,
Y2 = ABC +ABC +AC, Y3= AB,

6.

7.

8.

(8M+7M)

.jn

tu

kf
as

tu
pd

2.

Y4 =0.

a) Design, draw and explain the operation of RS- latch using universal gates.
b) Explain edge triggered D- flip flop with its logic diagram and truth table

(10M+5M)

a) Design, draw and explain the working principle of Ring counter.

b) Present the design considerations of control buffer register.

(10M+5M)

*******

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SET - 3

R10

Code No: R21054

om

II B. Tech I Semester, Supplementary Examinations, Dec 2013

DIGITAL LOGIC DESIGN
(Com. to CSE, IT)
Time: 3 hours
Max. Marks: 75
Answer any FIVE Questions
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~
a) Compute the addition and convert the result into a hexadecimal number.
(1234)8+ (1111)8 + (3456) 8
b) Convert the following into decimal number system.
i) (ABD) 16
ii) (98)16

at
es
.c

1.

(9M+ 6M)

a) Simplify the following Boolean expression.

T(x,y,z) = (x+y) { [x(y + z)]} +xy +xz
b) Represent the following Boolean function using minimum number of basic gates.
i) (AB + AB) (AB)
ii) [(ABD(C + D + E)) + (A +DBC)] (ABC + (CAD))
(7M+8M)

3.

a) Simplify the Boolean expression using K-map and implement the same using logic gates.
Y (A, B, C, D) = BD+ABC+AD+ABC
b) Obtain the simplified POS and SOP expressions for the function using K-Map.
Y(A,B,C,D)= (1,3,5,8,9,13)+d (0,7,12,14).
(9M+6M)

4.

a) Give the comparison between serial and parallel adders.

b) Design and draw the logic circuit diagram for full adder/subtractor. Let us consider a control
variable w and the designed circuit that functions as a full adder when w=0, as a full
subtractor when w= 1.
(5M+10M)

5.

a) Implement the Boolean function using a multiplexer.

Y(A,B,C,D)= (1,3,7,9,13,15)
b) Design, draw and explain a 3 to8 decoder logic circuit.

(8M+7M)

.jn

tu

kf
as

tu
pd

2.

a) Discuss about various types of ROM and tabulate the comparison of PLA, PAL and PROM.

6.

7.

8.

b) List out the applications of PLA.

(10M+5M)

a) Design, draw and Implement JK- flip flop using SR -flip flop and logic gates.
b) Give the classification of sequential logic circuits.

(10M+5M)

a) Design, draw and explain Ripple counter.

b) Draw and explain the operation of universal shift register.
******

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(7M+8M)

SET - 4

R10

Code No: R21054

om

II B. Tech I Semester, Supplementary Examinations, Dec 2013

DIGITAL LOGIC DESIGN
(Com. to CSE, IT)
Time: 3 hours
Max. Marks: 75
Answer any FIVE Questions
All Questions carry Equal Marks
~~~~~~~~~~~~~~~~~~~~~~~~
a) Why is hexadecimal number system used instead of octal number system when working with
a 8-bit and 16-bit digital computers? Explain.
b) Subtract the following binary numbers using twos compliment and specify the subtrahend
and minuend.
(6M+ 9M)
i) (101010)2 (111110) 2
ii) (11111) 2 - (10111) 2
iii) (101011) 2 - (1011) 2

2.

a) What are the basic logical operations? Explain their significance with Boolean theorems.

tu
pd

at
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.c

1.

b) Perform the realization of basic logic gates using universal gates. Draw the relevant logic
diagrams.
(5M+10M)
Using K-map method, simplify the POS expression for the Boolean function,
Y(A,B,C,D) = (0,1,2,3,4,6,10,11)
Implement the same using universal gates.

kf
as

3.

a) Draw and explain the logic diagram of carry look ahead adder.
b) Design and draw half adder logic circuit using NAND gates.

tu

4.

15M

(8M+ 7M)

a) Implement 16 to 1 multiplexer using two 8x1 and one 2x1 multiplexers and explain its
operation.
b) Write short notes on magnitude comparator.
(10M+5M)

6.

a) Tabulate the PLA programming table for the Boolean functions and minimize the number of
product terms.
A(x,y,z) =(1,2,4,6)
B(x,y,z) =(0,1,6,7)
C(x,y,z) =(2,6)
D(x,y,z) =(1,2,3,5,7)
b) Differentiate PLA and PAL with different performance parameters.
(10M+5M)

.jn

5.

7.

a) Convert T-FF to D-FF and D-FF to T-FF, with relevant truth tables and expressions.
Also draw the logic diagrams.
b) Draw the state diagram of a JK Flip-Flop and explain its logical operation.
(9M+6M)

8.

a) Design, draw and explain mod-10 counter.

b) Draw and explain the operation of bidirectional shift register.
******

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(7M+8M)