2013 26th International Conference on VLSI Design (VLSID 2013)

Tutorial T10

PostSilicon Validation, Debug and Diagnosis

Prabhat Mishra, University of Florida, Gainesville, FL, USA
Masahiro Fujita, University of Tokyo, Japan
Virendra Singh, Indian Institute of Technology Bombay, India
Nagesh Tamarapalli, AMD India Design Center, Bangalore, India
Sharad Kumar, Freescale Semiconductor, Noida, India
Rajesh Mittal, Texas Instruments, Bangalore, India

Abstract

Drastic increase in design complexity along with the emergence of new failure mechanisms in the nanometer regime
has led to significant increase in the complexity of verification, validation, and debug of integrated circuits. In spite
of extensive efforts, it is not always possible to detect all the functional errors and electrical faults during pre-silicon
validation. Post-silicon validation is used to detect design flaws including the escaped functional errors as well as
electrical faults. In this tutorial, we will provide a comprehensive coverage of both fundamental concepts and recent
advances in post-silicon validation, debug and diagnosis. The tutorial presenters (3 industry experts and 3 faculty
members) will provide unique perspectives on both academic research and industrial practices. First, we will discuss
various challenges associated with post-silicon validation and debug. Next, we will describe various techniques for
automated generation of directed tests to activate both functional errors and electrical faults. We will cover recent
advances in observability enhancement through signal selection and low-overhead trace hardware design. We will
also describe various state-of-the-art post-silicon debug approaches for modern microprocessors and SoC designs.
Next, we will present examples of real-life design failures, and successful debug scenarios in industrial settings.
Finally, we will conclude the tutorial with discussion on emerging issues and future directions for successful postsilicon validation and debug.

Speaker Biographies
Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and
Engineering at the University of Florida. He received his B.E. from Jadavpur University, Kolkata in 1994, M.Tech.
from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine in
2004 -- all in Computer Science. Prior to joining University of Florida, he spent several years in various
semiconductor and design automation companies including Intel, Motorola, Synopsys and Texas Instruments. He
has published four books, ten book chapters and more than 100 research articles in premier international journals
and conferences. His research has been recognized by several awards including the NSF CAREER Award from the

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National Science Foundation, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), five best paper
award nominations (including DATE 2012 and DAC 2009), and 2004 EDAA Outstanding Dissertation Award from
the European Design Automation Association. Prof. Mishra currently serves as an Associate Editor of ACM
Transactions on Design Automation of Electronic Systems, IEEE Design & Test of Computers, IET Computers &
Digital Techniques, and Springer Journal of Electronic Testing, Guest Editor of IEEE Transactions on Computers
(TC), and as a program/organizing committee member of several ACM and IEEE conferences including DAC,
ICCAD, DATE, ASPDAC, CODES+ISSS, RTAS and VLSI Design. He is a senior member of both ACM and
IEEE.

Prof. Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his
work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as
a researcher and started to work on automatic hardware synthesis as well as formal verification methods and tools,
including enhancements of BDD/SAT-based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories
of America and headed a hardware formal verification group developing a formal verifier for real-life designs
having more than several million gates. The developed tool has been used in production internally at Fujitsu and
externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the
University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and
software verificationmostly targeting embedded software and web-based programs. He has been involved in a
Japanese governmental research project for dependable system designs and has developed a formal verifier for C
programs that could be used for both hardware and embedded software designs. He has authored and co-authored
10 books, and has more than 200 publications. He has been involved as program and steering committee member in
many prestigious conferences on CAD, VLSI design, software engineering, and more. His current research interests
include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded
systems, digital/analog co-designs, and formal analysis, verification, and synthesis of web-based programs and
embedded programs.

Virendra Singh is an Associate Professor at IIT Bombay. He obtained Ph.D in Computer Science and Engineering
from Nara Institute of Science and Technology (NAIST), Nara, Japan in 2005. He received B.E and M.E in
Electronics and Communication Engineering from Malaviya National Institute of Technology (MNIT), Jaipur, India
in 1994 and 1996 respectively. Prior to joining IIT-B, he was a faculty member at Supercomputer Education and
Research Centre (SERC), Indian Institute of Science (IISc), Bangalore from 2007 to 2011. He also served Central
Electronics Engineering Research Institute (CEERI), Pilani, India (a national research Institute) as a Scientist for a
decade prior to joining IISc. His research interests are high performance computer architecture, testing and
verification of high performance processors, fault tolerant computing, VLSI testing, design for test, formal
verification of hardware designs, embedded system design, design for reliability, and CAD of VLSI Systems. He is
a member of the IEEE, the ACM, the VSI, and life member of the IETE. He is a co-founder of RASDAT (IEEE
International Workshop on Reliability Aware System Design and Test), and IWPVTD (IEEE Intl. Workshop on
Processor Verification, Test and Debug) workshops.

Dr. Nagesh Tamarapalli is a Fellow with AMD India Design Center in Bangalore, India, where he is engaged in
DFT and manufacturing test development for the next generation low-power Accelerated Processing Units (APUs).
Prior to AMD, he was with Mentor Graphics DFT group where he worked on logic BIST, test compression and
diagnosis tools. He has published in leading test conferences such as International Test Conference, Asian Test
Symposium and journals such IEEE Transactions on CAD. A paper he co-authored at International Test Conference
1999 on logic BIST has been selected for Honorable Mention Award. This and another paper he co-authored at
International Test Conference have been selected for significant papers from the past 35 years. He is the coinventor of 15 approved US patents in the area of testing. He has delivered DFT seminars in India and USA at
several venues including VLSI Design conference 2006, 2008 and 2012, ISQED 2007 and DAC 2008. He holds MS
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in Electrical Engineering from Indian Institute of Technology, Kharagpur, India and PhD in Electrical Engineering
from McGill University, Montreal, Canada.

Sharad Kumar manages the post silicon validation team for the Networking Products Group at Freescale
Semiconductor Pvt. Ltd. in Noida, India. He received his B.E. from Netaji Subhas Institute of Technology (NSIT),
Delhi in 1997 and an MS from Michigan State University, East Lansing in 2000. Since then he has worked
primarily for Motorola and Freescale Semiconductor. He has extensive experience is system architecture and
specification, performance modeling and post silicon validation. He currently manages the post silicon validation
team which is involved in methodology development and tools for multi-core post silicon debug, besides driving
validation for a variety of networking SoCs.

Rajesh Mittal received B.Tech (2002) from Kurukshetra University Haryana India, in electronics and
communication. He joined Texas Instruments in 2004 as Design Engineer where he worked on different DFT
aspects and currently working as DFT lead of a complex SOC. He has gone through post silicon qualification of 3
multi-million SOCs and taken design to release to production (RTP). His current focus is to take 45nm, 40mm2
mixed signal design SOC to release to production. He is part of internal TI training program where he has given
training on different DFT aspects like ATPG tool usage, memory repair flow, DMLED etc. He has also given tech
talk in TI on DFT and analog digital interface and fusefarm and its functional interface. He has also driven
several aspects of DFT methodology and has trained several DFT folks. He has authored or co-authored 5
international publications, 4 internal publications and 3 patents. He has received manufacturing incentive award
(MIA) for test time optimization while overlapping load and execution in LED test cases.

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