----------------------------------1.

RAM----------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
-- we -is the control bit when we=1 write we=0 read
-- din is the 4 bit input data
-- dout 4 bit o/p data
-- a is the 3 bit address
-- clk is the clock input
-- pulse is the pushbutton input pressed when writing into the ram
-- row is the output
entity ram is
port(
clk : in std_logic;
we : in std_logic;
-- write enable
din : in std_logic_vector(3 downto 0);
dout:out std_logic_vector(3 downto 0);
a : in std_logic_vector(2 downto 0);
pulse: in std_logic;
row : out std_logic);
end ram;
architecture Behavioral of ram is
type ram_type is array (7 downto 0) of std_logic_vector(3 downto 0); --(8x4) ram
signal ram :ram_type;
signal dclk: std_logic;
signal rowtemp: std_logic;
-- internal signal for row
component divd10
port( i : in std_logic;
o :out std_logic);
end component;
begin
u1:divd10 port map(i=>clk, o =>dclk);
rowtemp <= '0';
row <= rowtemp;

-- to enable row1

process( dclk)
begin
if(dclk'event and dclk='1') then
if( we = '1') then

-- writing into the ram

if(pulse = '0') then

-- when push button KB1 is pressed
ram (conv_integer(a)) <= din;
end if;
end if;
if( we = '0') then
dout <= ram(conv_integer(a));
end if;
end if;
end process;
end Behavioral;

-- reading from the ram

--conv_integer function is used
-- to convert bit vector to integer

-----------------------------------------------divd10
program---------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divd10 is
Port ( i : in std_logic;
o: out std_logic);
end divd10;
architecture Behavioral of divd10 is
signal cnt : std_logic_vector(18 downto 0):="0000000000000000000";
signal check: std_logic:='0';
signal t: std_logic:='0';
begin
tenm:process(i)
begin
if (i'event and i ='1') then
cnt <= cnt + '1';
--if cnt = "00011001" then
if cnt = "1111111111111111111" then
check <= not check;
cnt <= "0000000000000000000";
end if;
end if;
end process tenm;

onek:process(check)
begin
if check'event and check = '1'then
t <= not t;
o <= t;
end if;
end process onek;
end Behavioral;
waveform

----------------------------------------2. 3x8decoder----------------------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--g2a,g2b,g1 are TS5,TS4 and TS6 switch inputs i/p enable signals
-- g2a and g2b are active low inputs
--s are the switch i/p's TS1,TS2 and TS3
--dout is the o/p result routed to leds OPLED1,OPLED2,OPLED3,OPLED4,OPLED5,OPLED6.
-- OPLED7 and OPLED8

entity decoder is
Port ( g2a : in std_logic;
g2b : in std_logic;
g1 : in std_logic;
s : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(7 downto 0));
end decoder;

architecture Behavioral of decoder is

begin
process (s,g1,g2a,g2b)
begin
--checking of enable signal condition
if (g1 = '0' or g2a = '1' or g2b = '1') then
dout <= "11111111" ;
elsif(g1 = '1') then
--according to select i/p displaying the o/p on led
if(s = "000") then
dout <= "11111110";
elsif(s = "001") then
dout <= "11111101";
elsif (s = "010") then
dout <= "11111011";
elsif (s = "011") then
dout <= "11110111";
elsif(s = "100") then
dout <= "11101111";
elsif (s = "101") then
dout <= "11011111";
elsif (s = "110") then
dout <= "10111111";
elsif (s = "111") then
dout <= "01111111";
end if ;
end if;
end process;
end Behavioral;

-------------------------------------------------waveforms----------------------------------------------------------

-----------------------------------------------------3.decade
counter-------------------------------------------------------------------------decade counter, counts from 0000 to 1001
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- rst is the reset input
-- count is the output value it increaments from 0000 to 1001
-- clk is the input
entity decade_cnt is
Port ( rst : in std_logic;
count : out std_logic_vector(3 downto 0);
clk : in std_logic
);
end decade_cnt;

architecture Behavioral of decade_cnt is

signal cnt : std_logic_vector(3 downto 0);
signal bclk:std_logic;
signal dclk:std_logic;
component ibuf
port(
i:in std_logic;
o:out std_logic
);
end component;
component divd
port(i1:in std_logic;
o1:out std_logic);

end component;
begin
u1: ibuf
port map( i => clk, o => bclk);
u2: divd
port map(i1 =>bclk,o1 =>dclk);
process(dclk)
begin
if (rst = '1' ) then
cnt <= (others =>'0');
elsif (dclk'event and dclk = '1') then
cnt <= cnt + '1';
if cnt = "1001" then
cnt <= "0000";
end if;
end if;
count <= cnt;
end process;
end Behavioral;

--------------------------entity program for divd--------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
-- this component produces the clock cycle of 0.95Hz and 1.052 sec delay
entity divd is
Port ( i1 : in std_logic;
o1 : out std_logic);
end divd;
architecture Behavioral of divd is
signal cnt : std_logic_vector(20 downto 0):="000000000000000000000";

signal check: std_logic:='0';

signal t: std_logic:='0';
begin
tenm:process(i1)
begin
if (i1'event and i1 ='1') then
cnt <= cnt + '1';
if cnt = "111111111111111111111" then
check <= not check;
cnt <=
"000000000000000000000";
end if;
end if;
end process tenm;
onek:process(check)
begin
if check'event and check = '1'then
t <= not t;
o1 <= t;
end if;
end process onek;
end Behavioral;
--------------------------entity program for ibuf --------------------------------------------------library ieee;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ibuf is
Port( i:in std_logic;
o:out std_logic);
end ibuf;
architecture Behavioral of ibuf is
begin
o <= i;
end Behavioral;

-------------------------------------------------4.multiplexer 8x1-----------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--rst is the reset switch TS4 i/p
--din is the 8 bit switch i/p
--sel is the 3bit switch i/p
--y is the o/p routed to opled1
--w is the active low output roted to opled2
entity mux is
Port ( rst : in std_logic;
din : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
y : inout std_logic;
w : out std_logic );
end mux;
architecture Behavioral of mux is
begin
process(din,rst,sel)
begin
if(rst='1') then
y<='0';
elsif(rst='0')then
case sel is
when "000"=>y<=din(0);
when "001"=>y<=din(1);
when "010"=>y<=din(2);
when "011"=>y<=din(3);

when "100"=>y<=din(4);
when "101"=>y<=din(5);
when "110"=>y<=din(6) ;
when "111"=>y<=din(7);
when others =>y<='0';
end case;
end if;
end process;
w<= not y;
end Behavioral;

------------------------------------5.universal shift reg(74194)---------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--clr is switch i/p TS1,s is select 2bit switch i/p
--lin is left shift i/p switch data
--din is 4bit switch i/p,rin is right shift switch i/p
--dout is 4bit o/p routed to led
-- here clr is active low input
entity universal_shiftreg is
Port (
clk : in std_logic;
clr : in std_logic;
s : in std_logic_vector(1 downto 0);

lin : in std_logic;
din : in std_logic_vector(3 downto 0);
rin : in std_logic;
dout : out std_logic_vector(3 downto 0)
);
end universal_shiftreg;
architecture Behavioral of universal_shiftreg is
--local signal declaration
signal d1:std_logic_vector(3 downto 0);
-signal bclk:std_logic;
signal dclk:std_logic;
component divd10
port (i1:in std_logic;
o1:out std_logic);
end component;
begin
u1:divd10 port map(i1 => clk,o1 =>dclk);
clock:process(dclk,clr)
begin
dout <= d1;
if clr = '0' then
d1 <= "0000";
else if(dclk'event and dclk = '1') then
--case statement begins
case s is
when "01" => d1 <= rin & d1(3 downto
1) ;
when "10" => d1 <= d1(2 downto 0) &
lin ;
when "11" => d1 <= din;
when others => NULL;
end case;

end if;
end if;
end process clock;
end Behavioral;

------------------------------program for divd10---------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divd10 is
Port ( i1 : in std_logic;
o1: out std_logic);
end divd10;
architecture Behavioral of divd10 is
signal cnt : std_logic_vector(19 downto 0):="00000000000000000000";
signal check: std_logic:='0';
signal t: std_logic:='0';
begin
tenm:process(i1)
begin
if (i1'event and i1 ='1') then
cnt <= cnt + '1';
--if cnt = "00011001" then
if cnt = "11111111111111111111" then
check <= not check;
cnt <= "00000000000000000000";
end if;
end if;
end process tenm;
onek:process(check)
begin
if check'event and check = '1'then
t <= not t;

o1 <= t;
end if;
end process onek;
end Behavioral;

-------------------------------------------------4 bit
comparator------------------------------------------------------------------------------------------------------------------------------------------------- Title
: comparator
-- Design
: comparator1
-- Author
: xyz
-- Company : GopalReddyCollege
---------------------------------------------------------------------------------- File
: comparator.vhd
-- Generated : Tue Nov 2 14:27:56 2010
-- From
: interface description file
-- By
: Itf2Vhdl ver. 1.20
---------------------------------------------------------------------------------- Description :
---------------------------------------------------------------------------------{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {comparator} architecture {dataflow}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator is
port(
a,b : in STD_LOGIC_vector( 3 downto 0);
aeqb : inout STD_LOGIC;
agtb : inout STD_LOGIC;
altb : inout STD_LOGIC
);
end comparator;
--}} End of automatically maintained section
architecture dataflow of comparator is
signal x1,x2,x3,x4 : std_logic;
begin
x1<=a(3) xnor b(3);
x2<=a(2) xnor b(2);
x3<=a(1) xnor b(1);
x4<=a(0) xnor b(0);
aeqb <=x1 and x2 and x3 and x4;
agtb <= (a(3) and (not b(3)))or ((x1 and a(2) ) and (not b(2))) or (x1 and x2 and
a(1) and (not b(1))) or (x2 and x1 and x3 and (a(0) and (not b(0))));
altb <=aeqb xnor agtb;
end dataflow;

-------------------------------------------------7.D FLIPFLOP----------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.all;
entity dflipflop is
port(preset,clear,din,pulse: in std_logic;
q,qbar:inout std_logic );
end dflipflop;
architecture behavioral of dflipflop is
begin

process(clear,din,preset,pulse)
begin
if(clear = '0' and preset='1') then
q<= '0';
elsif(pulse'event and pulse='1') then
q<= din;
end if;
end process;
qbar<= not q;
end behavioral;
waveform