VMOS Field Effect Transistor

- overview or tutorial about the basics and essential details of the VMOS field
effect transistor or FET, electronics components used in many applications to
give higher power performance than traditional FETs.
FET tutorial includes

FET overview & types summary

FET specifications

Junction FET, JFET

MOSFET

Dual Gate MOSFET

Power MOSFET

VMOS

UMOS

TrenchMOS

GaAs FET / MESFET

HEMT / PHEMT

FinFET

VMOS field effect transistors or FETs are a form of power MOSFET and these electronics
components are used for a variety of applications where medium powers are required. The
VMOS FET gains its name from the fact that it is "Vertical Metal Oxide Silicon". From this it
can be imagined that the VMOS FET has many similarities to MOS technology, but the structure
is arranged with a V-groove which also adds another dimension to the name VMOS.
When VMOS FETs were first introduced they out-performed bipolar semiconductor technology
in many respects making the design of amplifiers much cheaper and easier. Since their
introduction VMOS FETs have become firmly established as useful power MOSFET electronics
components that can be used for a variety of power MOS applications ranging from power

supply switching applications through to medium power RF amplifiers. They are also
incorporated into many integrated circuits as they are able to switch very quickly.

VMOS FET structure

VMOS FETs are able to overcome many of the problems which prevented FETs being used in
power applications. Their new structure enabled much higher powers to be handled than was
previously possible with bipolar transistors of an equivalent size and cost.
The reason for this great improvement lies in the structure of the device. To show the advantages
of a VMOS FET a traditional MOS device. Here it can be seen that the drain and source are
separated by the gate. Current flows horizontally between the source and drain, controlled by the
potential on the gate. As the current only flows through a relatively small area, resistance values
can be high reducing the efficiency of the device.
The VMOS FET uses a different structure. The most striking point about the new device is the V
groove in the structure which is the key to the operation of the device. It can be seen that the
source is at the top of the device, and the drain is at the bottom. Instead of flowing horizontally
as in the standard FET, current in this device flows vertically giving the device its name Vertical Metal Oxide Silicon, VMOS.

VMOS FET structure

The device uses two connections for the source and accordingly there is a much large area
through which the current can flow. This reduces the ON resistance of the device allowing it to
handle much higher powers than conventional FETs.
The gate consists of a metallised area over the V groove and this controls the current flow in the
P region. As the gate is fabricated in this way it means that the device retains the exceptionally
high input resistance typical of the MOS family of devices.
The main drawback of the VMOS FET is that the structure is more complicated than a traditional
FET and this makes it slightly more expensive.

Power Mosfet-N-channel
Power MOSFETs are usually constructed in V-configuration, as shown in figure. That is why, the
device is sometimes called the V-MOSFET or V-FET. V-shaped cut penetrates from the device
surface almost to the N+ substrate through N+, P and N~ layers, as seen from figure. The N+
layers are heavily doped, low resistive material, while the N~ layer is a lightly doped, highresistance region. The silicon dioxide dielectric layer covers both the horizontal surface and Vcut surface. The insulated gate is metal film deposited on the Si02 in the V-cut. Source terminals
make contact to the upper N+ and P-layers through the Si02 layer. The N+ substrate is the drain
terminal of the device.
V-MOSFET is an E-mode FET and no channel exists between drain and source until the gate is
positive with respect to the source.On making gate positive with respect to the source, an N-type
channel is formed close to the gate, as in the case of an E-MOSFET. In this case, N-type
channel provides a vertical path for the charge carriers to flow between the N+ substrate (i.e.
drain) and the N+ source termination. When VGS is zero or negative, no channel exists and the
drain current is zero.
The drain and transfer characteristics for the enhancement-mode N-channel power MOSFET are
similar to those for the E-MOSFET, as illustrated in figs. With the increase in gate voltage, the
channel resistance is reduced and, therefore, the drain current ID increases. Thus the drain current
ID can be controlled by gate voltage control so that for a given level of VGS, ID remains fairly
constant over a wide range of VDS levels.

Drain terminal being at the bottom of the V-MOSFET (instead of at the top surface) can have a
considerable large area for any given size of the device. This allows much greater power
dissipation than are possible in a MOSFET having both drain and source at the surface.
In the power or V-MOSFETs the channel length is determined by the diffusion process, while in
other MOSFETs the channel length depends upon the dimensions of the photographic masks
employed in the diffusion process. By controlling the doping density and the diffusion time,
much shorter channels can be produced than are possible with mask control of channel length.
These shorter channels allow much more current densities which again contribute to larger power
dissipations. The shorter channel length also allows a larger transconductance gm to be attained in
the V-FET and very considerably improves the frequency response and the device switching
time.
Another very important factor in the geometry of the power MOSFET is the presence of the
lightly doped N~ epitaxial layer close to the N+ substrate. When VGS is zero or negative and the
drain is positive with respect to the source, the junction between the P-layer and the N~ layer is
reverse-biased. The depletion region at the junction penetrates deep into the N~ layer and thus
punch-through from drain to source are avoided. So relatively high VDS can be applied without
any danger of device breakdown.
P-channel V-MOSFETs are also available. Their characteristics are similar to those of N-channel
MOSFETs, except that the current directions and voltage polarities are reversed.

VMOS

From Wikipedia, the free encyclopedia

This article does not cite any references or sources. Please help
improve this article by adding citations to reliable sources. Unsourced
material may be challenged and removed. (December 2009)
This article is about a type of transistor. For the RCA computer operating system,
see Virtual Memory Operating System.

The VMOS structure has a V-groove at the gate region

A VMOS transistor is a type of metal oxide semiconductor transistor. Vmos is also used for
describing the V-groove shape vertically cut into the substrate material. VMOS /vims/ is an
acronym for "vertical metal oxide semiconductor", or "V-groove MOS".[1]
The "V" shape of the MOSFET's gate allows the device to deliver a higher amount of current
from the source to the drain of the device. The shape of the depletion region creates a wider
channel, allowing more current to flow through it.
This structure has a V-groove at the gate region and was used for the first commercial devices.
The device's use was a power device until more suitable geometries, like the UMOS (or TrenchGate MOS) were introduced in order to lower the maximum electric field at the top of the V
shape and thus leading to higher maximum voltages than in case of the VMOS.
VMOS was invented by T. J. Rodgers while he was a student at Stanford University.[citation needed]
See T._J._Rodgers#Patents 1975-1980.

References
1.

VMOSA new MOS integrated circuit technology. F.E. Holmes, C.A.T. Salama. 1974

Abstract
A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of
preferential etching of silicon to define the channels of the MOS transistors. The fabrication
involves either a three or four mask process and is capable of producing either silicon gate or
standard metal gate transistors. The technology results in very short channel length devices using
non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits
lower output conductance and higher breakdown voltage than a standard MOS transistor.
A first order theory is presented for the VMOS transistor along with measurements made on test
devices of various channel lengths. Some integrated circuit applications of the technology are
also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The
advantages of the VMOS technology in such applications are discussed.