DIGITAL ELECTRONICS, M.

TECH (PART TIME)

INPUT CIRCUITS
A simple input circuit consisting of a transmission gate activated by an enable (E) signal
and its complement is shown in Fig1

FIG1: (a) Input series transmission gate circuit and (b) its symbolic representation.
The incoming signal A is fed into the transmission gate through the protection network
(PN) from the bonding pad Of the chip. The enable signal is generated on-chip and
controls the gating of the input signal as
* X=A, when E=0
* X = high-impedance state, otherwise
Any unused chip input terminals should be tied to VDD or Vss using pull-up or pulldown resistors externally. Some input pad circuit modules have a built-in internal pull-up
or pull-down resistor or active load (normally-on transistor) with a resistance of 200 k
to 1 M

FIG2:. Inverting input circuit with (a) protection network, and (b) symbolic view.

AVINASH. N. J

INPUT CIRCUITS

DIGITAL ELECTRONICS, M.TECH (PART TIME)

FIG2 shows an inverting input circuit consisting of the protection network and a CMOS
inverter Typical values for VIL and VIH are 0.3VDD and 0.7 VDD, respectively for about
30% noise margins. This basic input circuit can be designed to receive TTL signals for
CMOS logic circuits by adjusting the ratio of the channel widths in Pmos and nMOS
transistors in the inverter. Figure 3 shows the principle of level shifting from TTL to
CMOS logic. In TTL, the worst-case output signal levels are
. VOL= 0.8 V
. VOH=2.0V
Therefore, input voltages less than or equal to 0.8 V should be interpreted low and input
voltages greater than or equal to 2.0 V should be interpreted high. After the input
protection circuit, the incoming signals have to be level-shifted to a desirable level,
depending on their voltage levels. For instance, if the incoming signal is from a TTL
driver, then its low voltage can be as high as 0.8 V and its high output voltage can be as
low as 2.0 V. Therefore a careful level shifting has to be done to translate such
logic levels to corresponding MOS gate voltage levels as shown in Fig. 3.

FIG 3: (a) TTL to CMOS level characteristic curve shifting and (b) the corresponding
voltage transfer
The level shifting between a TTL driver and a CMOS gate can be achieved by properly
designing the ratio between pMOS and nMOS transistors of the receiving CMOS inverter
gate. A practical method is to adjust the transistor ratio in the inverter gate such that the
saturation voltage at which both transistors operate in saturation region is set at the
midpoint between 0.8 V and 2.0 V. By using first-level models of MOS transistors, it can
be shown that the saturation voltage of the inverter gate can be expressed by

AVINASH. N. J

INPUT CIRCUITS

DIGITAL ELECTRONICS, M.TECH (PART TIME)

From these two equations, we find that

For example, if n = 3p and VTN, = -VTP= 1.0 V and VDD = 5 V, then in order to achieve

the nMOS-to-pMQS ratio must be

From the above calculation, we determine that r = 6.5 and

where VOUT , satisfies the following current equation:

Combining these two equations, we obtain

Vout = 4.97 V

AVINASH. N. J

INPUT CIRCUITS

DIGITAL ELECTRONICS, M.TECH (PART TIME)

and, hence

Likewise,

where VOut satisfies the following current equation

Combining these two equations, we obtain

Solving for VOUT and VIH yields:

VOUT= 0 206 V and VIH = 1.47 V
This design appears to meet the design objective of a level-shifting CMOS inverter,
providing logic 1 output level for TTL input voltages of up to 0.8 V (less than
VIL= 1.07V) and logic 0 output level for TTL input voltages not less than 2.0 V. The
output voltage of 0.206 V at Vin = 1.47 V is much less than the n-channel threshold
voltages of the next stage. However, to assure that the circuit would function properly
under all circumstances, careful circuit simulation should be performed by considering
the variations in process conditions, device temperature, and power supply voltage level.
Note that due to process variations, some chips can have strong pMOS (PH)-weak nMOS
(NL), or weak pMOS (PL)-strong nMOS (NH) combinations for which the level-shift
circuit performance would be somewhat different. This variation is illustrated in Fig. 4

AVINASH. N. J

INPUT CIRCUITS

DIGITAL ELECTRONICS, M.TECH (PART TIME)

FIG 4: Variation of the level-shifter VTC due to process variations

Figure 5, shows another non-inverting TTL level-shifting circuit. In this circuit, the level
shifting is accomplished in the first stage, which is followed by the second-stage inverter.

FIG 5: (a) Non-inverting TTL level-shifting circuit and (b) its symbolic view.
Figure 6, shows an input pad circuit with a Schmitt trigger circuit and a 70-k pull-down
resistor. This circuit provides a negative-going logic threshold voltage of 1 V and a
positive-going logic threshold voltage of 4 V, for a 5-V power supply.

AVINASH. N. J

INPUT CIRCUITS

DIGITAL ELECTRONICS, M.TECH (PART TIME)

FIG 6: (a) Input pad circuit with Schmitt trigger and (b) its symbolic view.
.

AVINASH. N. J

INPUT CIRCUITS