STK672 080

Ordering number : ENN6507
Thick-Film Hybrid IC
STK672-080
Stepping Motor Driver (Sine Wave Drive) Output Current: 2.8 A (No Heat Sink*)
Unipolar constant-current chopper (external excitation PWM) circuit with built-in microstepping controller
Package Dimensions
unit: mm
4186
[STK672-080]
46.6
3.6
15
Features
2.0
Can implement stepping motor drive systems simply by

providing a DC power supply and a clock pulse
generator.
8.5
41.2
(6.6)
1.0
Facsimile stepping motor drive (send and receive)

Paper feed and optical system stepping motor drive in
copiers
Laser printer drum drive
Printer carriage stepping motor drive
X-Y plotter pen drive
Industrial robots and other stepping motor applications
Continued on next page.
0.5
4.0
Applications
Note*: Conditions: VCC1 = 24 V, IOH = 2.0 A, 2W1-2

drive used.
25.5
The STK672-080 is a stepping motor driver hybrid IC that

uses power MOSFETs in the output stage. It includes a
built-in microstepping controller and is based on a
unipolar constant-current PWM system. The STK672-080
supports application simplification and standardization by
providing a built-in 4 phase distribution stepping motor
controller. It supports five excitation methods: 2 phase,
1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase
excitations, and can provide control of the basic stepping
angle of the stepping motor divided into 1/16 step units. It
also allows the motor speed to be controlled with only a
clock signal.
The use of this hybrid IC allows designers to implement
systems that provide high motor torques, low vibration
levels, low noise, fast response, and high-efficiency drive.
Compared to the earlier SANYO STK672-050, the
STK672-080 features a significantly smaller package for
easier mounting in end products.
<Control Block Features>

One of five drive types can be selected with the drive
mode settings (M1, M2, and M3)
2 phase excitation drive
1-2 phase excitation drive
W1-2 phase excitation drive
2W1-2 phase excitation drive
4W1-2 phase excitation drive
Phase retention even if excitation is switched.
The MOI phase origin monitor pin is provided.
The CLK input counter block can be selected to be one of
the following by the high/low setting of the M3 input pin.
Rising edge only
Both rising and falling edges
12.7
Overview
142.0=28
0.4
2.9
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircrafts
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
22002TN (OT) No. 6507-1/17
STK672-080
Continued from preceding page.
The CLK input pin include built-in malfunction

prevention circuits for external pulse noise.
ENABLE and RESET pins provided. These are Schmitt
trigger inputs with built-in 20 k (typical) pull-up
resistors.
No noise generation due to the difference between the A
and B phase time constants during motor hold since
external excitation is used.
Microstepping operation supported even for small motor
currents, since the reference voltage Vref can be set to
any value between 0 V and 1/2 VCC2.
<Driver Block>
External excitation PWM drive allows a wide operating
supply voltage range (VCC1 = 10 to 45 V) to be used.
Current detection resistor (0.15 ) built into the hybrid
IC.
Power MOSFETs for minimal driver loss
Motor output drive currents IOH up to 2.8 A (When Tc =
105C).
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage1
VCC1 max
No signal
52
Maximum supply voltage2
VCC2 max
No signal
0.3 to +7.0
0.3 to +7.0
3.3
30
mJ
Input voltage
VIN max
Logic input pins
Phase output current
IOH max
0.5 seconds, single pulse, with VCC1 applied.
Repeatable avalanche current
Ear max
Power loss
Pd max
Operating substrate temperature
Tc max
Junction temperature
Tj max
Storage temperature
Tstg
c-a = 0
105
150
40 to +125
Ratings
Unit
Allowable Operating Ranges at Ta = 25C

Parameter
Symbol
Conditions
Supply voltage1
VCC1
With input signals present
10 to 45
Supply voltage2
VCC2
With input signals present
5 5%
0 to VCC2
100 (min)
Input voltage
VIH
Phase driver voltage handling
VDSS
Tr1, 2, 3, and 4 (the A, A, B, and B outputs)
Phase current 1
IOH 1
Tc = 105C, CLK 200 Hz
Phase current 2
IOH 2
Tc = 80C, CLK 200 Hz
2.8
Electrical Characteristics at Tc = 25C, VCC1 = 24 V, VCC2 = 5 V

Parameter
Symbol
Conditions
Control supply current
ICC
Pin 6 input, with ENABLE pin held low.
Output saturation voltage
Vsat
RL = 12
Average output current

FET diode Forward voltage
Io ave
Load: R = 3.5 W/L = 3.8 mH per phase
Ratings
min
typ
0.445
Unit
max
2.1
14
0.65
mA
V
0.5
0.56
1.5
Vdf
If = 1 A
VIH
Except for the Vref pin
VIL
IIH
10
IIL
125
250
510
Input voltage
VI
Pin 7
2.5
Input current
II
Pin 7, 2.5-V input
330
415
545
VOH
I = 3 mA, pin MOI
2.4
VOL
I = +3 mA, pin MOI
[Control Inputs]
Input voltage
Input current
[Vref Input Pin]

0
[Control Outputs]
Output voltage
V
0.4
Continued on next page.
No. 6507-2/17
STK672-080
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
[Current Distribution Ratio (AB)]

2W1-2, W1-2, 1-2
Vref
= 1/8
100
2W1-2, W1-2
Vref
= 2/8
92
2W1-2
Vref
= 3/8
83
2W1-2, W1-2, 1-2
Vref
= 4/8
71
2W1-2
Vref
= 5/8
55
2W1-2, W1-2
Vref
= 6/8
40
2W1-2
Vref
= 7/8
21
Vref
PWM frequency
fc
100
37
47
%
57
kHz
Note: A constant-voltage power supply must be used.

The design target value is shown for the current distribution ratio.
No. 6507-3/17
M2
ENABLE 15
MoI 14
RESET 13
M3 12
CLOCK 11
CWB 10
M1
CR oscillator
Excitation state monitor
Raising edge/falling edge

detection and switching
Excitation mode
control
Reference clock
generation
Phase
advance
counter
PWM control
Phase excitation drive

signal generation
Pseudo-sine
wave generator
SUB
Current
distribution
ratio switching
Vref
VCC2
5
A
4
AB
3
B
2
BB
A13256
PG
STK672-080
Internal Block Diagram
No. 6507-4/17
STK672-080
Test Circuit Diagrams
Vsat
Vdf
VCC2
VCC1
6
Start
11
5
4
RL
AB
BB
STK672-080
Vref=2.5V
A
AB
B
BB
STK672-080
7
V
VCC2
13
1
A
A13257
A13258
IIH, IIL
loave, Icc, fc
VCC1
VCC2
VCC2
A
M1
M2
M3
IIH
CLK
A
CWB
IIL
RESET
ENABLE
A
2.5V
Vref
6
8
b a
Start
11
SW1
9
12
9
11
AB
B
SW2
STK672-080
STK672-080
10
13
14
Vref
ENABLE
15
BB
VCC1
SW3
15
7
fc
13
1
A13259
A13260
To measuring Io ave: With SW1 set to the b position, input Vref and switch SW2.
To measuring fc: With SW1 set to the a position, set Vref to 0 V, and switch SW3.
To measuring Icc: Set the ENABLE pin low.
No. 6507-5/17
STK672-080
Functional Description
2W1-2 Phase Excitation Drive (microstepping operation)
VCC2=5V
VCC1=10V to 45V
5
14
8
14
9
VCC2=5V
12
14
AB
B
BB
15
ENABLE
Vf 0.3V
Two-phase stepping motor
SG
11 STK672-080
CLK
RESET
100F or higher
PG
13
+
CBW
10
MoI
14
VCC2=5V
Ro1
Simplified power-on reset circuit
(This circuit cannot be used to detect
drops in the power-supply voltage.)
RoX
Vref
Ro2
A value of about 100 is recommended for

RO2 to minimize the influence of the Vref
pin internal impedance, which is 6 k.
ROX: The input impedance is 6 k 30%.
A13261
Always perform a power-on reset operation when the VCC2 supply voltage is first applied to this hybrid IC.
[Setting the Motor Current]

The motor current IOH is set by the Vref voltage on the hybrid IC pin 7. The following formula gives the relationship
between IOH and Vref.
ROX = (RO2 6 k) (RO2 + 6 k) (1)
Vref = VCC2 ROX (RO1 + ROX) (2)
1
Vref (3)
IOH =
k
RS
K: 4.7 (Voltage division ratio), Rs: 0.15 (The hybrid ICs internal current detection resistor (precision: 3%)
Applications can use motor currents from the current (0.05 to 0.1 A) set by the duty of the frequency set by the oscillator
up to the limit of the allowable operating range, IOH = 2.8 A
Ioave
IOL
IOH
0A
Motor current waveform
A13262
[Function Table]
M2
M1
M3
W1-2 phase excitation
2W1-2 phase excitation
Phase switching clock edge timing
2 phase excitation
1-2 phase excitation
Forward
Reverse
ENABLE
Motor current is cut off when low
RESET
Active low
CWB
2W1-2 phase excitation 4W1-2 phase excitation
Rising edge only

Rising and falling edges
No. 6507-6/17
STK672-080
Functional Description
External Excitation Chopper Drive Block Description
VCC1
IOFF
Enable A (control signal)
ION
Current
divider
Vref
A=1
L2
L1
CR
oscillator
Divider
800kHz
45kHz
S
Q Latch circuit
D1
MOSFET
Noise
filter
AND
Rs
A13263
Driver Block Basic Circuit Structure
Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required.
When a high level is input to A in the basic driver block circuit shown in the figure and the MOSFET is turned on, the
comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be
input, the Q output will go high, and the MOSFET will be turned on as its initial value.
The current ION flowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the Rs
potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output will
invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and the
current IOFF will be regenerated to the power supply. This state will be maintained until the time when an input to the
latch circuit set pin occurs.
In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant
current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize
with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the
same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position when
the motor is locked.
Input Pin Functions
Pin No.
Symbol
11
CLK
Phase switching clock
Function
Built-in pull-up resistor CMOS Schmitt trigger input
Pin circuit type
10
CWB
Rotation direction setting (CW/CCW)
15
ENABLE
Output cutoff
8, 9, 12
M1, M2, M3
Excitation mode setting
13
RESET
System reset
Vref
Current setting
Input impedance 6 k (typ.) 30%
No. 6507-7/17
STK672-080
Input Signal Functions and Timing
CLK (phase switching clock)
Input frequency range: DC to 50 kHz
Minimum pulse width: 10 s
Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.)
Pin circuit type: Built-in pull-up resistor (20 k, typical) CMOS Schmitt trigger structure
Built-in multi-stage noise rejection circuit
Function
When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge.
When M3 is low: The phase moves on both the rising and falling edges of the CLK signal, for a total of two steps
per cycle.
CLK Input Acquisition Timing (M3 = Low)

CLK input
System clock
Phase excitation counter clock

Excitation counter up/down
Control output timing
Control output switching timing

A13264
CWB (Method for setting the rotation direction)

Function
When CWB is high: The motor turns in the clockwise direction.
When CWB is low: The motor turns in the counterclockwise direction.
Notes: When M3 is low, the CWB input must not be changed for about 6.25 s before or after a rising or falling edge
on the CLK input.
ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold
as the internal state of this hybrid IC.)
Function
When ENABLE is high or open: Normal operating state
When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly
turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the
reset input have any effect on the hybrid IC state.
No. 6507-8/17
STK672-080
M1, M2, and M3 (Excitation mode and CLK input edge timing selection)
Function:
M2
M1
M3
2 phase excitation
2W1-2 phase excitation 4W1-2 phase excitation
Phase switching clock edge timing
Rising edge only

Rising and falling edges
Valid mode setting timing: Applications must not change the mode in the period 5 s before or after a CLK signal rising
or falling edge.
Mode Setting Acquisition Timing
CLK input
System clock
Mode setting
M1 to M3
Mode switching clock

Mode switching timing
Hybrid IC internal setting state
Phase excitation clock
Excitation counter up/down

A13265
RESET (Resets all parts of the system.)

Function
All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be at
least 10 s.)
At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current goes to
about 71% after the reset is released.
Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications must
apply a power on reset when the VCC2 power supply is first applied.
Vref (Sets the current level used as the reference for constant-current detection.)
Pin circuit type: Analog input structure
Function
Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a
voltage less than the control system power supply voltage VCC2 minus 2.5 V.
Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5 V as the
upper limit.
Output Pin Functions
Pin No.
Symbol
Function
Pin circuit type
14
MoI
Phase excitation monitor
Standard CMOS structure
Output Signal Functions and Timing

A, A, B, and B (Motor phase excitation outputs)
Function
In the 4 phase and 2 phase excitation modes, a 3.75 s (typical) interval is set up between the A and A and B and B
output signal transition times.
No. 6507-9/17
STK672-080
Phase States During Excitation Switching
Excitation phases before and after excitation mode switching <clockwise direction>
2W1-2 phase 2 phase
A
0
2W1-2 phase 1-2 phase
28
27
25
28
B 24
8 B
5
8 B
12
20
12
16
11
12
20
17
19
A
0
28
26
28
B 24
B 24
8 B
12
3
5
8 B
23
10
12
B
9
11
19
14
13
17
15
A
1-2 phase 2W1-2 phase
1-2 phase W1-2 phase
A
0
21
1-2 phase 2 phase
30 0 2
28
4
26
6
24
22
8
20
10
18
12
16 14
25
B
16
31
27
28 0 4
24
30
29
28
B 24
29
18
14
18 16
20
12
W1-2 phase 2W1-2 phase

A
20
12
16
22
10
20
A
0
30
26
W1-2 phase 1-2 phase
28
22
A
30 31 0 1 2
3
29
4
28
5
27
30 0 2
26
6
28
4
25
26
7
6
B 24
24
8
8 B
22
10
23
20
9
1816 1412
22
10
11
21
20
12
13
19
18 17 161514
W1-2 phase 2 phase
20
15
16
16
A
30
28 0 4
8
24
B 24
20
31
2W1-2 phase W1-2 phase
28
20
12
5
0
26
28
B
8 B
20
22
25
B
12
16
8
20
12
16
10
21
12
20
28 0 4
24
18
16
13
14
17
2 phase 1-2 phase
2 phase W1-2 phase
A
0
2 phase 2W1-2 phase
30
29
5
B 24
28
20
12
28
B
8 B
22
20
12
28
20
12
B
B
B
21
14
16
A
13
17
A
Excitation phase according to the first clock input pulse after changing the excitation mode setting (M1 to M2)
Excitation phase immediately before setting the excitation mode
A13266
No. 6507-10/17
STK672-080
Excitation phases before and after excitation mode switching <counterclockwise direction>
2W1-2 phase 2 phase
31
2W1-2 phase 1-2 phase
A
0
28
2W1-2 phase W1-2 phase
A
0 1
29
4
5
28
B 24
8 B
20
23
28 0 4
8
24
25
B 24
16
21
20
A
A
W1-2 phase 2 phase
W1-2 phase 1-2 phase
A
0
30
12
13
1716
15
16
8 B
9
12
20
12
28
8 B
20
12
16
12
22
22
1-2 phase 2 phase
25
8 B
10
23
13
17
15
A
1-2 phase 2W1-2 phase
A
30
4
28
20
12
26
B
8 B
20
28 0 4
24
B
B
12
16
27
28 0 4
24
22
B
9
11
19
14
30
28
21
1-2 phase W1-2 phase
A
0
B 24
30 0 2
28
4
26
6
24
22
8
20
10
18
12
16 14
B
8
31
27
12
18 16
14
29
6
20
16
A
4
28 0 4
24
26
B 24
B 24
W1-2 phase 2W1-2 phase
A
0 2
30
28
20
A
30 31 0 1 2
3
29
4
28
5
27
0
30
26
2
6
28
4
25
26
7
6
B 24
24
8
8 B
22
10
23
20
9
12
18
16 14
22
10
11
21
20
12
13
19
18 17 161514
8
20
12
16
23
10
11
12
20
19
14
18
16
A
15
2 phase 1-2 phase
2 phase W1-2 phase
A
0
2 phase 2W1-2 phase
A
2
3
27
B 24
28
20
12
26
B
8 B
28
20
12
B
B
10
28
20
12
B
11
16
A
19
18
A
A
A13267
No. 6507-11/17
STK672-080
Excitation Time and Timing Charts
CLK rising edge operation
2 Phase Excitation Timing Chart (M3=1)
1-2 Phase Excitation Timing Chart (M3=1)

1
M1 0
M1 0
M2 0
M2 0
1
0
M3 0
M3
RESET
CWB
RESET
CWB
MOSFET Gate Signal
CLK
A
MOSFET Gate Signal
CLK
A
B
B
MOI
100%
100%
71%
71%
Vref A
100%
71%
Comparator Reterence Voltage
MOI
B
B
Vref A
100%
71%
Vref B
Vref B
W1-2 Phase Excitation Timing Chart (M3=1)
2W1-2 Phase Excitation Timing Chart (M3=1)

1
M1 0
M1 0
M2 0
M2 0
M3 0
M3 0
CLK
CLK
MOSFET Gate Signal
RESET
CWB
MOSFET Gate Signal
RESET
CWB
A
A
B
B
100%
92%
100%
92%
71%
40%
71%
Vref A
B
B
MOI
MOI
40%
100%
92%
83%
71%
55%
40%
20%
Vref A
100%
92%
83%
71%
55%
40%
20%
Vref B
Vref B
A13268
No. 6507-12/17
STK672-080
CLK rising and falling edge operation
1-2 Phase Excitation Timing Chart (M3=0)
W1-2 Phase Excitation Timing Chart (M3=0)

1
M1 0
M1 0
M2 0
M2 0
M3 0
M3 0
RESET
CWB
RESET
CWB
MOSFET Gate Signal
CLK
A
MOSFET Gate Signal
CLK
A
B
B
MOI
100%
100%
92%
71%
71%
Vref A
100%
71%
MOI
B
B
40%
Vref A
100%
92%
71%
40%
Vref B
Vref B

1
M1 0
M1 0
M2 0
M2 0
M3 0
M3 0
CLK
CLK
MOSFET Gate Signal
RESET
CWB
MOSFET Gate Signal
RESET
CWB
A
A
B
B
100%
92%
83%
71%
55%
40%
20%
Vref B
20%
Vref A
B
B
MOI
MOI
100%
92%
83%
71%
55%
40%
97%100%
88% 92%
77% 83%
71%
66%
55%
48%
40%
31%
14% 20%
Vref A
97%100%
88% 92%
77% 83%
66% 71%
48% 55%
40%
31%
14% 20%
Vref B
A13269
No. 6507-13/17
STK672-080
Thermal Design
<Hybrid IC Average Internal Power Loss Pd>
The main elements internal to this hybrid IC with large average power losses are the current control devices, the
regenerative current diodes, and the current detection resistor. Since sine wave drive is used, the average power loss
during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during 2
phase excitation.
The losses in the various excitation modes are as follows.
2 phase excitation
fclock
IOH fclock
Pd2EX = (Vsat + Vdf) IOH t2 +
(Vsat t1 + Vdf t3)
2
2
fclock
IOH fclock
Pd1-2EX = 0.64 {(Vsat + Vdf) IOH t2 +
(Vsat t1 + Vdf t3)}
4
4
fclock
IOH fclock
PdW1-2EX = 0.64 {(Vsat + Vdf) IOH t2 +
(Vsat t1 + Vdf t3)}
8
8
fclock
IOH fclock
Pd2W1-2EX = 0.64 {(Vsat + Vdf) IOH t2 +
(Vsat t1 + Vdf t3)}
16
16
fclock
IOH fclock
Pd4W1-2EX = 0.64 {(Vsat + Vdf) IOH t2 +
(Vsat t1 + Vdf t3)}
16
16
Here, t1 and t3 can be determined from the same formulas for all excitation methods.
L
t1 =
R + 0.35
R + 0.35
n (1 IOH)
VCC1
L
t3 =
R
VCC1 + 0.35
n ()
IOH R + VCC1 + 0.35
However, the formula for t2 differs with the excitation method.

2 phase excitation
2
t2 = (t1 +t3)
fclock
7
W1-2 phase excitation t2 = t1
fclock
3
t2 = t1
fclock

15
t2 = t1
fclock
IOH
t3
t1
t2
A13270
Motor Phase Current Model Figure (2 Phase Excitation)

fclock: CLK input frequency (Hz)
Vsat: The voltage drop of the power MOSFET and the current detection resistor (V)
Vdf: The voltage drop of the body diode and the current detection resistor (V)
IOH: Phase current peak value (A)
t1: Phase current rise time (s)
VCC1: Supply voltage applied to the motor (V)
t2: Constant-current operating time (s)
L: Motor inductance (H)
t3: Phase switching current regeneration time (s)
R: Motor winding resistance (W)
No. 6507-14/17
STK672-080
<Determining the Size of the Hybrid IC Heat Sink>
Determine c-a for the heat sink from the average power loss determined in the previous item.
Tc max: Hybrid IC substrate temperature (C)
Tc max Ta
c-a = [C/W]
PdEX
Ta: Application internal temperature (C)

PdEX: Hybrid IC internal average loss (W)
Determine c-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below.
The ambient temperature of the device will vary greatly according to the air flow conditions within the application.
Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the aluminum
plate side) will never exceed a Tc max of 105C, whatever the operating conditions are.
16
12
ien
t
40
60
C
50C
No. Fin 25.5(C/W)

0
0
10
12
14
16
Heat sink thermal resistance, c-a C/W
c-a= Tc max Ta (C/W)

Pd
Tc max=105C
b
am
ed
nte ure
ara rat
Gu mpe
te
Heat sink thermal resistance, c-a C/W
S c-a
Pd c-a
20
2m
thi
ck
10
Al
(w
ith
the
Vertical
standing type
Convection
cooling
pla
te (
sur
wit
fac
hn
ep
os
urf
ace
ain
ted
pre
par
bla
atio
n)
ck)
No. Fin 25.5(C/W)

1.0
10
IC internal average power dissipation, Pd W
100
Heat sink area, S cm2
Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss
from the thermal resistance of the hybrid IC substrate, namely 25.5 C/W.
105 50
For a Tc max of 105C at an ambient temperature of 50C
PdEX = = 2.15 W
25.5
For a Tc max of 105C at an ambient temperature of 40C
105 40
PdEX = = 2.54 W
25.5
This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above.
(See Tc Pd curve in the graph on page 17.)
<Hybrid IC internal power element (MOSFET) junction temperature calculation>
The junction temperature, Tj, of each device can be determined from the loss Pds in each transistor and the thermal
resistance j-c.
Tj = Tc + j-c Pds (C)
Here, we determine Pds, the loss for each transistor, by determining PdEX in each excitation mode.
Pds = Pd/4
Since the average loss includes the loss of the current detection resistor, we take that voltage drop into consideration in
the calculation.
Vsat = IOH Ron + IOH Rs
Vdf = Vdf + IOH Rs
The steady-state thermal resistance of a power MOSFET is 15.6C/W.
No. 6507-15/17
STK672-080
fc VCC2
fc Tc
55
53
53
51
51
PWM frequency, fc kHz
PWM frequency, fc kHz
55
49
47
45
43
41
39
49
47
45
43
41
39
37
37
35
4
4.5
5.5
35
0
20
Supply voltage, VCC2 V
Motor Current vs. Output Supply Voltage

Internal diode forward voltage, Vdf V
Output saturation voltage, Vsat V
80
100
120
1.6
1.4
1.2
C
05
=1
Tc
0.8
5C
=2
Tc
0.6
0.4
0.2
0.5
1.5
2.5
1.4
25
1.2
Tc=
105
Tc=
0.8
0.6
0.4
0.2
0
0
3.5
0.5
1.5
2.5
Motor current, IOH A
Motor Current vs. Motor Voltage
Motor Current vs. Substrate Temperature
2.5
2.5
IOH=2
60
Internal Diode Forward Voltage vs. Motor Current
1.6
0
0
40
Substrate temperature, Tc C
1.5
0.5
1.5
IOH=1A
0.5
Vref=0
0
0
10
20
30
40
0
0
50
20
Motor voltage, VCC1 V
Reference Voltage vs. Input Current

Reference voltage input current, IVref A
Input current, IVref A
400
25
=
Tc
300
250
200
150
100
50
0
0.5
1.5
Reference voltage, Vref V
60
80
100
120
Reference Voltage Input Current vs. Substrate Temperature
450
350
40
2.5
450
Vref=2.5V
400
350
Vref=2V
300
250
200
Vref=1
150
100
50
0
0
20
40
60
80
100
120
No. 6507-16/17
STK672-080
Tc Pd
Motor Current vs. Reference Voltage

80
Substrate temperature rise, Tc C
VCC1: 24 V motor: PK264-02B
Reference voltage, Vref V
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0.5
1.5
70
60
50
40
30
20
10
0
0
2.5
Substrate Temperature Rise Test
1.5
2W1-2ex
40
2ex
30
0
0
3.5
VCC1 : 24V
Test motor : PK264-02B
Motor current :
IOH :
2-phase excitation: 1.5 A
2W1-2 phase excitation: 2 A
With no heat sink
2
5 7 1000
200Hz
50
10
3.5
CLK
20
2.5
Motor Current (IOH) Derating Curves for the Operating Substrate Temperature Tc
60
Substrate temperature rise, Tc C
0.5
Hybrid IC internal average power dissipation, Pd W
Hold mo
de
2.5
1.5
Motor voltage: 24 V
Motor resistance (R): 0.4
Inductance (L): 1.2 mH
0.5
5 7 10000
CLK frequency, PPS - Hz
5 7 100000
0
0
20
40
60
80
100
120
Operating substrate temperature, Tc C
Notes The above current ranges apply when the output voltage is not in the avalanche state.
The above operating substrate temperatures (Tc) are measured when the motor is operating. Since Tc will vary depending on the ambient
temperature (Ta), the value of IOH, and whether IOH is continuous or intermittent, the actual values of Tc must be verified (measured) in an actual
operating end product.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customers
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customers products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the Delivery Specification
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of February, 2002. Specifications and information herein are subject
to change without notice.
PS No. 6507-17/17
This datasheet has been download from:

www.datasheetcatalog.com
Datasheets for electronics components.

STK672 080

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STK672 080

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Ordering number : ENN6507

Can implement stepping motor drive systems simply by

Facsimile stepping motor drive (send and receive)

Continued on next page.

Note*: Conditions: VCC1 = 24 V, IOH = 2.0 A, 2W1-2

The STK672-080 is a stepping motor driver hybrid IC that

<Control Block Features>

SANYO Electric Co.,Ltd. Semiconductor Company

The CLK input pin include built-in malfunction

Maximum supply voltage1

Maximum supply voltage2

Logic input pins

Phase output current

0.5 seconds, single pulse, with VCC1 applied.

Repeatable avalanche current

Operating substrate temperature

Allowable Operating Ranges at Ta = 25C

With input signals present

With input signals present

Phase driver voltage handling

Tr1, 2, 3, and 4 (the A, A, B, and B outputs)

Tc = 105C, CLK 200 Hz

Tc = 80C, CLK 200 Hz

Electrical Characteristics at Tc = 25C, VCC1 = 24 V, VCC2 = 5 V

Control supply current

Pin 6 input, with ENABLE pin held low.

Output saturation voltage

Average output current

Load: R = 3.5 W/L = 3.8 mH per phase

Except for the Vref pin

Except for the Vref pin

Except for the Vref pin

Except for the Vref pin

Pin 7, 2.5-V input

I = 3 mA, pin MOI

I = +3 mA, pin MOI

[Vref Input Pin]

Continued on next page.

[Current Distribution Ratio (AB)]

2W1-2, W1-2, 1-2

Note: A constant-voltage power supply must be used.

Excitation state monitor

Raising edge/falling edge

Phase excitation drive

Internal Block Diagram

Two-phase stepping motor

A value of about 100 is recommended for

[Setting the Motor Current]

W1-2 phase excitation

2W1-2 phase excitation

Phase switching clock edge timing

1-2 phase excitation

1-2 phase excitation

W1-2 phase excitation

Motor current is cut off when low

2W1-2 phase excitation 4W1-2 phase excitation

Rising edge only

Enable A (control signal)

Driver Block Basic Circuit Structure

Phase switching clock

Built-in pull-up resistor CMOS Schmitt trigger input

Pin circuit type

Rotation direction setting (CW/CCW)