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Thesis/Dissertation Collections
2004
VHDL implementation and synthesis of adaptive

thresholding
Nicholas P. Sardino
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Sardino, Nicholas P., "VHDL implementation and synthesis of adaptive thresholding" (2004). Thesis. Rochester Institute of
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VHDL Implementation and Synthesis

of Adaptive Thresholding
A Thesis Submitted in
Partial Fulfillment of the
Requirements for the Degree of
Master of Science
m
Computer Engineering
Nicholas P. Sardino
Primary Advisor:
Kenneth Hsu
Dr. Kenneth W. Hsu, Professor, Dept. of Computer Engineering
Committee Member:
Andreas Savakis
Dr. Andreas Savakis, Dept. Head, Dept. of Computer Engineering
Committee Member:
Roy S. Czernikowski
Dr. Roy S. Czernikowski, Professor, Dept. of Computer Engineering
April, 2004
RELEASE PERMISSION FORM:
Rochester Institute of Technology
VHDL Implementation and Synthesis of Adaptive Thresholding
I, Nicholas P. Sardino, hereby grant pennission to the Wallace Library of the Rochester
Institute of Technology to reproduce my thesis in whole or in part, on or after April 19,
2004. Any reproduction will not be for commercial use or profit.
Nicholas Sardina
Nicholas P. Sardino
Date
Abstract:
As the
world of mobile multimedia
small, high performance, low
algorithms used
in these
In
keep
up
the speed at
with
implementation
This thesis
binarization
while
adapt
was utilized
modeled
FPGA
to
High-level
programming
an
implementations
where
be
increasingly
our
of
the
need
for
software
important issue in
technological society
and
examined.
and
is
throughout the
methods
does the
computing technology is growing, the hardware
algorithm
their
an
the goals of
system
properties of
course of
and
operation was
were
simulation
used
the
of
four image
thresholding
a simple global
to the luminescent
the image.
research.
simulated
in both the
A high-level
Each
in VHDL,
tested using a
custom
modeling
algorithm,
algorithm
and
then
PC interface.
and
VHDL
of the algorithms.
on
the Excalibur NIOS
Of the four algorithms, the local thresholding
algorithm would not
algorithms were synthesized
development board.
synthesize
realize
in MATLAB, implemented
synthesized
The
which
The first
the remaining three
first
to
describes the implementation
design philosophy
was
order
so
grow,
The implementation
therefore has become
of these algorithms must
algorithms.
continues to
power microchips.
systems
more recent applications.
computing
to
an
Altera 20K200E FPGA
due to the high-level VHDL
implementation. The remaining three,

and quick adaptive
thresholding
loop
global
commands
which
thresholding, running
were synthesized and written
were
utilized
average
in the
thresholding,
to the target device
with
7.12%, 89.76%
global
thresholding
thresholding
MHz.
and
58.52%
utilization of
algorithm
achieved
achieved
17.6 MHz,
the devices on the FPGA
and quick
clock
frequency
thresholding
of
respectively.
62.1
obtained a
MHz,
frequency
The
running
of
21.4
Table
of
Table
Contents
of
Contents
List
of
Figures
in
List
of
Tables
iv
List
of
Equations
Acknowledgements
vi
Glossary
vii
Chapter 1 : Introduction
1.1 Purpose
1.2 Design
of HDL
Image
Processing Research
Philosophy
1.3 Development Hardware
1.4 Related Work

1
.5
Related Work in Adaptive
Chapter 2: Algorithm
Thresholding
Theory
2.1 Image
Thresholding A Global Scheme

Thresholding
2.2.1 Local Thresholding
2.2.2 Running Average Thresholding.
2.2.3 Quick Adaptive Thresholding
-
2.2 Adaptive
Chapter 3: Algorithm
Modeling
10
16
16
17
17
20
27
32
3.1 Global
32
3.2 Local
33
Thresholding
Thresholding
3.3 Running Average Thresholding
3.4 Quick Adaptive Thresholding
Chapter 4: VHDL Implementation
37
39
42
4.1 Global
45
4.2 Local
45
4.3
46
4.4
Thresholding
Thresholding
Running Average Thresholding
Quick Adaptive Thresholding
Chapter 5: FPGA Synthesis
47
48
5.1 Test Hardware
48
5.2 Global
51
Thresholding
5.3 Local Thresholding
5.4 Running Average Thresholding
5.5 Quick Adaptive Thresholding
Chapter 6: Results
and
Analysis
51
53
53
54
6.1 General Conclusions

6.2 Quantitative Results
54
6.3 Analysis
56
55
"
References
11
List of Figures
Figure 1.1
Figure 1.2
Figure 1
Design
Philosophy
Altera Excalibur NIOS Development Board
Histogram-Based
12
Global
Thresholding Example
Local Thresholding Example (Equations)
Horizontal Running Average
Running Averages (Combination)
16
Local
18
.3
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Vertical
19
20
21
Running Averages
Running Average Thresholding Example 1
Figure 2.8 Running Average Thresholding Example 1 (Equations)
Figure 2.9 Running Average Thresholding Example 2
Figure 2.10 Running Average Thresholding Example 2 (Equations)
Figure 2.11 Quick Adaptive Thresholding (Left to Right Scheme)
Figure 2.12 Quick Adaptive Thresholding (Right to Left Scheme)
Figure 2.13 Quick Adaptive Thresholding (Alternating Scheme)
Figure 2.14 Quick Thresholding Example
Figure 2.15 Quick Thresholding Example (Equations)
21
Figure 3.1
Local
Thresholding Buffer Example (Row 1)

Thresholding Buffer Example (Rows 2 & 3)
Local Thresholding Buffer Example (Rows 4 & 5)
Quick Thresholding Pixel Analysis Order
Quick Thresholding Buffer Implementation
34
Local
35
23
24
25
26
27
28
28
30
31
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 4.1
State Diagram for VHDL Implementations
43
Figure 5.1
Interface Board Schematic
50
36
39
40
List
of
Tables
44
Table 4.1-1/0 List

Table 6.1
Table 6.2
Algorithm Runtime
55
(MATLAB)
56
Synthesis Results
IV
List of Equations
Equation 1.1
Equation 1
.2
Iterative
12
Entropic
13
Thresholding Equations
Field Matching Thresholding Equations
Equation 1.3
-Edge
Equation 1.4
-Niblack's
Equation 1.5
Equation 2.1
Equation 2.2
Equation 2.3
Equation 2.4
Equation 2.5
Equation 2.6
Equation 2.7
Equation 2.8
Equation 2.9
Equation 4.1
Equation 4.2
Equation 4.3
Sauvola
Local Variance Equations
and
Pietaksinen's Local Variance Equations
Possible Local
Running Average Thresholding (Horizontal Average)
Running Average Thresholding (Horizontal Weighting Function)
Running Average Thresholding (Vertical Average)
Running Average Thresholding (Vertical Weighting Function)
Running Average Thresholding (Final Determination)
Quick Adaptive Thresholding (Determination of 's')
Quick Adaptive Thresholding (Weighted Average)
Quick Adaptive Thresholding (Threshold Calculation)
Global
Thresholding End Pixel

Local Thresholding End Pixel
Quick Thresholding End Pixel
13
14
14
17
20
20
21
22
22
28
29
29
45
46
47
ACKNOWLEDGEMENTS
The
author wishes
and
Dr.
to thank
his
committee
Roy Czernikowski for
Tolleson for supplying
members, Dr. Ken
Hsu, Dr.
Andreas
Savakis,
their guidance throughout this project, and Richard
equipment when
it
was needed.
Bell from Altera Corporation for providing the
VI
support
special
for FPGA
thanks goes to Brian
synthesis.
Glossary
HDL (Hardware Description
describe
and
Language) [1]
the
model
Programming
discrete
of
operation
Programming methods include behavioral, dataflow,

ASIC (Application Specific Integrated
task repeatedly and very
one
VHDL
[1]
The
Verilog [1]
example of a
PDA (Personal Digital
MATLAB
[2]
Array) [1]
Assistant) [1]
In this project, it
implementation in VHDL.
one
Global
bit (black
[7]
Adaptive
used as
and can
Small,
be
used
used
mobile
of
was used
converting
research.
circuit
in the design
that can
be
of custom chips.
computing device that
provides
numerical calculations with matrices
to
model
the
algorithms
each pixel of an
Binarization technique whereby
the threshold between black and
Term
used
whereby the threshold for

properties of the image.
methods
Local
Thresholding [8]
lighting
in this
perform
before their
image from
n-bits
to
or white).
Thresholding [7]
is
Process
designed to
management and portable multimedia capabilities.
and vectors.
Image Binarization
circuit
An integrated
An engineering tool for performing
components.
hardware description language.
manufacturing
information
personal
to
efficiendy.
FPGA (Field Programmable Gate

programmed after
hardware
used
and structural.
Custom
hardware description language
specific
Another
Circuit) [1]
language that is
a predetermined global value
white.
to describe any
a given pixel
of
the image binarization
is determined
dynamically by the
Thresholding [8] Binarization technique whereby the threshold for

dynamically determined by examining a window of pixels around it.
-
vn
each pixel
is
Chapter 1: Introduction
1.1 Purpose
Mobile
of
HDL Image
computing is
multimedia
higher performance,
no
longer
suitable
the-fly image
examined so
Since
are
can
that
be
flexible
and
for
lower
technology
the
rise
and as a
result, so is the
image processing tasks
Standard
such as
The hardware implementation

can
keep up with the
demands
full-custom ASIC is time consuming
considered as
and
on
power microprocessors.
real-time
manipulation.
designing
Verilog
Processing Research
the
valid,
of
of
day
modern
for smaller,
software algorithms are
streaming
these
video and
on-
algorithms must
be
of business and society.
very expensive, VHDL
and
Implementation
cost-effective approaches.
performance
need
FPGAs rivals that
or
strategies
of
current
microprocessors.
FPGAs containing image
and video
into PDA's, scanners, printers,

These
chips
may be
specific
a wide range of uses.
role
in the future
1.2 Design
and
Regardless
algorithms will
digital cameras,
to their target
of how
as well as
application or
they
are
eventually find their way
home
may be
used, FPGAs
personal computers.
reprogrammable
will
play
to have
very important
of mobile multimedia computing.
Philosophy
A high-level design philosophy
simply
processing
means
was utilized throughout
the
that high level programming techniques were
course of
used
this
project.
This
for both the MATLAB
modeling
design
VHDL implementation.
and the
The Figure below
the steps of the
shows
process.
K
MATLAB
High-Level
VHDL
Figure 1.1
Initially,
Design
Philosophy
the algorithms were modeled using MATLAB.

the
of
understanding
theory behind
the
algorithms
comparisons with which to compare the results of the
The
next
developed from the MATLAB

and out of
machine.
A testbench
supply the
required
target
see
code.
the system and the
The final step
FPGA,
was
and
how the tools
This
and
was
also
done to
to
gain a
establish
better
baseline
VHDL implementations.
to implement the algorithms in VHDL using behavioral descriptions
was
step
FPGA
Synthesis
to
overall
was created
data in the
for
protocol was made
for passing information into
operation was encapsulated
each algorithm
to
gather
in
simple state
data from text files
and
correct order.
synthesize
verify the
these high-level behavioral algorithms, write them to the
results
made use of
the
through the
available
use of a
hardware
PC interface. The
and
how the
goals were
to
algorithms performed
overall.
The
results obtained were analyzed
and
clarity
of
mainly in
the resulting images.
Two
a qualitative
fashion, looking
at
the quality
quantitative results were obtained
however
which
indication
provide a good
algorithms.
These two
and maximum
of
how the
synthesis
tools handled the behavioral
numbers are the utilization percentage of
operating
FPGA logic
elements
frequency of the chip while running each algorithm.
1.3 Development Hardware
There
boards in
existence
today,
in
price and performance.
so
that design tools and
each with
It is
their
a good
used
in this
needed
for the
FPGA,
Figure 1.2.
software,
scope of
ease of
and
research
can
is
FPGAs
which
vary tremendously
chosen selectively.
by
which
Altera Corporation
was chosen
picture of the
and
is
called
includes the development board
provides much more
This board
use, and low cost. A
be
made
This kit,
documentation,
the project.
of
development
and
idea, from the beginning, to identify the target part
the Excalibur NIOS Development Kit.
itself, bundled
lines
own
implementation details
The development board
size
logic devices
are numerous manufacturers of programmable
functionality
for its flexibility,
development board
than
was
fairly large
can
be
seen
in
Figure 1.2
Altera Excalibur NIOS Development Board
The NIOS development board has

certain pins on
inputs. A C
the FPGA.
five
volt
tolerant header that interfaces
Through this, the data
program was written
could
be
sent
using
directly
standard
to imitate the actions of the testbench in
to
TTL level
order
to verify
the operation of the algorithms in the chip.
1.4 Related Work

In the early 1960's, the idea
of reconfigurable
like Gerald Estrin [REF 1]. With

accompanied
academic
by decreasing
and
cost
commercial
implementations for
recent
trends in
more research
arenas,
was
computing
technology
in this
specifically
custom and reconfigurable
born
area
the aid of people
increasing
has taken
dealing
hardware.
with
with
performance
place
in both the
high-performance
Research
two
and
development in this
directions
structural
high-level
software
researchers
synthesize
projects
study existing
directly
to
and suites of tools
compilers
do the
Gokhale,
oriented
or
in
one of
low-level
and
and
synthesis
Others
and
on
develop
protocols.
applications written
effectiveness of
behavioral
code.
own
efforts on
and
designing
programming languages
called
Using
(RTL)
contrast
the
the Streams-C
Evaluation of the
An Applications Perspective [REF 2].
Streams-C,
the
and
which
plus
Streams-C
structural
to the AMC Wildforce board
and
their
is
small
group
which uses
performance
compiler
of
the
All
subset
libraries
of
and
same algorithms
using
implementations
methods
in synthesizing parallel,
of
four
Xilinx 4036 FPGAs. Their
different
work
synthesize
they
compiler,
VHDL.
Their
synthesizable
in Streams-C. In addition, they implement the
Register-Transfer-Level
compare
focus their
presented a paper entitled
instructions from the C programming language
synthesized
tools to take behavioral code
Field Programmable Gate Arrays in 2001, Jan Frigo,
Dominique Lavenier
existing language
communication
Some
few different forms.
to accomplish the same end goal.
Streams-C C-to-FPGA Compiler:

an
in
while other researchers
same.
At the International Symposium
to
be
based designs,
compiler
themselves
manifest
hardware,
compiler algorithms to
involves
and
space tends to
designs.
High-level design
Maya
design
particular
to
pipelined
are
goal
gauge
is
the
designs from
Malay Haldar,
entitled
Anshuman Nayak, Alok
Applications Described in MATLAB
Compilers, Architectures,
[REF 3].
Their
MATLAB
code
work
and
commercial synthesis
has the ability to
through their
use
is
and
on a
VHDL through
the International Conference
of
compiler
by
to
take
algorithm
The
five image processing benchmarks
generated
2000
Xilinx XC4028 FPGA.
pipelining.
then compiler,
To test the
into
compiler
effectiveness
implemented in three
each
VHDL,
the
second
the third is VHDL
passed
structural
and
on
of
passed
loop
Image
compiler with optimizations enabled.
on
Programming
presented
a paper
compiler algorithm
and
Pedro Diniz
and
of
describing parallelizing
is to integrate high-level
optimized
Language Design
Implementation in June
the
University
of
Southern
of
A Compiler Approach to Fast Hardware Design Space Exploration
provide researchers and
which
FPGAs for Signal
on
The first implementation is hand-coded
in FPGA-Based Systems,
goal
presented a paper
The VHDL is then
VHDL.
structural
2002, Byoungro So, Marry Hall,
Their
Prith Banerjee
Synthesis for Embedded Systems in November
tool and implemented
VHDL
At the Conference
California
at
involves the development
create
they
methods.
un-optimized
and
optimize the
their compiler,
different
is
and
Automated Synthesis of Pipelined Designs
Processing
of
Choudhary,
developers
for the demands

for creating
compilers with
a method
of
compiler
existing behavioral
to take C
todays technology.
pipelined
development [REF 4].
programs
This
synthesis
directly
to
tools to
hardware
paper presents a specific
behavioral VHDL from C
code.
They
compare
the performance of the same compiler algorithm with different levels of parallelization on
five different multimedia
In June
of
Southern
algorithms.
2003, Heidi Ziegler, Mary Hall,
California,
Pipelined FPGA Applications

5].
Their
different
work
and
began
with
at
the
40th
Pedro Diniz,
of
the
Stanford SUIF
of an
communication techniques to pipelined
VHDL is
with
VHDL
standard
compare the performance of the
four
and
on
presented a compiler
FPGAs
with
Power
and
Compilers, Architecture,
[REF 6].
Their
Their
delivers high
consumption.
paper
in their
paper
Using five
HDL
and compiles
behavioral VHDL.
simulated
in
it
This
software
Alok
Choudhary,
at
and
to
synthesized
designs
processing
optimized
designs
the International Conference
flexible C to HDL
which
Prith
Targeting ASICs
Synthesis for Embedded Systems in October
signal
takes a
compiler
PACT HDL: A C Compiler
Performance Optimizations
and
and
Pal, Xiaoyong Tang,
introduces PACT HDL,
performance
consumption of PACT
compiler
showing how
communication methods.
Alex Jones, Debabrata Bagchi, Satrajit

Banerjee
compiler
image processing kernel,
using four different

compiled
of
Annual Design Automation Conference [REF
the adaptation
C implementation
University
Compiler-Generated Communication for
communication schemes affected the performance.
standard sequential
the
again with
focus
on
benchmarks, they
against unoptimized
of
2002
compiler which
minimizing
compare
designs.
power
the power
Computer
Science
students
examining HDL implementations
October
1998
of
the
at
faculty
and
at
of various
Workshop
on
Reconfigurable
the
it
In
Computing
implementation
more
July
widely
of
of
They had
developed
generate
VHDL
at
and
in
goal
In
years.
in Paris,
Processing
is to
Applications
develop
reconfigurable
Processors (ASAP '00) in
on
tools to aid in
computers, making
they
again presented
their
called
SA-C
to
hardware.
In
reconfigurable
published another paper on
Workshop
with a compiler
on
the
same subject which
Computer Architectures for
(CAMP'00) [REF 9].
Colorado State
University have
done
much more
and spoken at numerous conferences and educational
Their
most
recent
FPGAs"
on
faculty
Boston, Massachusetts [REF 8].
binaries for programming
the
the Fifth IEEE International
papers,
that time.
students and
high-level programming language
and students at
published more
Applications
and
Machine Perception
since
algorithms
few
Computing (PACT'98)
Image
[REF 7]. Their
past
the IEEE International Conference on Application-Specific
that same year,
was presented at
faculty
for the
R. Beveridge
of
have been
University
accessible.
Systems, Architectures,
The
Machines"
2000, Colorado State University
of
and
Prograrnming
image processing
latest work, this time
September
High-Level
State
algorithms
Reconfigurable
France, W. Najjar, B. Draper, A.P.W. Bdhm,

"The Cameron Project:
Colorado
and
was
publication
presented
is
entitled
in August
of
research,
institutions
"Implementing
2002
at
the
Image
International
Conference
Pattern Recognition in Quebec
on
information
on
the
Cameron Project,
Researchers in the low-level design

into the
space spend time
synthesizing
structural
figure
performance and
February
University,
VHDL.
They
out ways
Marc Trepanier
breaking
them
blocks for the

compare
high-level designs down
They
up.
complex
hardware
take these
structural
algorithms, ultimately
performance
to
software
to take advantage of this speedup in hardware.
2002, Srdjan Coric,
of
and
building
detailed
more
http://www.cs.colostate.edu/cameron/
smaller structural components which make
components and use them as
In
visit
For
[REF 10].
City
of
Miram Leeser,
Mercury
Computer
and
Eric Miller
Systems, Inc.
the International Symposium on Field Programmable Gate Arrays
of
Northeastern
presented a paper at
entitled
Parallel-Beam
Backprojection: An FPGA Implementation Optimizedfor Medical Imaging which

the first
application of reconfigurable
research
which
used
is
involves the implementation

a
in the
very
the
a software
Jorg
and
imaging field.
parallelized
performance of
of
and
The
presented
parallel-beam
reconstruction
algorithm
parallelized
of
their paper
[REF 11].
backprojection
from dense
hardware
performance.
Their
algorithm
projection
is implemented using discrete
data
structural
In the end, they
against non-parallel
hardware
and
consumer grade microprocessors.
Martin-Luther-University
entitled
imaging
medical
to further increase the
the
Paul Molitor
the
for image
implementation on two target
Ritter
Germany
common method
medical
components
compare
computing to
marked
Halle-
Wittenberg
in
Halle,
A Pipelined Architecture for Partitioned DWT
Based
Lossy Image Compression Using FPGAs
Programmable Gate Arrays in

pipelined
for
of
the International Symposium on Field
2001 [REF 12].
February
hardware implementation
at
Their
research
et alii presented
for High Performance Image
implementation
of
2002
at
on a custom
and synthesized
Techniques, Pavel Zemcik

entitled
Processing Applications
International
the
of
in
paper
reconfigurable
July 10,
describes his
FPGA
2000
the Brno
work
co-processor
press release
Xilinx FPGAs for
reconfigurable signal
in taking
great
success
ASIC
and
Graphics
complex
success
story
Processing
processing boards.
10
and
Interactive
presented
a paper
Imaging Algorithms Using FPGAs
a general purpose
in the
involves
process.
Technology
of
research
The DSP is designed
chip.
Computer
on
for performing
details the
[REF 13]. Their
0.5um CMOS
University
Reconfigurable Image
Microsystems has had
Conference
Hardware Acceleration of Graphics
14]. His
1998, Jens Peter
of
their paper, Realization of a Programmable Parallel DSP
the HiPAR-DSP
using VHDL descriptions
the
lossy image compression on an FPGA development board using external memory.
Wittenburg,
In
with
the two-dimensional discrete wavelet transform
At the Annual ACM Design Automation Conference in June
the
deals
DSP
and
pairing it
[REF
with a
image processing tasks.
of
VisiCom
Module"
commercial
"VisiCom Uses
[REF 15].
arena
as
well
Annapolis
with
their
1.5 Related Work in Adaptive

A
of
recent
survey
Electronic
of
Thresholding
thresholding
Imaging
entitled
algorithms and techniques was published
Survey
Quantitative Performance Evaluation.
into
six
distinct
categories
Over Image
This
paper categorizes
Histogram-Based thresholding
and
Local
algorithms work
methods
by
histogram [REF 23].
Convex hull thresholding is
algorithm which works
by
In the
identified
sample
Techniques
thresholding
using concavity
points
to
shape of
one example of a
choose
potential
threshold
3f
Histogram-Based
11
the image's
histogram-based
the threshold for
with red arrows.
Figure 1.3
Entropy-
[REF 23].
analyzing the
histogram in Figure 1.3, two
and
algorithms
including Histogram Shape-Based, Clustering-Based,
Based, Object Attribute-Based, Spatial,
image.
Thresholding
in the Journal
a particular
values
are
Clustering-Based thresholding
particular clusters
determined
example of a clustering-based
developed
model.
the
an
For
iterative thresholding
foreground
and
assigning
by fitting Gaussians
thresholding
a given number of
by
methods work
algorithm
iterations,
background
method
class
a new
means
be
used
Top,
pixel
to one of two
One
to the histogram [REF 23].
is iterative thresholding. T. W. Ridler
based
on a
two-class Gaussian
threshold is determined
until
as
the
mixture
average of
the differential between the
threshold and the previous threshold becomes sufficiently
equations can
each
small
[REF 23]. The
new
following
to describe this algorithm.
lun
mf(T)
mb(T)
where
mf(Tn)
T!g=oSP^)
Equation 1.1
Entropy-Based
methods use
and
Iterative
the entropy
of
mb(T)
Thresholding
background
and
the sum
the two
of
as
distinct signals,
Equations
equations
12
of
gray levels in
Entropic thresholding
of which
entropies reach a maximum.
Wong quantize this by the following
Y?g=Tm^gp{g)
the distribution
determine the threshold for the image [REF 23].

foreground
the threshold is
image to
analyzes
determined
J. N. Kapur, P. K. Sahoo,
[REF 23].
an
and
the
when
A. K. C.
Top,=argmax[Hf(T) + Hb(T)
where
Hf(T)
j
*'g=o
P(T)
Equation 1.2
Entropic
Object Attribute-Based thresholding

already binarized
version of
field
created
binarized image. The

the two edge
the
field images
*-ig=T+\ pff\
image
and
the same image to determine the threshold [REF 23].
An
from the
global
i^log^
p(T)
algorithms use similarities
is
example of an object attribute-based method
an edge
Hb(T)
and
prp\
original
edge
image is
being
compared
an
field matching thresholding,
compared
threshold is taken as the
between
value
to
that
[REF 23]. This
an edge
field from the
maximizes
concept can
where
the overlap of
be described
by
following equation.
Top,
arg mmiEgray
PI Ebmary (T)]
where
Egray
Ebmary
edSe
=
edge
Equation 13
Spatial thresholding
neighboring
pixels
recognizes the
order
entropies
field from
field from
Edge Field
methods
original grayscale
use
both
due to
spatial
binary image
Matching Thresholding Equations
the
to determine a threshold
fact that two images
image
could
structure.
gray
value
value
distribution
and properties
[REF 23]. Co-occurance thresholding
have identical histograms
with
different
Threshold is then determined partially
13
of
n*
by
considering the
adaptive
detennined
method of
thresholding
per pixel
is the
Niblack'
based
deviation
interest [REF 23].
each
horizontal
pixel's
vertical
and
algorithms are a class of algorithms where the threshold
on
number of
any
W. Niblack
and
statistics
[REF 23].
following
equation
window and a
A. K. Jain
is the
show
bxb,
The
by the
around
is
simplest
local
mean
the pixel of
to determine the threshold
standard
that using b
deviation.
15
and
Using
=
-0.2
results.
Equation 1.4
and
the
in the
T(i, j)
J. Sauvola
local
a given window of pixels,
uses
mean of pixels
satisfactory
for
calculated
method, O. D. Trier
produces
of
local thresholding, Local Variance, determines the threshold
and standard
where m
probability
[REF 23].
neighbors
Locally
co-occurance
M. Pietaksinen's
following equation with k
0.5
T(i,j)
Equation 1.5
km(i, j) +
a(i, j)
Niblack's Local Variance Equations
method
and
and
upon
Niblack's
method
128 [REF 23].
m(i,j)
Sauvola
improves
\l + k
vQJ)
Pietaksinen's Local Variance Equations
14
by
using the
The three
adaptive
adaptive
category.
thresholding
algorithms studied
These types
hardware implementations
where
of algorithms
data is
streamed
15
in
this thesis all
fall into the
locally
lend themselves best to low-memory,

in
and out.
Chapter 2: Algorithm Theory
2.1 Image
The
is
Thresholding
purpose of
greater
whose
thresholding is
intensity
being black
used
and one
to binarize
being
Standard thresholding
interest is less than
this
greater
method can
image that
can
be
an
white.
image
The
that
the global
threshold, the
be
below
where
to be
intensity
the
be to
for the
is
new pixel
is
entire
set
Figure 2.1
Global
16
zero
size of the
image. If the
white.
threshold
Example
one,
machines.
An
105
Thresholding
the
to
Global Thresholding
zero or
If
eight-bit grayscale.
Threshold
to
pixels
Typically
to black.
set
specified global
level.
reduce
copy
intensity
setting the
while
change all pixels
new pixel
threshold, the
all pixels whose
machines and
threshold value
global
assumed
another
is to
fax
than the
seen
setting
purpose of this would
applications such as
uses a global
by
intensity level,
is less than that threshold to
is beneficial in
and
interest is
to segment an image
than a certain threshold value to one
thresholding is
image
A Global Scheme
pixel of
the pixel of
example of
is 105 for
test
2.2 Adaptive
Thresholding
Adaptive thresholding differs from
dynamically
changed as
images
dramatic
with
were chosen
this
for this
project was
pixels
in
for
the image is processed, making it
lighting
[REF 16]. Three
changes
in
project and are explained
embedded real-time
than
and out rather
thresholding in
standard
applications,
image,
read an entire
image. The
chosen algorithms also
2.2.1 Local
Thresholding
great
that the
possible
adaptive
to
algorithms were chosen
process
have lower memory
it,
and
might
be
used
with the pixel of interest at
the
methods
Since the focus
detail below.
then
is
accommodate
thresholding
that
produce
of
stream
the
new
requirements.
Local thresholding is to statistically determine the threshold level based

surrounding pixels,
threshold
center.
One
of the
on a window of
following methods
to determine the threshold for a particular pixel:
mean
median
-or
max+min
2
Equation 2.1
In
order
large.
to get a
valid
has
Possible Local
representation, the size of the
In contrast, choosing
each region
uniform
a region
intensity
considered region must
that is too large goes
[REF 16]. The
17
following
against
be
fairly
the assumption that
example uses a window size
of
3x3
original
and
the median method of
image is
determining
an eight-bit grayscale
the threshold, again, assuming that the
image.
Local Thresholding
Window Size
Figure 2.2
Local
3x3
18
D.
100 + 110 + 80 + 85
..
Pixel #1
P/*g/#2:100
..,
Pixel #3
110 + 140 + 80 + 85 +
139=109
110 + 140 + 145 + 85 + 139 + 140
r
=
100 + 110 + 80 + 85 + 75 + 78
:
110 + 140 + 80 + 85
88
139 + 75 + 78 + 139
1/iri1
=
Etc.
Figure 2.3
126.5
00
=
,^100
Pixel #6
93.75
1Jic
Pixel #5
Mne
=
Local
Thresholding Example (Equations)
19
1 05. 1 1
2.2.2
In the running
stream changes.
calculated
arbitrary
by
algorithm, the threshold is determined continually
average
The horizontal running average, Y(i), for
the
following difference
given an
image,
pixel,
the data
(i,j),
myimage.
can
be
is
an
that
size:
7(/)
Equation 2.2
Y(i
1) + f[my image(i, j)
The function
{[delta]
is
f[my
Horizontal
1)]
Running Average
weighting function
in
a scan
image (i,j)
f[x]
Equation 23
y(i
Running Average Thresholding (Horizontal Average)
successive points
weighting function
Figure 2.4
between
equation,
a given
as
Running
which
1)]
be
given
0.2x[my_ image(i, j)
Average
For the
line [REF 17].
-y(i
Thresholding
20
returns
the change
sake of
in
example, let the
by:
y(i
(Horizontal
average
1)]
Weighting Function)
The
actual
running
threshold
is determined bv
of
the horizontal and
vertical
averages.
Figure 2.5
The
a combination
vertical
running average,
Running Averages (Combination)
Z(j), is
ZU)
Equation 2.4
calculated
similarly
by the following function:
Z(j-l) + g[Y(i)-ZU-l)]
Running
Figure 2.6
Average
Thresholding
Vertical
21
(Vertical
Running Averages
Average)
The function g[Y(i)

given
Z(j
1)] is
a special
Equation 2.5
If
following
did
be
not
not
purposes, a
j)
<
z(j) then BLACK
functions,
[REF 17]:
else
WHITE
Running Average Thresholding (Final Determination)

to determine the threshold for each
an eight-bit grayscale original
indicate that the
have
o.2x[r(o|y.-z(j-i)]
examples use the above equations
pixel, again, assuming
weighting
by the following equation
my_image(i
Equation 2.6
does
which can
Running Average Thresholding (Vertical Weighting Function)
The final judgment is determined
and
f[delta]
by:
gM
The
weighting function like
this
algorithm produces a
algorithm produces
enough contrast
second example
completely
the
white
first
regions of black and white.
also given which yields a
and white pixels.
22
binary
sample
image.
insufficient results, but that
to clearly define
is
image. For
image
the
This
image
result
input image
For illustrative
with
both black
Figure 2.7
Running Average Thresholding Example
23
Y(0)
Z(0)
.'.
7(2)
Z(0)
Z(l)
.-.
102
-+
102
20.4
0.2(1 40 -102)
WHITE
0 + 0.2(109.6-0)
Pixel #3
20
#7#r
0 + 0.2(102-0)
Pixel #2
7(0)
->
100 + 0.2(110-100)
Z(0)
.-.
0 + 0.2(100-0)
Pixel #1
F(l)
.'.
100 (first pixel)
109.6
21.92
WHITE
80 (y?r^ pixel)
20 + 0.2(80-20)
Pzxe/ #5
32
FF///TE
Etc.
Figure 2.8
Running Average Thresholding Example
24
(Equations)
Running
Figure 2.9
Average Thresholding
Running Average Thresholding Example 2
25
7(0)
Z(0)
.-.
0 + 0.2(232-0)
Pixel #1
7(1)
Z(0)
.-.
232 (first pixel)
Z(0)
Z(\)
0.2(230
232)
0.2(23 1.6-0)
->
23 1
.6
->
23 1
.6
46.32
WHITE
0.2(224
0 + 0.2(230.08
Pixel #3
7(0)
.-.
Pixel #2
7(2)
/.
46.4
FFH77E
->
232
23 1 .6)
0)
230.08
46.016
WHITE
230 (first pixel)

46.4
Pixel #5
->>
0.2(230
46.4)
83.12
0H77E
Etc.
Figure 2.10
Running Average Thresholding Example 2 (Equations)
26
2.2.3 Quick Adaptive
Quick
adaptive
Thresholding
thresholding is
hardware implementation because

moving
weighted average
one pass
through the
is
[REF 18].
This has implications
not confined
strikingly different
its
algorithm
quickness and
from the last
document. This differs from
is
or
of
calculated
the average
right, right to left,
very basic
to one specific
on
row or
the way in
that lends itself nicely to a
low memory
constraints.
's'
pixels
the running
column, but
which
the
alternating between the two. It turns
seen,
which requires
a specific number of pixels
pixels are accessed
out
Quick Adaptive
Thresholding
27
only
because
average algorithm
that
(Left to Right
left to
each method produces
results.
Figure 2.11
Scheme)
Figure 2.12
Figure 2.13
It
was
best
Quick Adaptive
Quick Adaptive
found from Wellner's
results.
Therefore,
's'
research
Thresholding (Alternating Scheme)
that about 1/8
of
the
width of
the image yields the
is determined by:
Equation 2.7
Thresholding (Right to Left Scheme)
Number of Columns
Quick Adaptive
Thresholding (Determination
28
of s')
The
average
specifically
is
computed as an approximation of the average of the
weighted
by
the pixel of
interest. The
following
formula is
's'
last
used
pixels,
to
calculate
the approximated average, G(s):
G(s + l)
G(s)-
G(s)
Current Pixel Value}
V
Equation 2.8
The
actual
given
by
Quick Adaptive
threshold is computed
Thresholding (Weighted Average)
as a percentage of the
average, G(s). This
the amount above or below the average that the threshold
an absolute percentage of
threshold for
The
the average.
following
formula is
should
used
percentage
be,
rather
is
than
to calculate the
each pixel:
T(n)
Equation 2.9
The
following
100
Thresholding (Threshold Calculation)
the above equations to determine the threshold for each
an eight-bit grayscale original
that the number of columns is
pixels are analyzed
G(s)-
Quick Adaptive
example uses
pixel, again, assuming
32,
making
alternating from left to right
29
4,
and
and
image.
For this example,
assume
that t
15.
that the
right to left.
Also
assume
Figure 2.14
Quick Thresholding Example
30
>JUU
I
G(s)
r()
100
0-- +
25
25
()
21.25
,100,
.'.
Pixe/ #1
G(s)
T(n)
J*7//r
->
25-
46.25
4
^85^
46.25
39.3125
vlOOy
Pzxe/ #2
G(,)
T(n)
^/Y/r
46.25-^^ +
69.68
85
69.68
^
=
59.23
vlOOy
.".
P/xe/ #3
->
^/7/7/
G(,)
88.51-== +
T(n)
100.49-
.-.
-+
101.383
85 ^
=
Uoo,
Pixe/ #5
86.1751
JPH77E
Etc.
Figure 2.15
Quick
Thresholding Example (Equations)
31
Chapter 3: Algorithm Modeling
The first step in

order
feasibility
to assess the
into the best way to do

image
and process the
useless as a
so.
in this case,
of
It
them in
implementing
would
have been very
when all pixel values were
step in this
filled sequentially to
cycle
these algorithms was to model them using MATLAB in
implementing
input data entering into the
a clock cycle was represented
For the MATLAB algorithms, the
native
whole
method would
image
have been
were created and
algorithm at one pixel per clock
'imwriteO'
'imreadO'
were used
and
specified.
Thresholding
The modeling
previous pixel
state
in the
by one iteration through a loop.
functions
to read in and write out image data in any format
3.1 Global
simple to read
known. This
insight
and give some
Instead, temporary buffers
process though.
simulate
hardware
of
the global
information is
information
must
be
thresholding
required
stored
into the algorithm, decide black
The MATLAB
code
"myGlobal.m"
and can
for the
be
seen
to
algorithm
compute
to compute the
or white
global
based
the
on
the
32
given global
algorithm
on page
A-l.
is
For
trivial,
as
no
In addition,
no
was
new pixel value.
new pixel values.
thresholding
in Appendix A
in MATLAB
each pixel
coming
threshold
contained
in the file
3.2 Local
Thresholding
Two different
versions of the
fixed
version used a
understanding
much more
of
window size of nine pixels
how the
flexible
implementation.
local thresholding
window
implementation
It does
size
version
be
window
not make sense
As
stated
algorithm.
(window
The
size +
pixel of
specified, the
before,
size
of
have been
read.
be in the
in the
code
On
for
of
the
to verify the
3x3.
variable
with
Since the
version,
all
the fixed 3x3
used
was
even number of pixels on each
exact center of the window.
each algorithm such
given window size +
that, if
-I)
>r
to hold pixels as
in the image. Pixels
they
33
is
can
an even
entered
actually
Window Size
,-,-,,
Number of Columns
each successive cycle, one pixel
To
was used.
the buffer required to implement this algorithm is
1) by the number of columns
once
case
better
for the VHDL
used
a window size of
using
gain a
designed to be
the goal
size version was
specific
must
temporary buffer
done to
purposes.
interest
Window Size
processed
and was
second version was
to have a window size that has an
a check was put
window size was
implemented. The first
to the variable implementation
for illustrative
used
for this,
is simply
with respect
side, considering the

correct
and operate on a variable window size
In addition, the fixed
explanations will
3x3
The
algorithm worked.
operation of the variable window size version
fixed
algorithm were
read
into
equal
start
the
to
being
1
pixels
the
buffer
and one pixel
at
the center of the
following
while
The
example.
is
window
red pixel
the blue pixel is the pixel
a window size of
3x3
and
is the
being
begins
This
analyzed.
at
pixel of
can
best be illustrated
interest
filled from the input
the time
at
the
the window,
center of
source.
when enough pixels
through the
The
example assumes
have been
read
to begin
processing.
Row 1
<
Row 1
Legend
Row 2
Pixel
Row 3
Interest
of
Row?
Window
Area
Row 1
Row 2
i
w m m m m
Row 3
Row?
RowX
Row
Pixel
Row 1
Being
Being
Row 2
Row 3
Row?
Figure 3.1
Local
Thresholding
34
Buffer Example (Row
1)
Filled
Filled
Row 2
Row 3
Row 1
Row 5
Row 2
Row 2
'
Row 3
Row 4
Row 3
Row 4
Row 5
^Row
Row 3
Row 4
Figure 3.2
The
interesting thing
begins to be
read
in.
Local
to note
Thresholding Buffer Example
from the
Since the
above
algorithm
illustration is
(Rows 2 &
what
happens
has finished processing
35
3)
row
when row
one, the
five
values
contained there
dimensional
begin to be
overwritten
matrix minimizes
by
the amount
the new values coming in.
of required storage within
Row 4
This
circular 2-
the algorithm.
Row 5
Row 5
Row 2
Row3
V
Row 4
Row 3
Row 4
UJ
Row 5
Row 5
Row 2
Row 3
Row 6 j
Row 3
Row 4
Row 4
Row 5
Row 6
Row 3
Row 4
Figure 3.3
The
above
illustration
back to the
Local
shows
beginning
implementation detail
as
Thresholding
how the
processing
calculating the
Buffer Example (Rows 4 &
window wraps around
continues.
from the
end of
This brings up the
window extremities
36
5)
for
each pixel.
next
the buffer
important
The
x coordinates
coordinate
is the
center pixel plus
the
bounds
rows
is
position within the
center pixel minus
(window
of the
used
image,
size +
then
for the ending
1)
row
horizontal
(window
/ 2. If the
1 is
used
size
row
1) / 2
calculated
easy to
limits
The
calculate.
the end
while
for the starting
depending
coordinate,
are
coordinate
of the window
the
x coordinate or
on which edge of the
lie
start
is the
outside
number of
image is
being
much
more
analyzed.
The y
coordinates
They
complicated.
incremented
and
vertical
An
decremented.
The MATLAB
in the files
A-2 & A-5
3.3
be
Again,
adjusted
overall row counter must
image is known in
addition
code
within
the circular buffer
be implemented using saturating
must
window coordinates must
image.
position
if the
be
be both
the fact that the
maintained so that the absolute position
in the
the
local thresholding
and can
and
at
top
or
buffer.
of the row within the circular
"myLocalX.m"
"myLocal3.m"
by
can
of the
versions of the
interest is
that
bottom
pixel of
to the relative position
for the two
counters
this is further complicated
are
be
seen
algorithm
is
contained
in Appendix A
on pages
respectively.
The running
average algorithm
pixels are analyzed as
they
are
is
similar
to the global thresholding algorithm in that
input. Storage
elements are still required
however to
track of the running averages for each row and column, which ultimately
new pixel value.
37
keep
determine the
The
buffer
size of the
required to
in the image. The first

second
Since
is
used
average
the pixels in the
of
pixels, the
the results
in the buffer is
this
used
is 2
algorithm
the
number of columns
to store the horizontal averages
while
the
to store the vertical averages.
no previous
horizontal
row
implement
information is
is
first
set equal
row are
the successive
quickly become
a more
to that pixel
running
rows, but
reading the first pixel,
value.
slightly biased
previous vertical
for
available upon
by
The horizontal
this assumption.
average was
as more
taken as
the
first
calculated
for
the rest of
averages
For
zero.
the entire
This slightly
image information is read, the
accurate representation of
image's light
the
first
row
affects
averages
intensity
at that
location in the image.
The weighting
equal
functions, f(
to 0.02 x (Current
coding
and
g( y
),
were
Previous Average).
and the calculation.
Although
in itself,
The MATLAB
file
which was
code
beyond the
for the running
"myRunningAvg.m"
and can
be
Using
as simple
could
linear functions, both
linear function
a more complex
better results, choosing the weighting function

project
taken
function
have been
might
simplified
have
the
produced
another entire research
scope of this project.
average
seen
thresholding
in Appendix A
38
algorithm
on page
A-9.
is
contained
in the
3.4 Quick Adaptive
Thresholding
As
2.2.3, choosing
stated
in
section
accesses the pixels plays an
since
it had been
used to
the way in which the quick
important
shown to produce the
determine
the
in the quality
role
best results,
of
that the
thresholding
the output.
alternating
It
algorithm
was
decided,
scheme would
be
new pixel values.
'
'p=x=
Figure 3.4
In
order
order
to
process
alternation.
information
is
the
storage rows
connectivity
this
Thresholding
the data stream continually.
Processing
end.
Quick
Pixel Analysis Order
to implement this alternating access method, some pixels must be buffered in
information is 2
the two
number of columns
in
occurs
the
row
available at
were
1, last
needs
size of
pixel, to
the buffer
in the image. To
implemented
repeatedly from
exists as row
One
buffer
The
start
row
to
to store this
the processing easier,
as one continuous
end of
2, last
make
required
the buffer
pixel, effectively
row, laid
end
to
in the center, the
implementing
the
to be read in advance in order to have the required
the time it is
needed.
accomplished.
39
The illustration below clearly
shows
how
Sample Image
1
Legend
>^ ^<
| 10 ]
11
13
14
15
16
17
19
; 20
21
i 22 ! 23 | 24
25
26
27
| 28 i 29 ; 30
31
! 32
33
34
12
18
^yp
-~-
13
13
14
'
'
>
-^
-~
4^4%
^Br^3
12
12
r^M
14
15
16
14
15
16
-"
| 12
^J
Pixel
Being
14
'
Interest
Filled
15
16
15
I 16
17
I 18 I 12 I 11 T 10
Y 17 Y 18 Y 12 Y
14
mum
14
15
14
15
16
^J
14
15
16
17
^^
15
16
17
13
11
Y 10
ie
o
|n
17
m>M
22
10
11
11
10
And
^^M
24
Quick
Thresholding Buffer Implementation
40
4Bp
19
19
21
: 21
20
22
so on...
12
Figure 3.5
25
18
::
r~-
r~*
-~
e
6
11I10I9I8T7
^M
o
of
"
fj
'
10
Pixel
| 35 | 36
M3!4!5!9!'!'!'!'!'
'
;:,;;;:
The
weighted
MATLAB
the
average
is
calculated
implementation,
simply
as
the percentage offset
described in
was
section
taken as a
2.2.3.
For the
parameter passed
into
function.
The MATLAB
code
for the
"myQuick.m"
and can
be
quick adaptive
seen
thresholding
in Appendix A
41
on page
algorithm
A-l 1
is
contained
in the file
Chapter 4: VHDL Implementation
In making the transition from MATLAB to

algorithms
state machines
functions
separate
using
of
parameters,
very well,
the
and
data
VHDL, it
path and control sections.
was
decided to implement
VHDL
synthesis
tools handle
so a simple state machine was created to separate the
algorithm
processing
reset, reading image
pixels.
width and
This fundamental
height,
reading
concept was utilized
the
in
different
algorithm
all
VHDL
implementations.
The
state
diagrams for the different
steps added or removed
based
on
algorithms are
the
essentially the
same with
number of parameters required
example, the state diagram for the global
thresholding
following page.
42
intermediate
to be read in. As
algorithm can
be
seen on
an
the
Note IS_DONE is
an
generated signal that

when
processing the
entire
DATA_VALID = '0
RESTTt^T
DATA_VALID =
RESEfb^'1
'0'
DATA_VALID
'0"
REST>?=T
Figure 4.1
State Diagram for VHDL Implementations
43
internally
determines
the algorithm has finished
image.
common
I/O interface
The details
mechanisms.
of the
Port
DATAJN
designed
was
I/O
can
be
Direction
[7:0]
be tested using
so that all algorithms could
seen
similar
in the table below:
Description
INPUT
The 8-bit information being
DATA_READY
INPUT
Indicates to the hardware that
RESETL
INPUT
Asynchronous
CLOCK
INPUT
System
present at
DATAJN
clock
read
in
data is
valid
[7:0]
reset
device is driven
clock and must
be in
by
an external
sync
with
the device
if
the
supplying the data
DATAOUT
OUTPUT
DATAJVALID
OUTPUT
Binary pixel data output

Single
bit
indicating
DATAOUT is
receiver of the
DONE
OUTPUT
Asserted
Since
implementing floating
were used where
floating
truncation occurred, but
point
point
be
read
the
the entire
by the
algorithm
has
finished
image
I/O List
in VHDL is complicated, integer divide
divisions
on
information
when
processing
Table 4.1
valid and should
data
were
in MATLAB.
Some
places where margin was
already
previously
added additional margin
in
operations
used
being applied.
For
each of the
number of
hardware,
four algorithms,
columns,
and
the
an
'end
nature of
is
pixel'
the
algorithm.
and when this counter equals the
allowing the
discussed in
state machine
more specific
calculated
based
counter
on
is
the
number or
rows,
maintained within
'end pixel', the ISDONE
signal
is
the
asserted
to exit the Process state and enter the Done state. This will be
detail in the
sections
44
below.
Testing
the VHDL code was accomplished through the use of a testbench.
of
testbench reads in
text file.
new
can
value, image
be
the file
simple
text file and sends the
ASCII image format is
including
image information to
VHDL I/O
operations.
be
designation,
the
ASCII text
The VHDL testbench is
seen
for testbench implementation
and all pixel values are given as
and can
in Appendix B
on page
maximum
values and
contained
B-l
in
Thresholding
global
Process
The
used
new
the image format
"thresholdingtestbench.vhd"
Since the
out.
.ppm
dimensions,
in using
read
4.1 Global
one
The
Image information
simplicity.
pixel
image data from
The
thresholding
When
state.
end pixel
is
algorithm requires no
being
valid pixels are
calculated
simply
as
the
internal
read
in,
space, there is only
storage
valid pixels are also
number of rows multiplied
being
by the
sent
number
of columns.
END
PLXEL
Equation 4.1
The VHDL
code
for the
Global
quick adaptive
"globalthreshold.vhd"
and can
4.2 Local
NUM
be
seen
ROWS NUM
Thresholding End
thresholding
in Appendix B
COLS
Pixel
algorithm
on page
is
B-21
contained
in
the
file
Thresholding
In the local thresholding algorithm,

valid pixels can
be
sent
to the
a certain number of pixels must
output.
As
45
result, two Process
be
states
read
in before
Process 1
and
Process2
are created
in the
in Process2 it is
while
account
extra time at the
END
PIXEL
((NUM
T.
equal to
for the
(NUM
The
DATAVALID is
be
end pixel must
ROWS NUM
EACH
EACH
calculated
equal
to
'0'
accordingly to
COLS) +
SIDE) + (NUM
where
Processl,
beginning.
COLS NUM
NUM
In
state machine.
SIDE
EACH
SIDE +
_
1))
WINDOW
SIZE
-I
2
Equation 4.2
Local
Thresholding
In the local thresholding implementation with fixed

each side of the center pixel
for the two
versions
is known
of the
"local_rhreshold_3.vhd"
so
it
4.3
B-26 & B-36
window
size, the number of pixels
makes the calculation easier.
local thresholding
is
algorithm
"local_threshold.vhd"
and
pages
End Pixel
and can
be
The VHDL
contained
seen
on
code
in the files
in Appendix B
on
respectively.

is
The ninning
average
algorithm
information is
required
to be stored; therefore the
exactly the
contained
page
same.
The VHDL
in the file
code
similar
for
the
to
global
thresholding in
equation
running
for calculating
average
"mnning_avg_threshold.vhd''
and can
B-46.
46
that no
the end pixel
is
algorithm
is
thresholding
be
seen
pixel
in Appendix B
on
4.4 Quick Adaptive
The
quick adaptive
in before the
Thresholding
thresholding
pixels can
END
be
algorithm requires that one complete row
processed.
PIXEL
NUM
The VHDL
code
for the
ROWS NUM
Equation 43
Therefore, the
Quick
quick adaptive
"quickthreshold.vhd"
and can
be
seen
is
end pixel
COLS
has been
read
given as:
NUM
COLS
_
Thresholding End Pixel
thresholding
in Appendix B
47
algorithm
on page
is
B-52.
contained
in the file
Chapter 5: FPGA Synthesis
In
the transition
from VHDL
that the native VHDL arrays
algorithms were
FPGA
being
be
could
could
be
being
physically
FPGA synthesis, it
used as storage elements
from the
constructed
in the
standard
logic
fit inside the target FPGA

As
processed.
processed
using the
result, limits
physical
and
consequently the
were placed on
the
discovered
was
thresholding
adaptive
than the specific memory cells. This severely limited the
rather
elements that could
that
software simulation to
in
elements
the
number of storage
size of
size of the
the images
images that
hardware.
5.1 Test Hardware

Altera'
Nios Development Kit
processing
It has
and
is
connectivity
moderately
fairly
of uses
This kit
kit containing
complete
required
algorithms.
in
was used as
was chosen
for
development board
hardware, development
sized consumer grade
inexpensive. Overall it is
undergraduate
the hardware
a number of reasons.
which
software,
FPGA,
flexible
on which
interfaces
and
full
directly
good
of
image
all, it is
to a
PC,
all
documentation.
(EP20K200EFC484),
platform which could
run the
First
product
the APEX 20KE
classes, and this was
to
have
opportunity to
a wide range
evaluate
its
performance.
One
unknown at
had been
written
convenient
the
beginning
of
to the hardware.
the
project was
how to test the
The Nios development board
way to do this.
48
algorithms once
provided an
easy
they
and
The development board itself has
5V tolerant header for accessing
all of the
I/O
pins of
the FPGA device. This made it possible to implement a TTL logic interface to the FPGA
which could
LEDs for
be driven
debugging
information to
schematic of
code
and
by
a simple
purposes,
from
the
and
program.
FPGA through the
and
of
An interface board
program
the TTL interface can be seen on the
for the implementation
30, C-37,
49
written
which
transferred
parallel port of a standard
following
the I/O interface can be
C-44.
was
was created with
seen
page
PC.
The
in Figure 5.1. The C
in Appendix C
on pages C-
$ I
D7
DataT71
D6
D4
D5
D3
$
D1
D2
do
<9>
Data|6]
<8>
Data[5]
<7>
Data[4]
<6>
Data|3)
<5>
Data:2;
<4>
Data[l]
<3>
Data{Ol
<2>
.
<?
<
DATA READY
<14>
/JesrapK
v:.
DATA VALID
'
<15>
'
R19
,
Status(5]
<12>
'
DONE
Status[3]
Status|6]
<10>
,
Figure 5.1
Interface Board Schematic
50
5.2 Global
Thresholding
The
thresholding
global
simulated
work on
VHDL.
algorithm was
Since
storage elements were not required
images up to the
integer in VHDL. The
be
seen
53 Local
synthesized
on page
of the
C-l
VHDL for the
local thresholding
global
algorithm
It
to simplify the calculation of the threshold.
For these two reasons, it
was not possible
to 3 pixels square, it would
reason
was created
for this is
to
apparent
separate
It
the
upper
thresholding
bound
of
algorithm can
cycle,
state,
or clock cycle
with nine read ports.
so one write port on
window
known
when
would also
51
3x3,
in this
In addition,
the RAM
stated
size
that the
was
largest
the image size was
a state machine
calculation of the
there are a maximum of nine
case.
a write
be
before,
In the
of the algorithm.
accesses
RAM
Even
in the implementation. As
total memory
use of a
was also
written.
a given pixel and a given widow size of
one
fixed
the greatest
not synthesize.
the different functions
in
that
provided
to implement the local threshold algorithm
threshold, for
same
by
the most complicated memory accesses.
using the behavioral VHDL that had already been
the
could
in hardware
was clear
amount of storage space was required as well as
The
for this algorithm, it
the entire project.
challenge throughout
shrunk
to the
Thresholding
The implementation
required
with no changes
maximum specified size which was set
an
in Appendix C
implemented in hardware
This
would
have
required
to the memory occurs in the
needed.
Even using the
implementation
standard
to work.
this algorithm in
modules
There
provided
two ways
are
hardware. One way
would
their own clock cycle,

effectively adding 8
the input
and output
pixel value would
be
timing
every
change such that one value was read
interface
a standard
The
second
If a faster
way
was used
would
be to
for
all
clock
Since only
and output
This
was
Units
of
data
further
VHDL
which
allowed
read
in
This
to implement
reads
to
would change
per clock cycle while a new
The input timing
would
have had to
to match the output timing.
was not
this
really
Since
an option.
the FPGA
or
could
be
driving two
realized
distinct
get nine values out
a divide-
by implementing
clock signals
to both drive the algorithm
in
into the device.
and synchronize
the
neither of these solutions are possible.
complicated
code
by
for specialty
is designed to
they
be
nine cycles
This
utilize
an
incomplete development
modules such as
could not
be
RAM
environment.
cells and
modules were not available on
simulated
52
Since the
the development
properly in the development
project.
Altera
Arithmetic Logic
the hardware optimally when synthesized.
VHDL libraries for these specialty Altera

workstation,
worked
RAM, it would be possible to
one external clock was used
input
provides
inside
have
have
the state machine and the RAM using different clocks.
clock was used to clock the
counter
not
to the execution.
stages
algorithms, this
one clock cycle of the state machine.
by-nine
which could
nine cycles.
every
could
be to completely isolate the memory
one pixel would
created once
Altera
by
stages of the
As
result,
it
decided that the local thresholding
was
implemented in hardware because it

VHDL
and
the I/O
local thresholding
5.4
interface
would require a complete
code.
The
be
seen
algorithm can
restructuring
of
both the
code on which synthesis was attempted
in Appendix C
on page
be
not
would
algorithm
for
the
C-6.
The
quick adaptive
thresholding
the simulated version.
integer divide
The operating image
operations were replaced
effectively turning it into
implementing
situation.
seen
The
algorithm was
synthesized
The
thresholding
average algorithm.
VHDL for the
were
quick
where
If
with minimal changes
to 127
pixels square and all
the divisor
is
a power of
a structural approach was
module could
average
from
have been
thresholding
two,
taken in
used
in this
algorithm can
be
C-17.
Thresholding
divide functions
divider
standard
5.5 Quick Adaptive
running
divisions
VHDL for the running
on page
quick adaptive
size was reduced
a simple shift operation.
this algorithm, a
in Appendix C
implemented
algorithm underwent
The image
changed
size was
to divide
thresholding
by
same
basic
be
changes as
decreased to 127x127
a constant power of
algorithm can
53
the
seen
2.
in Appendix C
and
The
the
the integer
synthesized
on page
C-23.
Chapter 6: Results and Analysis

The resulting images from
images
from
were used
the
this project can
to test the
thresholding
be
seen
due to its
No
algorithms.
hardware for the local thresholding
synthesize
in Appendix D. In
algorithm
output
end, 20
the
images
sample
were obtained
because the VHDL
would not
complexity.
6.1 General Conclusions

The resulting images
Some
nature.
cannot
analyzed
user
window
size,
thresholding
noise
project and
Given
can
be greatly
themselves
therefore no
situations.
fashion due to
about the
their subjective
differences between the four
algorithms
with
varying
is very
reduced
different input
images using
produce
clean
54
each
image
to
noise.
which
given
The
parameters
quick
output,
is
3x3
By increasing the
the threshold for any given
larger
From the resulting images obtained, the
for
intensity. With the
susceptible
since
input parameters, the
both
average
taken over a larger area.
given
additional
a conservative set of
thresholding
be drawn
algorithm
represents a more accurate average
algorithms against
a qualitative
to choose an appropriate threshold
be done optimally for images
window, the local
in
the global scheme is the simplest and produces clean results, but
intelligent
requires an
be
general conclusions can
Clearly
algorithms.
must
performance of
not
the focus
pixel
these
of
this
window size were produced.
thresholding
and
running
each of which excel
quick
thresholding
average
in different
algorithm seems
to handle images
better,
while
the running average method produces
cleaner output on
pages with pure text.
6.2 Quantitative Results

In the modeling stage, the
for
shows the runtimes
runtime of each algorithm was recorded.
each
image
and the
corresponding
# Pixels
size of each
Time
following
(Seconds)
Running
Width
Height
Global
Local
01_test.j P9
02_test.j pg
03_test.j pg
04_test.j pg
05_test.j pg
06_test.j pg
07_test.j pg
08_test.j pg
09_test.j pg
10_test.j pg
11_test.j pg
12_test.j pg
13_test.j pg
14_test.j pg
15_test.j pg
16_test.j pg
17_test.j pg
18_test.jpg
400
525
20
304
70
172
400
518
14
309
69
171
400
518
16
339
73
177
400
530
18
324
68
183
400
526
18
311
72
184
400
547
20
312
75
191
400
550
20
367
75
206
400
529
18
285
76
162
400
529
18
283
69
167
400
533
17
283
70
153
400
523
19
282
68
157
400
518
15
289
62
170
400
533
19
286
66
174
400
533
19
292
68
171
400
245
138
30
76
400
536
18
298
71
175
540
540
17
449
90
239
540
540
18
427
98
249
rockefeller.jpg
960
1280
225
1482
451
941
yankees.jpg
1280
960
176
1490
441
932
following
table shows the
synthesized algorithms.
no synthesis
data is
Again,
Algorithm Runtime
clock speed and
the local
55
Quick
(MATLAB)
FPGA logic
thresholding
available.
table
image.
Image
Table 6.1
The
The
utilization
for
algorithm would not
each of
the
synthesize,
so
Algorithm
Utilization
Frequency
Global
62.1 MHz
Local
:-'
Quick
Average
Running
Table 6.2
M;-
(%)
7.12
:
;-/\r
21.4 MHz
58.52
17.6 MHz
89.76
Synthesis Results
6.3 Analysis
Each
continuous streams of
enough
data. Some
data had been
infinity however,
More
in this
of the algorithms used
read
project are single pass and can operate on and produce
of
to begin processing.
each algorithm requires
complex adaptive
thresholding
repeatedly to determine the
single and multiple
pass cases
since
the integer
number
slower clock
process an
is
nested
images
particular pixel.
of order
not considered
frequency,
temporarily
until
0(n),
in the
to
complete.
or scan pixel
data
For both types
even
in the
multiple
The
complexity.
of
more
must complete more actions per clock
and
therefore
will
take longer
overall
to
image.
with a
for loops
for any
because they
stored
the number of pixels approaches
algorithms store whole
The ideal design for the local thresholding

implementation
be
pixels
number of clock cycles
pass, the complexity is
complex algorithms are still slower
cycle, resulting in a
As
the same
optimum threshold
algorithms,
completely
them require that
fixed
window size.
which worked
great
in
algorithm
would
The behavioral
simulation
56
but
have been
code
a pipelined
that was written used
would not synthesize
these
statements
on
the
frequently
FPGA,
Even though
were met
while
the
synthesize
making
to asynchronous
circuit
local thresholding
successfully.
logic
algorithm would not
Three relatively
to illustrate the benefits of using
algorithms
design
all
both
the way to a
matters, but the
gained
qualitative and
along the
physical
process of
take up too
much real estate
timing uncontrollable.
complex
implemented in VHDL using purely behavioral

order
and
VHDL,
quantitative,
image processing
57
algorithms
and
the trials
the
of
taking
project
it's
experience and
not
were
to hardware in
the comparative performance
and
way.
project objectives
code and synthesized
implementation. In this
getting there
synthesize, the
of
the three
high level VHDL

the end
result
knowledge that
that
was
References
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Rochester Institute of Technology

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VHDL implementation and synthesis of adaptive

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VHDL Implementation and Synthesis

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Rochester Institute of Technology

VHDL Implementation and Synthesis of Adaptive Thresholding

world of mobile multimedia

small, high performance, low

computing technology is growing, the hardware

the Excalibur NIOS

Of the four algorithms, the local thresholding

algorithm would not

algorithms were synthesized

the remaining three

describes the implementation

therefore has become

of these algorithms must

more recent applications.

Altera 20K200E FPGA

due to the high-level VHDL

implementation. The remaining three,

were synthesized and written

to the target device

the devices on the FPGA

1.3 Development Hardware

1.4 Related Work

Related Work in Adaptive

Thresholding A Global Scheme

Chapter 5: FPGA Synthesis

5.1 Test Hardware

6.1 General Conclusions

Altera Excalibur NIOS Development Board

Thresholding Buffer Example (Row 1)

State Diagram for VHDL Implementations

Interface Board Schematic

Table 4.1-1/0 List

Local Variance Equations

Pietaksinen's Local Variance Equations

Thresholding End Pixel

Roy Czernikowski for

Tolleson for supplying

members, Dr. Ken

their guidance throughout this project, and Richard

Bell from Altera Corporation for providing the

thanks goes to Brian

HDL (Hardware Description

Programming methods include behavioral, dataflow,

PDA (Personal Digital

computing device that

numerical calculations with matrices

Binarization technique whereby

the threshold between black and

whereby the threshold for

management and portable multimedia capabilities.

An engineering tool for performing

hardware description language.

FPGA (Field Programmable Gate

hardware description language

a predetermined global value

the image binarization