Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September 1 October 2014

Simplified FPGA implementation of the generalized

space vector pulse width modulation (GSVPWM)
for three wire three-phase inverters
Jose Restrepoa,b,c, Julio Violaa,b , Flavio Quizhpib
a

Prometeo-SENESCYT, Quito-Ecuador
Universidad Politecnica Salesiana, Cuenca-Ecuador
c
Universidad Simon Bolvar, Caracas-Venezuela
email:restrepo@ieee.org,{jviola, fquizhpi}@ups.edu.ec
b

AbstractThis paper presents the development and implementation on a low-cost FPGA, of a fast generalized space vector
pulse width modulation (GSVPWM) scheme. The implemented
pulse width modulation uses a standard carrier-based triangle
interception method (SPWM).

I. I NTRODUCTION
The widespread use of advanced microprocessor and field
programmable logic array (FPGA) is providing industry and
academia with low cost access to high-performance reconfigurable devices for its use in digital controllers for power
electronics applications. Most of these applications need to
control a power stage, composed of an array of power-switches
(power BJTs, power MOS, IGBT, etc.), such as the three phase
converter shown in Fig. 1. There are different ways to link
the digital controller and the power stage, and for three-phase
converters the most common linking unit is a pulse width
modulation (PWM) module. There is large amount of research,
done since earlier works in speed drives by Schonung [1], on
different ways to produce efficiently the signals of the PWM
module. Injecting zero sequence components is one of the
most important improvements of the PWM module, leading to
an increased dynamic range of the modulator. Later, the space
vectors theory provided another extension, with the concept
of space vector pulse width modulation (SVPWM). However,
this modulation technique imposes a large computational load
on the central processing unit.
Modern industrial processors include PWM modules, freeing the central processing unit of the burden of producing
the gating signals for the power stage. However, hardware
solutions for advanced space-vector techniques are not available at the moment. Thus requiring additional processing time
devoted to calculate and carry-out the algorithms for these
advanced techniques; several algorithms does not even use the
standard carrier-based triangle interception method found in
most modern processors.
This paper proposes the implementation of the GSVPWM
algorithm, into a low cost FPGA, a Xilinx Spartan 3
(XC3S200). This algorithm has the advantage of changing
modulation strategies by just changing a parameter known as
null vector ratio , as described in the next section.

AH

VDC

BH

CH

BL

AL

CL

GN D

Fig. 1: Typical three-phase three wire voltage source inverter.

A. Generalized Space Vector Pulse Width Modulation

The three-phase three wire converter shown in Fig. 1 has
only 8 valid states, ~v0 to ~v7 as shown in Fig. 2, out of the 64
possible states. Using pulse width modulation, the voltage at
each phase can take any value in an averaged sense in the range
[0 VDC ], and with transformation (1), this will produce a
space-vector with coordinates falling inside the hexagonal area
shown in Fig. 2.
Modern control algorithms use a space vector description of
state variables such as currents, voltages, or fluxes. The following transformation [2], [3], known as Clarke transformation,
is commonly employed in three phase systems.


f~ = fa a0 + fb a1 + fc a2 ,
where a = ej 2
3 , and usually takes the values 1,

(1)

2
3

or

2
3.

The voltage demand for each phase of the converter can

be normalized by VDC , the resulting space-vector, for lineal
operation, falls inside the normalized hexagonal space shown

Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September 1 October 2014

TABLE I: Typical modulation methods using the generalized

algorithm.

replacements

~v3

~v2

~v
~v0

~v4

~v1

0
1
2
3

Modulation
DPWMmax
DPWMmin
SVPWM
DPWM0

DPWM1

DPWM2

0
1
1
1
2
1
2

1
2
1
2

2


N1
1 + (1)N 

 1 + (1)

(N1 +1)
1 + (1)(N +1) 
2

1 + (1) 2
6
DPWM3
For (x, y) coordinates:
N1 = 2.5 sign(fy ) [(fx > fy ) + (fx > fy ) + 0.5]
N2 = 3.5 sign(fx + 3fy ) [(fx > 0) + (fx > 3fy ) + 0.5]

~v6

~v5

Fig. 2: Representation of the space vector loci for the three

phase converter.

Fig. 3a shows an example of the control signals that must be

applied to the power devices in each branch when a PWM with
central symmetry is used. In this example the average voltage
space vector reference is such that Da < Dc , N1 = {5, 6},
branch b is in low state and the null vector is synthesized with
state (0,0,0). In this case the possible firing sequences are:

in Fig. 2. The per unit vector is,

~vpu =vx + jvy =
1

1
VDC

vaN a0 + vbN a1 + vcN a2 =


(va vN ) + (vb vN ) a + (vc vN ) a2 =
VDC


= D a + D b a + D c a2 ,
(2)
=

where Da , Db and Dc are the duty cycles for the respective

phases.
Several works have been devoted to developing simple
algorithms for generating the gating signal for the converter,
conforming to different space-vector methods, the most common of which are, DPWMmax , DPWMmin , DPWM0 , DPWM1 ,
DPWM2 , DPWM3 , and the most widely used is SVPWM [4]
[10].
Since modern control strategies describe the state variables
using complex notation in the form f~ = fx + jfy , the chosen
algorithm should exploit this variable description, using x, y
coordinates. The modulation method can be easily selected
using a single parameter, known in literature with different
names as: zero state partitioning 0 and 7 [5], parameter
[6], and null vector ratio [9].
The duty cycles for the VSI switches in the generalized
vector based algorithm are obtained by doing the following
change of variables in (2),
fx = vx ;

vy
fy = .
3

B. Examples of firing sequences

(3)

In this work the null vector ratio will be employed to select

the modulation method. The variation of the null vector ratio
, representing the zero state partitioning, during the switching
period, yields an infinite number of modulation possibilities.
The value of for most common modulation methods is shown
in Table I [9].
The expressions for the duty cycles, as a function of the
null vector ratio and of N1 in Table I, are shown in Table II.

firing sequence
~v6 ~v5 ~v0 ~v5 ~v6
~v6 ~v1 ~v0 ~v1 ~v6
~v6 ~v0 ~v6

condition
Da < Dc
Da > Dc
Da = Dc

Fig. 3b shows an example of an average vector such that

Da < Dc , N1 = {1, 2}, branch b is in high state and the
null vector is synthesized with state (1,1,1). In this case the
possible firing sequences are:
firing sequence
~v7 ~v4 ~v3 ~v4 ~v7
~v7 ~v2 ~v3 ~v2 ~v7
~v7 ~v6 ~v7

condition
Da < Dc
Da > Dc
Da = Dc

Fig. 3c shows an example of an average vector synthesized

with N1 = 2, and the null vector is equally synthesized
using space vectors ~v0 and ~v7 . In this case the possible firing
sequences are:
firing sequence
~v7 ~v4 ~v3 ~v0 ~v3 ~v4 ~v7
~v7 ~v4 ~v0 ~v4 ~v7
~v7 ~v3 ~v0 ~v3 ~v7
~v7 ~v0 ~v7

Da
Da
Da
Da

condition
< Dc < Db
< Db = Dc
= Dc < Db
= Dc = Db

Fig. 3c shows the case when = 12 and Da < Dc < Db .

Figs. 4a-4c show the typical duty cycles required to produce
a maximum amplitude circular trajectory of the voltage space
vector for the three previously discussed methods [10]. The
circular trajectory is generated in the (x, y) plane using the
following expression,

3 jt
~vpu (t) = vx + jvy =
e .
2

(4)

Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September 1 October 2014

TABLE II: Expressions for duty cycles required in the practical implementation of the generalized algorithm.
N1
0
1
2
3
4
5

v5
~

~
v6

~
v5

~
v0

Da
(fx + fy 1) + 1
Db + fx fy
Db + fx fy
Dc + fx + fy
Dc + fx + fy
(fx fy 1) + 1

~
v6

Db
Da fx + fy
(2fy 1) + 1
(fx + fy 1) + 1
Dc + 2fy
Dc + 2fy
Da fx + fy

v4
~

~
v7

1
D2b
D2c

1
D1c

~
v4

~
v7

~
v7

~
v4

~
v3

Dc
Da fx fy
Db 2fy
Db 2fy
(fx fy 1) + 1
(2fy 1) + 1
Da fx fy

v3 ~
~
v3
v0 ~

~
v4

~
v7

1
D3b
D3c

D1a
D1b

D2a
t0

t1

t2

t
t5 t0 + Ts

t4
Ts /2

t0

(a) Generalized method with = 1

t1

t2

t D3a
t0
t5 t0 + Ts

t4
Ts /2

(b) Generalized method with = 0

t
t1 t2 t4 t5
Ts /2

t0 + Ts
1
2

(c) Generalized method with =

Fig. 3: Firing sequence for a PWM with central symmetry.

1
D1c

0.8

Duty Cycle

Duty Cycle

D1b

0.6
0.4

Duty Cycle

D1a

0.8
0.6
0.4
0.2

0
0.04

0.06

Time (s)
(a) Duty Cycle for = 1

0.08

0.1

0.4

0
D2a

D2c
0.02

0.6

0.2

0.2

0.8

0.02

0.04

0.06

0.08

Da

Dc

D2b
0.1

0.02

0.04

Db

0.06

0.08

0.1

Time (s)

Time (s)
(b) Duty Cycle for = 0

(c) Duty Cycle for =

1
2

Fig. 4: Modulation waveform for a maximum amplitude circular trajectory of the inverter voltage space vector in SVPWM
with (a) = 1. (b) = 0. and (c) = 12 .
C. Over-modulation
Any per carrier period average space vector located outside
the hexagonal area is not achievable with the VSI shown
in Fig. 1, since the demanded duty cycles are outside the
operational range of the modulator. The space-vector falling
outside the hexagonal area, in Fig. 2, needs to be adjusted
for proper operation of the modulator circuitry [5], [11],
[12]. There are several possible ways to adjust the duty
cycle demand to be fed to the modulator circuitry. A simple
approach is to clip the per phase requested duty cycle to be
inside the range 0%-100%. Another option is to clip the space
vector magnitude to the maximum achievable by the converter,
while keeping the reference voltage space vector angle; this
limiting strategy corresponds to the over-modulation in mode
I, described in [11]. Fig. 5 shows the effect of using these two

limiting strategies when the required voltage space vector falls

outside the hexagonal area. This work uses the field weakening
over-modulation strategy proposed in [12], corresponding to
~vr2 in Fig. 5.
II. FPGA

IMPLEMENTATION OF THE

GSVPWM

ALGORITHM

The duty cycle generation for the GSVPWM algorithm

presented in the previous section is implemented using the
industry standard hardware description language VHDL [13],
[14], the block diagram of the duty cycle algorithm for the
GSVPWM is shown in Fig. 6, made of 3 main units, in charge
of intermediate computations required by the algorithm. The
first unit receives the normalized demands for the x and y
components of the space vector, and generates the following

Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September 1 October 2014

y
~v3
~vr2

~v
~vr1

~v1

~v5

Fig. 5: Limiting strategies for overmodulation showing the

required space vector ~v and the resulting vectors using rescaling ~vr1 and clipping ~vr2 .

fx
intermediate
variables
fy

select

=0
=1
=

Range

Scaling

[Da , Db , Dc ]

Output

1
2

Fig. 6: Block diagram of the GSVPWM.

intermediate signals, using the fixed point VHDL language

[14] with the ieee proposed library [15].
k1 <= to_sfixed(0.33333333333,0,-15);
k2 <= to_sfixed(0.577350269,0,-15);
fx <= to_sfixed(x,0,-15);
fy <= to_sfixed(y,0,-15);
iy <= resize(fy*k2,0,-16);
fx3 <= resize(fx*num1,0,-16);
fa1 <= fx + iy;
fb1 <= fx - iy;
fa1_2 <= resize(fa1 sra 1,1,-16);
fb1_2 <= resize(fb1 sra 1,1,-16);
fa2 <= fx3 + iy;
fb2 <= fx3 - iy;
fy2 <= resize(iy sla 1,1,-16);
The input variables to the GSVPWM module are the variables fx and fy in Q15 fractional format, the modulation
method selector and the maximum value for the carrier
counter in the PWM module. The second unit computes the

values of sector related variable N1 and N2 , from Table I,

and in conjunction with the modulation method selector
fixes the value for the null vector ratio . Since the space
vector modulation methods presented in Table I are generated
using the instantaneous values {0, 0.5 and 1} of the null
vector ration , the third unit is a selector for the DP W Mmin ,
DP W Mmax or SVM methods. The final unit computes the
resulting duty cycles using the proper value of , according to
the previous unit, using the equations in Table II, and scales
the output values for their use by the triangular intersection
PWM module.
III. S IMULATION AND E XPERIMENTAL R ESULTS
The VHDL algorithm for the GSVPWM has been simulated
using GHDL and GTKwave [16] and implemented using
Xilinx ISE 14.7. on a custom made prototype [17] hosting
a Xilinx Spartan 3 XC3S200-4 composed of 4.320 logic
cells, each constituted by two 16 1 lookup tables (LUTs)
and two flip-flops. This FPGA includes twelve 18 18
hardware multipliers, twelve 18-kb blocks of random access
memory. The module uses a 40 MHz clock, which is also
used for clocking a standard triangular comparison PWM.
Table III shows the module level utilization report for the
FPGA implementation of the GSVPWM algorithm.
TABLE III: Device utilization.
Slices
Slice Regs.
LUTs
MAP MULT 18x18

714
65
1341
5

A. Simulation results
The algorithm is simulated for four modulation methods,
DP W Mmin , DP W Mmax , SVM , and DP W M 0. The simulation conditions are the same during the four tests, and
a circular trajectory x = 0.7 cos(), y = 0.7 sin() is fed
to the GSVPWM module in each case. Figure 7 shows the
waveforms for the modulation method DP W Mmin , selected
with parameter = 0. In this case the algorithm keeps
= 1, constant for the test duration. Figure 8 shows the
waveforms for the modulation method DP W Mmax , selected
with parameter = 1. The value of the null vector ratio is
keep constant, by the algorithm, at value 0 for the duration of
the test. For the third test = 2 selects the traditional SVM
algorithm, the waveforms for this test are shown in Fig. 9. In
this case a digital representation of 2 for maps the operations
shown in Table II when = 21 , and this value is kept constant
by the algorithm for the duration of the test. The waveforms
for last test, DP W M0 method selected with = 3, is shown
in Fig. 10. In this case the algorithm assigns = 1 when the
sector selector N 1 is even, and = 0 when N 1 is odd.
B. Experimental results
An exhaustive test comprising an array of 12.576.769
different space vectors for a PWM module of 11 bits was
implemented. For this test the hexagonal space is divided in
three zones, and the test vectors are programmed as follows,

Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September 1 October 2014

Time
Time

delta[1:0]=1
gamma[1:0]=1
n1a[2:0]=4
n2a[2:0]=6
pwmmax[-1:-12]=3E8
fx[0:-15]=0

100 us
1
1
0
1 2
3E8

200 us

2
3

300 us

3
4

400 us

500 us

0
1

1
2

600 us

2
3

700 us

3
4

4
5

delta[1:0]=1
gamma[1:0]=3
n1a[2:0]=4
n2a[2:0]=6
pwmmax[-1:-12]=3E8
fx[0:-15]=0

100 us
1
3
0
1 2
3E8

200 us
1

2
3

300 us

3
4

4
5

400 us
0

500 us

5
6

0
1

1
2

600 us
1
2

700 us

3
4

4
5

iy[0:-15]=-0.700012
iy[0:-15]=-0.700012

dax[1:-15]=3223
dax[1:-15]=3223

Fig. 10
Fig. 7

Time

delta[1:0]=0
gamma[1:0]=0
n1a[2:0]=4
n2a[2:0]=6
pwmmax[-1:-12]=3E8
fx[0:-15]=0

100 us
0
0
0
1 2
3E8

200 us

2
3

300 us

3
4

400 us

500 us

0
1

1
2

600 us

2
3

700 us

3
4

4
5

iy[0:-15]=-0.700012

dax[1:-15]=4757

Fig. 8

Time

delta[1:0]=2
gamma[1:0]=2
n1a[2:0]=4
n2a[2:0]=6
pwmmax[-1:-12]=3E8
fx[0:-15]=0

100 us
2
2
0
1 2
3E8

200 us

2
3

300 us

3
4

4
5

400 us

5
6

500 us

0
1

1
2

600 us

2
3

700 us

3
4

4
5

// First parallelogram
for(i=0;i<PWMMAX;i++)
for(j=0;j<PWMMAX;j++)
{
fx=(i-0.5*j)/(float)PWMMAX;
fy=(j*M_SQRT3_2)/(float)PWMMAX;
}
// Second parallelogram
for(i=0;i<PWMMAX;i++)
for(j=1;j<PWMMAX;j++)
{
fx=(-0.5*i-0.5*j)/(float)PWMMAX;
fy=(M_SQRT3_2*(i-j))/(float)PWMMAX;
}
// Third parallelogram
for(i=1;i<PWMMAX;i++)
for(j=1;j<PWMMAX;j++)
{
fx=(i-0.5*j)/(float)PWMMAX;
fy=(-j*M_SQRT3_2)/(float)PWMMAX;
}

where
PWMMAX is the PWM scale and M SQRT3 2 is equal
to 23 . The result obtained with the FPGA are compared with
the ones generated with the DSP based controller, and have a
less than 1 bit error.
The duty cycle information in the P W M gate signals
corresponds to the modulation information, and can be easily
recovered with a low pass filter. Fig. 11 shows the filtered
version of the PWM gate pulses for the standard SVM
modulation method. The low pass R-C filter parameters are:
R=2 k and C=200 nF.
IV. C ONCLUSION

iy[0:-15]=-0.700012

dax[1:-15]=3990

Fig. 9

This paper has presented a fast implementation of the

generalized space vector PWM for FPGA suitable for space
vector demands in x, y coordinates. The proposed algorithm
permits an on-flight change of the modulation method, that
can be exploited for efficient modulation applications [18].
Also, the FPGA implementation of the GSV P W M frees the
processing unit of the computational load required to execute
this algorithm.

Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September 1 October 2014

Fig. 11: Filtered PWM gate pulses for the standard SVM.

ACKNOWLEDGMENT
The authors gratefully acknowledge the support of Prometeo
Project, Secretara de Educacion Superior, Ciencia, Tecnologa
e Innovacion, and Universidad Politecnica Salesiana, both
in Republica del Ecuador, as well as the Deans Office for
Research and Development of Universidad Simon Bolvar and
FONACIT Research Project #2011000970 both in Venezuela.
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