Sri Lanka Institute Of Information Technology

Lab 7

EC304 Physical and Opto Electronics

Name

: H.M.N.S.S.B Herath

Registered No

: EN13530518

Course

: BSc in Engineering

Field of Specialization

: Electrical and Electronic Engineering

Abstract

The purpose of this lab is to explore the operation of MOSFETs. The operation of the MOSFET will be
investigated under the DC operation conditions. And to analyse characteristics of a MOSFET by
measuring VDS, VGS and ID.

Introduction

The metaloxidesemiconductor field-effect transistor (MOSFET) is a transistor used for amplifying

or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can
induce a conducting channel between the two other contacts called source and drain. The channel can
be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figure 1 shows the
schematic diagram of the structure of an nMOS device before and after channel formation.

Figure 1
Output Characteristics of a MOSFET
The characteristics of an nMOS transistor can be explained as follows. As the voltage on the top
electrode increases further, electrons are attracted to the surface. At a particular voltage level, which
we will shortly define as the threshold voltage, the electron density at the surface exceeds the hole
density. At this voltage, the surface has inverted from the p-type polarity of the original substrate to an
n-type inversion layer, or inversion region, directly underneath the top plate as indicated in Fig. 1. This
inversion region is an extremely shallow layer, existing as a charge sheet directly below the gate. In the
MOS capacitor, the high density of electrons in the inversion layer is supplied by the electronhole
generation process within the depletion layer. The positive charge on the gate is balanced by the
combination of negative charge in the inversion layer plus negative ionic acceptor charge in the
depletion layer. The voltage at which the surface inversion layer just forms plays an extremely
important role in field-effect transistors and is called the threshold voltage Vtn. The region of output
characteristics where VGS<vtn</v and no current flows is called the cutt-off region. When the channel
forms in the nMOS (pMOS) transistor, a positive (negative) drain voltage with respect to the source
creates a horizontal electric field moving the electrons (holes) toward the drain forming a positive
(negative) drain current coming into the transistor. The positive current convention is used for electron
and hole current, but in both cases electrons are the actual charge carriers. If the channel horizontal

electric field is of the same order or smaller than the vertical thin oxide field, then the inversion
channel remains almost uniform along the device length. This continuous carrier profile from drain to
source puts the transistor in a bias state that is equivalently called either the non-saturated, linear, or
ohmic bias state. The drain and source are effectively short-circuited. This happens when VGS >
VDS + Vtn for nMOS transistor and VGS < VDS +Vtp for pMOS transistor. Drain current is linearly
related to drain-source voltage over small intervals in the linear bias state.

Fig 2
Transfer Characteristics of MOSFET
The transfer characteristic relates drain current (ID) response to the input gate-source driving voltage
(VGS). Since the gate terminal is electrically isolated from the remaining terminals (drain, source, and
bulk), the gate current is essentially zero, so that gate current is not part of device characteristics. The
transfer characteristic curve can locate the gate voltage at which the transistor passes current and
leaves the OFF-state. This is the device threshold voltage (Vtn). Figure 3 shows measured input
characteristics for an nMOS and pMOS transistor with a small 0.1V potential across their drain to
source terminals.

Fig 3

The transistors are in their non-saturated bias states. As VGS increases for the nMOS transistor in Figure
5a, the threshold voltage is reached where drain current elevates. For VGS between 0V and 0.7V, ID is
nearly zero indicating that the equivalent resistance between the drain and source terminals is
extremely high. Once VGS reaches 0.7V, the current increases rapidly with VGS indicating that the
equivalent resistance at the drain decreases with increasing gate-source voltage. Therefore, the
threshold voltage of the given nMOS transistor is about Vtn 0.7V. The pMOS transistor input
characteristic in Figure 5b is analogous to the nMOS transistor except the ID and VGS polarities are
reversed.

Methodology
According the circuit diagrams given in the lab sheet the mosfets were connected (both pmos and
nmos) ID values were measured respect to the VGS values for constant VDS of 1V.
From ID vs VGS graph threshold voltage was calculated.
For different VGS value (>Vt) ID vs VDS measurements obtained.
ID vs VDS graphs plotted in same axis for different VGS values.
Trans-conductance gm was obtained from the graph.

Results
N-Channel Mosfet

ID vs VGS graph

VGS (V)

ID (mA)

2.6

0.1*10-3

2.8

0.5*10-3

3.0

4.5 *10-3

3.2

36*10-3

3.4

260*10-3

3.6

1.56

3.8

15.64

4.0

32.63

4.2

66.15

4.4

109.4

4.6

118.1

4.8

120.8

5.0

121.8

5.2

122.5

5.4

123.0

5.6

123.2

6.0

123.7

6.5

124.2

7.0

124.5

8.0

124.8

9.0

124.9

10.0

125.0

From the graph,

Threshold voltage Vt = 2.8V

VGS = 3V

VDS (V)

ID (mA)

2.8

0.5*10-3

3.0

4.0*10-3

3.2

38.9*10-3

3.4

204.0*10-3

3.6

1.37

3.8

27.83

4.0

44.8

4.2

77.1

4.4

213

4.6

255.2

4.8

255.3

5.0

255.5

5.5

255.8

6.0

255.9

VDS (V)

ID (A)

VGS = 5V

2.6

0.1*10-3

2.8

0.7*10-3

3.0

4.3*10-3

3.2

43.8*10-3

3.4

329.1*10-3

3.6

2.10

3.8

32.3

4.0

110

4.2

150

4.4

275.5

4.6

275.5

4.8

275.6

VGS (V)

ID (mA)

2.6

0.1*10-3

P-Channel Mosfet

ID vs VGS graph

2.8

0.5*10-3

3.0

5.8 *10-3

3.2

34.9*10-3

3.4

652*10-3

3.6

13.77

3.8

41.3

4.0

94.6

4.2

118.2

4.4

120.6

4.6

122.6

4.8

123.3

5.0

124.0

5.2

124.4

5.4

124.5

5.6

124.8

6.0

124.9

6.5

125.2

7.0

125.4

8.0

125.8

9.0

125.9

10.0

126

From the graph,

Threshold voltage Vt = 2.9V

VGS = 3V

VDS (V)

ID (mA)

2.6

0.1*10-3

2.8

0.3*10-3

3.0

5.6*10-3

3.2

163.4*10-3

3.4

1.25

3.6

8.37

3.8

56.4

4.0

112.2

4.2

255.4

4.4

255.4

VDS (V)

ID (A)

2.6

0.1*10-3

2.8

1.0*10-3

3.0

4.1*10-3

3.2

90.2*10-3

3.4

1.26

3.6

6.66

3.8

92.3

4.0

150.9

4.2

265.2

4.4

265.5

VGS = 5V