A 4th Order Continuous-Time ADC with

VCO-Based Integrator and Quantizer

ISSCC 2009, Session 9.5

Matt Park1, Michael H. Perrott2

Massachusetts Institute of Technology, Cambridge, MA USA
2 SiTime Corporation, Sunnyvale, CA, USA
1

Motivation
Analog
Anti-Alias
Filter

Digital
Channel
Filter
ADC

LNA

cos(wot)
sin(wot)

Sample
Clock
ADC

A highly digital receive path is very attractive for

achieving multi-standard functionality
A key issue is achieving a wide bandwidth ADC with high
resolution and low power

- Minimal anti-alias requirements are desirable for simplicity

Continuous-Time Sigma-Delta ADC structures
have very attractive characteristics for this space

A Basic Continuous-Time Sigma-Delta ADC Structure

Multi-Level
Quantizer
IN

OUT
H(s)
clock
DAC

Sampling occurs at the quantizer after filtering by H(s)

Quantizer noise is shaped according to choice of H(s)

- High open loop gain required to achieve high SNR

We will focus on achieving an efficient implementation

of the multi-level quantizer by using a ring oscillator
3

Application of Ring Oscillator as an ADC Quantizer

Ring Oscillator
Vtune

Ref
Vtune

Reset
Counters

Oscillator
Phases

Count
Ref

Register
Out

Count

Similar approaches:
Alon, Stojanovic, Horowitz
JSSC 2005
Out
Kim, Cho, ISCAS 2006

15

30

12

21

Input: analog tuning of ring oscillator frequency

Output: count of oscillator cycles per Ref clock period
4

VCO-Based Quantizer Also Shapes Delay Mismatch

Enable

Measurement 1

Enable

Measurement 2

Enable

Measurement 3

Enable

Measurement 4

Barrel shifting through delay elements

- Mismatch between delay elements is first order shaped

5

Benefits of VCO-based Quantization

N-Stage
Resistor
Ladder Pre-Amp Comparator

Vdd
N

N-Stage Ring Oscillator

IN

Vdd
Buffer
CLK

A
IN

N-bit Register

1
CLK

Much more digital implementation

Offset and mismatch is not of critical concern

Metastability behavior is improved

- No resistor ladder or differential gain stages

Implementation is high speed, low power, low area

6

Frequency Domain Model of VCO Quantizer

VCO modeled as integrator

and Kv nonlinearity
Sampling of VCO phase
modeled as scale factor of 1/T
Quantizer modeled as
addition of quantization noise

VCO
Vtune

First Order
Quantizer Difference
Out

1- z-1
Ref
T

Key non-idealities:

- Quantization noise
- First order shaped!
- VCO noise
- VCO K nonlinearity

VCO
Quantization
Noise
Noise
-20 dB/dec

Vtune

f
2Kv
s

VCO Kv
VCO
Nonlinearity

Output
Noise
20 dB/dec

f
1
T
Sampler

f
Out

1-

z-1

First Order
Difference

Example SNDR with 20 MHz BW (1 GHz Sample Rate)

Simulated ADC Output Spectrum

60
40

Amplitude (dB)

20
0
-20

VCO noise:
-100
dBc/Hz
@ 10 MHz

Conditions

SNDR

Ideal

68.2 dB

VCO Thermal
Noise

65.4 dB

VCO Thermal
+ Nonlinearity

32.2 dB

Kvco: 5% linearity

-40
-60
-80

-100 5
10

10

10

Frequency (Hz)

VCO Kv nonlinearity is
key SNDR bottleneck

VCO
Quantization
Noise
Noise
-20 dB/dec

Vtune

10

f
2Kv
s

VCO Kv
VCO
Nonlinearity

Output
Noise
20 dB/dec

f
1
T
Sampler

f
Out

1-

z-1

First Order
Difference

Reducing the Impact of Nonlinearity using Feedback

Ref
In

Gain and Vtune VCO-based

Filtering
Quantizer

Out

DAC
Iwata, Sakimura, TCAS II, 1999
Naiknaware, Tang, Fiez, TCAS II, 2000

Place VCO-based quantizer within a continuous-time

Sigma-Delta ADC structure

- Quantizer nonlinearity suppressed by preceding gain

stage

A Second Order Continuous-Time Sigma-Delta ADC

973 MHz

VIN
VA

VB

IDAC1

Vtune VCO-based
Quantizer &
Barrel-Shift
DEM

IDAC2

D OUT

Straayer, Perrott
VLSI 2007
0.13u CMOS IC

31

Third order noise

shaping with a second
order structure!

Peak SNDR limited by Kv non-linearity to 67 dB (20 MHz BW)

10

How Do We Overcome Kv Nonlinearity to

Improve SNDR?

11

Voltage-to-Frequency VCO-based ADC (1st Order )

In prior work, VCO frequency is desired output variable

- Input must span the entire non-linear voltage-to-frequency

(K ) characteristic to exercise full dynamic range
- Strong distortion at extreme ends of the Kv curve
v

12

Proposed Voltage-to-Phase Approach (1st Order )

VCO output phase is now the output variable

- Small perturbation on V allows large VCO phase shift

- VCO acts as a CT integrator with infinite DC gain
tune

High SNDR requires higher order

13

Proposed 4th Order Architecture for Improved SNDR

Goal: ~80 dB SNDR with 20 MHz bandwidth

- Achievable with 4 order loop filter, 4-bit VCO-based quantizer

- 4-bit quantizer: tradeoff resolution versus DEM overhead
th

Combined frequency/phase feedback for stability/SNDR

14

Schematic of Proposed Architecture

Opamp-RC integrators

Explicit
DWA

- Better linearity than Gm-C, though higher power

15

Schematic of Proposed Architecture

Passive summation performed with resistors

Explicit
DWA

- Low power
- Must design carefully to minimize impact of parasitic pole

16

Schematic of Proposed Architecture

DEM explicitly performed on phase feedback

DEM implicitly performed on frequency feedback

- NRZ DAC unit elements

- RZ DAC unit elements

(Note: Miller, US Patent (2004))

17

Behavioral Simulation (available at www.cppsim.com)

FFT PLOT

20
0

20 MHz Bandwidth

-20

AMPLITUDE (dB)

-40

Selected Noise,
-60 Non-Linearity:
-80 SNDR ~ 85 dB
-100

-140

-180
-200
0.1

-120

-160

Key Nonidealities

Only VCO Kv
Non-Linearity:
SNDR ~ 95 dB
1.0
10.0
100.0
ANALOG INPUT FREQUENCY (MHz)

VCO Kv nonlinearity
Device noise
Amplifier finite
gain, finite BW
DAC and VCO
unit element
mismatch

85 dB SNDR!

VCO nonlinearity is not the bottleneck for achievable SNDR!

Circuit Details

19

VCO Integrator Schematic

en0

en1

en2

15 stage current
starved ring-VCO

- 7 stage ring-VCO
shown for simplicity
- Pseudo differential
control
- PVT variation

en4

accommodated by
enable switches on
PMOS/NMOS

en0

en1

en2

en4

Rail-to-rail VCO
output phase signals
(VDD to GND)

Straayer, VLSI 2007

20

VCO Quantizer Schematic

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

outm

outp

Phase
quantization
with senseamp flip-flop

- Single

phase
clocking

clk
clk
inp

inm

clk

Rail-to-rail
quantizer
output
signals (VDD
to GND)

Nikolic et al, JSSC 2000

21

Phase Quantizer, Phase and Frequency Detector

Frequency Output
d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

d
d

q
q

Phase Output

Highly digital
implementation

- Phase sampled &

quantized by SAFF
- XOR phase and
frequency
detection with FF
and XOR

Automatic DWA for

frequency detector
output code

- Must explicitly

perform DWA on
phase detector
output code

22

Main Feedback DAC Schematic

iout,p

iout,m

VDD

iout,p

(same cell for Vinm)

- Keeps switch

iout,m

ap
Vinp

Vinp

Vinp

Vinm
Vcasc,n

Vinm

Vbias,n

am

clk

Yan et al
JSSC 2004

VSS
data

Low-swing
buffers

DB QB

iout,p

iout,m

Retiming
Flip-Flop

Low-Swing
Buffer

Current DAC
Unit-Element

devices in
saturation
Fast on / Slow
off reduces
glitches at DAC
output
Uses external
Vdd/Vss

Resistor
degeneration
minimizes 1/f
noise

Bit-Slice of Minor Loop RZ DAC

PMOS Drivers
clk
up

Vbias,p
Vcasc,p

VDD
clkb

dump,p
dump,p

up
NMOS Drivers
VDD
dump,n
clk
data

inp

clkb
datab

inm

outp

outm
inm

inp
Vcasc,n

dump,n
vcm

Vbias,n

RZ DAC unit elements transition every sample period

- Breaks code-dependency of transient mismatch (ISI)

- Uses full-swing logic signals for switching

24

Opamp Schematic
Vcm

Gm

Vcm

Mitteregger et al, JSSC 2006

Gm

Vbp

outm
outp

inm
Vcm
inp

Vbn

Parameter

Value

DC Gain

63 dB

Unity-Gain Frequency
Phase Margin
Input Referred Noise
Power (20 MHz BW)
Power (VDD = 1.5 V)

4.0 GHz
55
11 uV
(rms)
22.5 mW

Gm

Vcm

Modified nested Miller opamp

- 4 cascaded gain stages, 2

feedforward stages
- Behaves as 2-stage Miller near
cross-over frequencies
- Opamp 1 power is 2X of

opamps 2 and 3 (for low noise)

25

DEM Architecture (3-bit example)

Barrel Shift

5 2 3 6

5 2 3 6
Accumulator

Phase
Quantizer
Output

Therm. to
Binary

3
clk

See also:
Yang
ISSCC 2008

NRZ
DAC
Inputs

Achieves low-delay to allow 4-bit DEM at 900 MHz

- Code through barrel shift propagates in half a sample period

Die Photo (0.13u CMOS)

Die photo courtesy of Annie Wang (MTL)

Active area
0.45 mm2
Sampling Freq
900 MHz
Input BW
20 MHz
Supply Voltage
1.5 V
Analog Power
69 mW
Digital Power
18 mW
27

Measured Results
100

SNDR (20MHz)
SNR (20MHz)

60
40
20

Peak SNDR = 78.1 dB

Peak SNR = 81.2 dB

0
-20

-80 -70 -60 -50 -40 -30 -20 -10

Input Amplitude (dBFS)

100,000 pt. FFT

80

Magnitude (dB)

SNDR/SNR (dB)

80

100

60
40
20
0

-20
0

-40
0.1

1.0
10.0
Frequency (Hz)

78 dB Peak SNDR performance in 20 MHz

Architecture robust to VCO Kv non-linearity

100.0

- Bottleneck: transient mismatch from main feedback DAC

Figure of Merit: 330 fJ/Conv with 78 dB SNDR

28

Behavioral Model Reveals Key Performance Issue

FFT PLOT

20
0

20 MHz Bandwidth

-20

AMPLITUDE (dB)

-40

Selected Noise,
-60 Non-Linearity:
-80 SNDR ~ 78 dB
-100
-120
-140
-160
-180
-200
0.1

Only VCO Kv
Non-Linearity:
SNDR ~ 95 dB
1.0
10.0
100.0
ANALOG INPUT FREQUENCY (MHz)

Amplifier
nonlinearity
degrades
SNDR to 81 dB
DAC transient
mismatch
degrades
SNDR to 78 dB

- DEM does
not help
- Could be

improved
with dual RZ
structure

Transient DAC mismatch is likely the key bottleneck

Conclusion

VCO-based quantization is a promising component to

achieve high performance ADC structures

- High speed, low power, low area implementation

- First order shaping of quantization noise and mismatch
- Kv non-linearity was a limitation in previous approaches

Demonstrated a 4th-order CT ADC with a

VCO-based integrator and quantizer

- Proposed voltage-to-phase conversion to avoid

distortion from Kv non-linearity
- Achieved 78 dB SNDR in 20 MHz BW with 87 mW power
Key performance bottleneck: transient DAC mismatch

30