M Tech VLSIES 15-16 Draft

M.
Tech (VLSI Design& Embedded Systems) VR15
DETAILED
SYLLABUS
for
M Tech Degree Course
(Semester System)
VLSI DESIGN AND EMBEDDED SYSTEMS

w.e.f 2015-2016
COURSE STRUCTURE VR15
DEPARTMENT OF
ELECTRONICS & COMMUNICATION
ENGINEERING
VELAGAPUDI RAMAKRISHNA
SIDDHARTHA ENGINEERING COLLEGE

(AUTONOMOUS)
(Sponsored by Siddhartha Academy of General & Technical Education)
VIJAYAWADA 520 007
VELAGAPUDI RAMAKRISHNA SIDDHARTHA ENGINEERING COLLEGE: VIJAYAWADA - 7
M.Tech (VLSI Design & Embedded Systems) VR15

ELECTRONICS AND COMMUNICATION ENGINEERING
Curriculum, Scheme of Examination and Syllabi
For M.Tech Degree Program
in
VLSI Design & Embedded Systems
Being Offered at
Velagapudi Ramakrishna Siddhartha Engineering College
w.e.f 2015-2016
FIRST SEMESTER
Code
ECVE 1001
ECVE 1002
ECVE 1003
ECVE 1004
ECVE 1005/1
ECVE 1005/2
ECVE 1005/3
ECVE 1005/4
ECVE 1006/1
ECVE 1006/2
ECVE 1006/3
ECVE 1006/4
ECVE 1051
ECVE 1052
Subject
Principles of Embedded Systems
Advanced Digital Design using HDL
CMOS Digital IC Design
Microcontrollers for Embedded Systems
Semiconductor Device Modeling
Fabrication Technology
Advanced Data Communications
Advanced Computer Architecture
DSP Processors & Architectures
CPLD and FPGA Architectures and
Applications
Physical Design Automation
Embedded Computing System
VLSI Design Lab
Embedded Systems Lab
Total Credits
(6 Theory + 1 Lab + Seminar)
4
4
4
4
0
0
0
0
4
4
4
4
40
40
40
40
60
60
60
60
100
100
100
100
40
60
100
40
60
100
0
0
3
3
2
2
25
25
50
50
75
75
24
06
28
290
460
750
L: Lecture
P: Practice
C: Credits
I: Internal Assessment
E: End Examination
T: Total Marks

in
Being Offered at
w.e.f 2015-2016
SECOND SEMESTER
Code
ECVE 2001
ECVE 2002
ECVE 2003
ECVE 2004
ECVE 2005/1
ECVE 2005/2
ECVE 2005/3
ECVE 2005/4
ECVE 2006/1
ECVE 2006/2
ECVE 2006/3
ECVE 2006/4
ECVE 2051
ECVE 2052
Subject
Low Power VLSI Design

CMOS Analog IC Design
Networking & Internetworking using
microcontrollers
RTOS for Embedded Applications
Digital System Testing and Testable
Design
System on Chip Design
Advanced Digital Signal Processing
High Speed Digital Design
Hardware software co-design
Embedded Device drivers
VLSI Signal Processing
PERL Scripting Language
Analog and Digital CMOS Circuits Lab
Seminar
Total Credits
(6 Theory + 1 Lab + Seminar)
4
4
0
0
4
4
40
40
60
60
100
100
40
60
100
40
60
100
40
60
100
40
60
100
0
-
3
-
2
2
25
25
50
50
75
75
18
03
22
290
460
750
L: Lecture
P: Practice
C: Credits
I: Internal Assessment
E: End Examination
T: Total Marks

in
Being Offered at
w.e.f 2015-2016
THIRD SEMESTER
Code
Subject
T(I)
ECVE3051
Project Seminar
50

in
Being Offered at
w.e.f 2015-2016
FOURTH SEMESTER
Code
ECVE 4051
Subject
Project work and
Viva-voce
24
50 + 50 ( III Sem)
150
250
ECVE 1001
PRINCIPLES OF EMBEDDD SYSTEMS
Lecture :
Credits :
4 Hrs/ Week Practical: 4
Internal Assessment:
Final Examination:
40
60
Course Outcomes
Upon completion of the course student will be able to
understand the working of various communication architectures and protocols in an
embedded system
understand various capabilities of Embedded C and execute basic programs using it
understand RTOS features and case studies and analyze them for real time
applications
UNIT I
Embedded Computing - Introduction, Complex systems and microprocessors, The
embedded system design process, Formalism for system design, Model train controller, CPU:
Introduction, Programming input and output, Supervisor mode, Exceptions, and Traps, Coprocessors, Memory system mechanism; CPU performance and CPU power consumption,
Design example: Data compressor.
UNIT II
Bus-based Computer Systems - Introduction, The CPU bus, memory devices, I/O devices,
Component interfacing, Designing with microprocessors, Development and debugging,
System-level performance analysis, Program Design and Analysis, Models of programs,
Assembly, Linking, and Loading, Basic compilation techniques, Program optimization,
Program-level performance analysis, Software performance optimization, Program-level
energy and power analysis, Analysis and optimization of program size, Program validation
and testing, Software modem.
UNIT III
Hardware Accelerators and Networks Processors - Introduction, CPUs and accelerators,
Multiprocessor performance analysis, Design examples: Digital still cameras, and video
accelerator. Distributed embedded architectures, Networks for embedded systems, Networkbased design, Internet-enabled systems, Vehicles as networks, Sensor networks, Design
example Elevator controller.
UNIT IV
Introduction to Real Time Operating Systems - OS and RTOS basics, Tasks and task
states, Tasks and data, Semaphores and shared data, Message queues, Mailboxes and pipes,
Timer functions, Events, memory management, Interrupt routines in an RTOS environment,
Round robin, Round robin with interrupts, Function queue scheduling architecture, Real time
operating system architecture.

Text Books
1. Wayne Wolf (2012), Computers as Components: Principles of Embedded Computing
System Design, 3rd Ed, Morgan Kaufmann publishers. (Unit-I, II, III)
2. David Simon (1999), An Embedded Software Primer, Pearson Education. (Unit-IV)
References
1. Frank Vahid, Tony Givargis (2005), Embedded System Design, J Wiley India.
2. K V K K Prasad, Embedded Real Time Systems: Concepts, Design Programming,
Dreamtech Press.
ECVE 1002
ADVANCED DIGITAL DESIGN USING HDL
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Upon the completion of this course, students will be able to
Design and synthesize combinational and sequential logic.
Develop architectures for processors and controllers.
Apply post synthesis design tasks for any design.
UNIT-I
Introduction to Digital Design Methodology, Glitches and Hazards, Design of sequential
machines, state-transition graphs, design example: BCD to Excess-4code converter, serial line code converter for data transmission, state reduction, and equivalent states,Algorithmic
State Machine Charts for behavioral modeling, ASMD charts, switch debounce, metastability,
and synchronizers for asynchronous signals, design example: keypad scanner and encoder.
UNIT-II
Synthesis of Combinational and Sequential Logic:
Introduction to synthesis, synthesis of combinational logic, synthesis of sequential logic with
flip-flops, synthesis of explicit state machines, registered logic, state encoding, synthesis of
implicit state machines, registers, and counters, synthesis of gated clocks and clock enables
UNIT-III
Design and Synthesis of Datapath Controllers:
Partitioned sequential machines, design example: binary counter, design and synthesis of a
RISC stored-program machine, design example: UART
Algorithms and Architecture for Digital Processors
Algorithms, nested-loop programs, and data flow graphs, digital filters and signal processors,
building blocks for signal processors, asynchronous FIFOs- synchronization across clock
domains.
UNIT-IV:
Post synthesis Design Tasks:
Post synthesis design validation, post synthesis timing verification, estimation of ASIC timing
violations, false paths, system tasks for timing verification.
Text Books
1. Michael D. Ciletti (2002), Advanced digital design with the Verilog HDL, Eastern
economy edition, PHI. (Units I - IV)

References:
1. Stephen Brown & Zvonko Vranesic (2007) , Fundamentals of Digital logic with
Verilog design, 2nd edition, Tata McGraw Hill,.
2. Ian Grout (2011), Digital systems design with FPGAs and CPLDs, Elsevier
Publications.
3. Palnitkar, S. (2003). Verilog HDL: a guide to digital design and synthesis (Vol. 1).
Prentice Hall Professional.
ECVE 1003
CMOS DIGITAL IC DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Evaluate the performance of CMOS Inverter in terms of area, power and speed.
Evaluate the performance and power consumption of complex gates of a number of
contemporary gate logic families
Analyze sequential circuits
Analyze and apply timing issues for designing sequential circuits.
UNIT I
The CMOS Inverter - Static CMOS Inverter, Static Behaviour, Performance of CMOS
Inverter: Dynamic Behaviour, Power, Energy, and Energy- Delay, Technology Scaling and its
Impacts on the Inverter Metrics.
UNIT II
Designing Combinational Logic Gates in CMOS - Static CMOS Design Complementary
CMOS, Ratioed Logic, Pass Transistor Logic, Dynamic CMOS Design, Dynamic Logic:
Basic Principle, Speed and Power Dissipation of Dyanamic Logic, Issues in Dynamic Design,
Cascading Dynamic Gates.
UNIT III
Designing Sequential Logic Circuits - Introduction, Static Latches and Registers, Dynamic
Latches and Registers, Pipelining: An approach to Optimize Sequential Circuits, Non-Bistable
Sequential Circuits, Choosing a Clocking Strategy.
UNIT IV
Timing Issues in Digital Circuits - Timing Classification of Digital Systems, Synchronous
Interconnect, Synchronous Design, Clock Synthesis and Synchronization using a Phase
Locked Loop, Future Directions and Perspectives.
Text Books
1. Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, (2003) Digital
Integrated Circuits: a Design Perspective, 2nd Edition, Pearson Education.
References
1. J. Uyemura (1992), Circuit Design for CMOS VLSI, Kluwer.
2. A. Kang and Leblebici, (1999) CMOS Digital Integrated Circuits, 2nd Ed., McGrawHill.
ECVE 1004
MICROCONTROLLERS FOR EMBEDDED SYSTEMS
Lecture :
Credits :
Final Examination:
40
60
Course outcomes:
Upon completion of the course students will be able to
Understand the architecture and instruction set of 8051microcontroller and develop interfacing
programs in assemblylanguage and C.
Understand and analyze the design aspects, Architecture, and instruction set associatedwith
ARM processors.
Analyze the Cprogrammingoptimization methods forARM processor
Examines various cache-technologies that surround the ARM cores.
UNIT-I
The 8051 microcontrollers Overview of the 8051 family and architecture, Assembly
language programming, I/O port programming, 8051 Addressing Modes, Arithmetic, Logic
Instructions and programs.8051 programming in C: Programming timers, Serial port
programming,Interrupt programming, accessing external data memory, 8051 interfacing with
the 8255, DS12887 RTC Interfacing, Stepper motor interfaces.
UNIT II
ARM Processor Fundamentals: Registers, Current Program Status Registers, Pipeline,
Exceptions, Interrupts, and the Vector Table, Core Extensions, Architecture Revisions, ARM
Processor Families. Introduction to the ARM Instruction SET: Data Processing
Instructions, Branch Instructions, Load-Store Instruction, Software Interrupt Instruction,
Program Status Register Instructions, loading Constants, ARMv5E Extensions, Conditional
Execution.
UNIT III
Introduction to the Thumb Instruction Set :Thumb Register Usage, ARM-Thumb
Interworking, Other Branch Instructions, Data Processing Instructions, Single-Register LoadStore Instructions, Multiple-Register Load-Store Instructions , Stack Instruction, Software
Interrupt Instructions. Efficient C Programing :Overview of C Compiler and Optimization,
Basic C Data Types, C Looping Structure, Register Allocation,Function Calls, Pointer
Aliasing, Structure Arrangement, Bit-fields, Unaligned Data and Endianness, Division,
Floating Point, Inline Function and Inline Assembly, Portability Issues. Writing and
Optimizing ARM Assembly Code:Writing Assembly Code, Profiling and Cycle Counting,
Instruction Scheduling, Register Allocation, Conditional Execution, Looping Constructs, Bit
Manipulation, Efficient Switches, Handling Unaligned Data.Introduction to DSP on ARM,
FIR Filter, IIR Filter, Discrete Fourier transform

UNIT IV
Exception and Interrupt Handling: Exception handling, Interrupts, Interrupt Handling
Schemes. Caches: The Memory Hierarchy and CACHE memory, Cache Architecture, Cache
policy, Coprocessor 15 and caches, Flushing and Cleaning Cache memory, Cache Lockdown,
Caches and Software Performance. Memory Protection Units: Protected regions,
Initialization the MPU,Caches, and Write Buffer, Demonstration of an MPU system. Memory
Management Units:Moving from an MPU to MMU, HOW virtual Memory Works, Details
of the ARM MMU, Page Tables, The TranslationLook aside Buffer, Domains and Memory
Access Permission, The caches and Write Buffer, Coprocessor 15and MMU Configuration,
The Fast context Switch Extension.
Text Books:
1. Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D. McKinlay (2008), The 8051
Microcontroller and Embedded Systems Using Assembly and C Second Edition Pearson
Education.
2. A.Sloss, D.Symes, C.Wright, (2003), ARM system Developers Guide: Designing and
Optimizing System Software, Morgan Kaufmann publishers.
References:
1. Valvano, J. (2011),Embedded microcomputer systems: real time interfacing, 3rd
Edition, Cengage Learning.
10
ECVE 1005/1
SEMICONDUCTOR DEVICE MODELING
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Upon the completion of the course student will be able to
understand the concepts of semiconductor device physics.
analyze the BJT and MOSFET device characteristics
understand the second order effects of BJT and MOSFET.
UNIT I
Energy bands in solids, Electrons and holes densities in equilibrium, Excess carriers - Nonequilibrium situation, Mobility of carriers, Charge transport in semiconductors, Continuity
equation.
UNIT II
Introduction to BJT, Operation of BJT at high frequencies, Design of high frequency
transistors, Second order effects in BJTs, Variation of beta with collector current, High
injection in collector, Heavy doping in emitter, Non-conventional BJTs, Hetero-junction
bipolar BJTs.
UNIT III
Metal-semiconductor junction, Energy band diagram of M-S junction, Current-voltage
characteristics of M-S junction, Ohmic contacts, Junction field effect transistor, Small signal
parameters of JFETs, The MESFETs, The Hetero- junction FETs.
UNIT IV
Introduction to MOSFETs, Effect of gate and drain voltages on carrier mobility in the
inversion layer, Channel length modulation, MOSFET break down and punch-through, Subthreshold current, MOSFET scaling, Non-uniform doping in channel, Threshold voltage of
short channel MOSFETs, Small signal analysis, Other MOSFETs configuration.
Text Books
1. Nandita Das Guptha , Amitava Das Guptha (2004), Semiconductor Devices
Modelling and Technology, Prentice Hall India.(UNIT I - IV)
References
1. Ben G. Streetman (2000), Solid State Electronic Devices, 5th edition, Pearson
Education Asia.
11
ECVE 1005/2
FABRICATION TECHNOLOGY
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Describe various fabrication steps involved in IC fabrication.
Understand the process of crystal growth, wafer preparation, epitaxial growth.
Understand significance of thin and thick oxidation in fabrication process.
Understand the development of metallic interconnects through lithography,
metallization, etching.
UNIT I
Crystal Growth and Wafer Preparation Introduction, Electronic grade silicon,
Czochralski crystal growing, Silicon shaping, Processing considerations.
Epitaxy Introduction, Vapor phase epitaxy, Molecular beam epitaxy, Silicon-on-insulators,
Epitaxial evaluation.
UNIT II
Oxidation Introduction, Growth mechanism and kinetics, Thin oxides, Oxidation
techniques and systems, Oxide properties, Redistribution of dopants at interface, Oxidation
of polysilicon, Oxidation induced defects.
Etch and Cleaning: materials used in cleaning, various cleaning methods, Wet etch, Dry
etch, Plasma etching, RIE etching, etch selectivity/selective etch.
Lithography Introduction, Optical lithography, Electron lithography, X-Ray lithography,
Ion lithography.
Reactive Plasma Etching Introduction, Plasma properties, Feature size control and
anisotropic etch mechanisms, Reactive plasma etching techniques and equipment.
UNIT III
Dielectric and Polysilicon Film Deposition Introduction, Deposition processes,
Polysilicon, Silicon dioxide, Silicon nitride, Plasma assisted depositions.
Diffusion Introduction, Models of diffusion in solids, Measurement techniques, Diffusion
in polycrystalline silicon, Diffusion in SiO2.
UNIT IV
Ion Implantation Introduction, Range theory, Implantation equipment, Annealing,
Shallow junctions, High-energy implantation.
Metallization Introduction, Metallization applications, Metallization choices, Physical
vapor deposition, Patterning.
Text Books
1. S.M.Sze (2001), VLSI Technology, 2/E Tata McGraw-Hill. (UNIT I - IV)
12

References
1. Yasuo Tarui (1986), VLSI Technology: Fundamentals and Applications, SpringerVerlag.
2. Plummer (2001), Silicon VLSI Technology: Fundamentals, Practice, and Modeling,
Pearson Education India.
3. S. K. Ghandhi, (1983), VLSI Fabrication Principles: Silicon and Gallium Arsenide
Wiley, New York,
4. C.Y. Chang and S.M.Sze (Ed), (1996), ULSI Technology, McGraw Hill Companies
Inc.
5. Stephen Campbell (1996), The Science and Engineering of Microelectronics,
Oxford University Press,.
13
ECVE 1005/3
ADVANCED DATA COMMUNICATIONS
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Understand the various digital communication techniques
Understand the Circuit Switching- Space Division Switches- Time Division
Switches.
Understanding and ability to Time Division Multiplexing (TDM),Synchronous Time
Division Multiplexing
UNIT I
Digital Modulation - Introduction, Information Capacity Bits, Bit Rate, Baud, and M-ARY
Coding, ASK, FSK, PSK, QAM, BPSK, QPSK, 8PSK, 16PSK, 8QAM, 16QAM, DPSK
Methods, Band Width Efficiency, Carrier Recovery, Clock Recovery.
UNIT II
Basic Concepts of Data Communications, Interfaces and Modems - Data
Communication- Components, Networks, Distributed Processing, Network CriteriaApplications, Protocols and Standards, Standards Organizations- Regulatory Agencies, Line
Configuration- Point-to-point- Multipoint, Topology- Mesh- Star- Tree- Bus- Ring- Hybrid
Topologies, Transmission Modes- Simplex- Half duplex- Full Duplex, Categories of
Networks- LAN, MAN, WAN and Internetworking, Digital Data Transmission- Parallel and
Serial, DTE- DCE Interface- Data Terminal Equipment, Data Circuit- Terminating
Equipment, Standards EIA 232 Interface, Other Interface Standards, Modems- Transmission
Rates.
UNIT III
Error Detection and Correction - Types of Errors- Single- Bit Error, CRC (Cyclic
Redundancy Check) - Performance, Checksum, Error Correction- Single-Bit Error
Correction, Hamming Code.
Data link Control - Stop and Wait, Sliding Window Protocols.
Data Link Protocols - Asynchronous Protocols, Synchronous Protocols, Character Oriented
Protocol- Binary Synchronous Communication (BSC) - BSC Frames- Data Transparency,
Bit Oriented Protocols HDLC, Link Access Protocols.
UNIT IV
Switching - Circuit Switching- Space Division Switches- Time Division Switches- TDM
Bus- Space and Time Division Switching Combinations- Public Switched Telephone
14

Network, Packet Switching- Datagram Approach- Virtual Circuit Approach- Circuit
Switched Connection Versus Virtual Circuit Connection, Message Switching.
Multiplexing - Time Division Multiplexing (TDM), Synchronous Time Division
Multiplexing, Digital Hierarchy, Statistical Time Division Multiplexing.
Text Books
1. B. A.Forouzan. (2009), Data Communication and Computer Networking, 4th ed.,
TMH. (UNIT-II, III, & IV).
2. W. Tomasi. (2008), Advanced Electronic Communication Systems, 5 ed., PEI.
(UNIT-I).
References
1. Prakash C. Gupta. (2006), Data Communications and Computer Networks, PHI.
2. William Stallings. (2007), Data and Computer Communications, 8th ed., PHI.
3. T. Housely. (2008), Data Communication and Tele Processing Systems, 2nd
Edition, BSP.
15
ECSP 1005/4
ADVANCED COMPUTER ARCHITECTURE
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Evaluate cost performance and reliability of RAID system.
Describe quantitative evaluation of multi-threading.
Survey the limitations of Instruction-Level parallelism & Thread-level parallelism.
Understand the optimization techniques of cache performance.
UNIT I
Fundamentals of Computer design - introduction, classes of computers, defining computer
architecture, trends in Technology, trends in cost, trends in power in integrated circuits,
dependability, measuring, reporting and summarizing performance, quantitative principles of
computer design.
Instruction-Level parallelism and its exploitation - concepts and challenges, basic compiler
techniques for exposing ILP reducing branch costs with prediction, overcoming data hazards
with dynamic scheduling, Dunamic scheduling: examples and algorithm, hardware based
speculation, exploiting ILP using multiple issue and static scheduling, exploiting ILP using
dynamic scheduling, multiple issue, and speculation, advanced techniques for instruction
delivery and speculation.
UNIT II
Limitations on instruction Level parallelism: introduction, studies of the limitations of
ILP, limitation on ILP for realizable processors, crosscutting issues: hardware versus software
speculation, multithreading: using ILP support to exploit thread level parallelism.
Multiprocessors and thread level parallelism: introduction, symmetric shared memory
architectures, performance of symmetric shared memory multiprocessors, distributed shared
memory and directory based coherence, synchronization: the basics, models of memory
consistency: an introduction, crosscutting issues.
UNIT III
Memory hierarchy design - introduction, eleven advanced optimization of cache
performance, memory technology and optimizations, protection: virtual memory and virtual
machines, the design of memory hierarchies.
UNIT IV
Storage systems - introduction, advanced topics in disk storage, definition and examples of
real faults and failures, i/o performance, reliability measures and benchmarks, a little queuing
theory, crosscutting issues, designing and evaluating an I/O system.
16

Text Books
1. L. Hennessy & David A. Patterson (2011) Computer Architecture A quantitative
approach 4th edition, Morgan Kufmann (An Imprint of Elsevier). (UNIT I- IV)
References
1. Kai Hwang and A.Briggs (1984) Computer Architecture and parallel Processing
International Edition McGraw-Hill.
2. Dezso Sima, Terence Fountain, Peter Kacsuk (1997), Advanced Computer
Architectures, Pearson.
17
ECVE 1006/1
DSP PROCESSORS AND ARCHITECTURES
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Gain knowledge on computational accuracy issues and architectures of DSP devices.
Demonstrate knowledge of internal architecture, memory and peripheral devices for a
DSP processor.
Understand the implementation of applications for FFT algorithms using DSP
Processors
UNIT I
Introduction to Digital Signal Procesing Introduction, A Digital signal-processing system, The
sampling process, Discrete time sequences. Discrete Fourier Transform (DFT) and Fast Fourier
Transform (FFT), Linear time invariant systems, Digital filters, Decimation and interpolation,
Analysis and Design tool for DSP Systems MATLAB, DSP using MATLAB. Computational
Accuracy in DSP Implementations Number formats for signals and coefficients in DSP systems,
Dynamic Range and Precision, Sources of error in DSP implementations, A/D Conversion errors,
DSP Computational errors, D/A Conversion Errors, Compensating filter.
UNIT II
Architectures for Programmable DSP Devices - Basic Architectural features, DSP
Computational Building Blocks, Bus Architecture and Memory, Data Addressing
Capabilities, Address Generation Unit, Programmability and Program Execution, Speed
Issues, Features for External interfacing.
Programmable Digital Signal Processors - Commercial Digital signal-processing Devices,
Data Addressing modes of TMS320C54XX DSPs, Data Addressing modes of
TMS320C54XX Processors, Memory space of TMS320C54XX Processors, Program Control,
TMS320C54XX instructions and Programming, On-Chip Peripherals, Interrupts of
TMS320C54XX processors, Pipeline Operation of TMS320C54XX Processors.
UNIT III
Implementations of Basic DSP Algorithms - The Q-notation, FIR Filters, IIR Filters,
Interpolation Filters, Decimation Filters, PID Controller, Adaptive Filters, 2-D Signal
Processing.
Implementation of FFT Algorithms - An FFT Algorithm for DFT Computation, A Butterfly
Computation, Overflow and scaling, Bit-Reversed index generation, An 8-Point FFT
implementation on the TMS320C54XX, Computation of the signal spectrum.
18
UNIT IV
Interfacing Memory and I/O Peripherals to Programmable DSP Devices - Memory space
organization, External bus interfacing signals, Memory interface, Parallel I/O interface,
Programmed I/O, Interrupts and I/O, Direct memory access (DMA).
A Multichannel buffered serial port (McBSP), McBSP Programming, a CODEC interface
circuit, CODEC programming, A CODEC-DSP interface example.
Text Books
1. Avatar Singh and S.Srinivasan. (2004), DSP Processors and Architectures, Thomson
Publications. (Units-I,II & IV)
2. Lapsley et al. (2000), DSP Processor Fundamentals, Architectures & Features,
S.
Chand & Co. (Unit-III )
References
1. B. Venkataramani and M. Bhaskar. (2002), Digital Signal Processors, Architecture,
Programming and Applications TMH.
2. Jonatham Stein. (2005), Digital Signal Processing, John Wiley.
19
ECVE 1006/2
CPLD AND FPGA ARCHITECURES AND APPLICATIONS
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Examine various programmable logic devices.
Comprehend FPGA programming technologies
Design applications using FPGA devices.
UNIT-I:
Introduction to Programmable Logic Devices
Introduction, Simple Programmable Logic Devices Read Only Memories, Programmable
Logic Arrays, Programmable Array Logic, Programmable Logic Devices/Generic Array
Logic; Complex Programmable Logic Devices Architecture of Xilinx Cool Runner
XCR3064XL CPLD, CPLD Implementation of a Parallel Adder with Accumulation.
UNIT-II:
Field Programmable Gate Arrays
Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block
Architectures, Programmable Interconnects, and Programmable I/O blocks in FPGAs,
Dedicated Specialized Components of FPGAs, Applications of FPGAs.
UNIT-III:
SRAM Programmable FPGAs
Introduction, Programming Technology, Device Architecture, The Xilinx XC2000, XC3000
and XC4000 Architectures.
Anti-Fuse Programmed FPGAs
Introduction, Programming Technology, Device Architecture, The Actel ACT1, ACT2 and
ACT4Architectures.
UNIT-IV:
Design Applications:
General Design Issues, Counter Examples, A Fast Video Controller, A Position Tracker for a
Robot Manipulator, A Fast DMA Controller, Designing Counters with ACT devices,
Designing Adders and Accumulators with the ACT Architecture.
Text Books
1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer
International Edition.(Unit I, II)
2. Digital Systems Design - Charles H. Roth Jr, Lizy Kurian John, Cengage
Learning.(Unit III, IV)
20
References
1. Field Programmable Gate Arrays - John V. Oldfield, Richard C. Dorf, Wiley India.
2. Digital Design Using Field Programmable Gate Arrays - Pak K. Chan/Samiha
Mourad, Pearson Low Price Edition.
3. Digital Systems Design with FPGAs and CPLDs - Ian Grout, Elsevier, Newnes.
4. FPGA based System Design - Wayne Wolf, Prentice Hall Modern Semiconductor
Design Series.
21
ECVE 1006/3
PHYSICAL DESIGN AUTOMATION
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Comprehend the working of physical design flow.
Formulate CAD design using algorithmic paradigms
Understand design and automation of the FPGAs and MCMs.
UNIT I
VLSI Physical Design Automation - VLSI Design Cycle , Physical Design Cycle, New
Trends, Design Styles, System Packaging Styles, Historical Perspectives, Existing Design
Tools
Fabrication Process and Its Impact - Fabrication Materials, Fabrication of VLSI Circuits,
Design Rules, Layout of the Basic Design, Scaling Methods, Status of Fabrication Process,
Issues Related to Fabrication Process, Future of Fabrication Process, Tools and Process
Development.
UNIT II
Data Structures and Basic Algorithms - Complexity Issues and NP-hardness, Basic
Algorithms, Basic Data Structures, Graph Algorithms for Physical Design.
UNIT III
Partitioning - Introduction to Partitioning, Problem Formulation, Classification of
Partitioning Algorithm, Group Migration Algorithm, Simulated Annealing and Evolution,
Other Partitioning Algorithm, Performance Drive Partitioning.
Floorplanning and Placement - Floorplanning, Chip Planning, Pin Assignment, Integrated
Approach, Placement.
UNIT IV
Routing and Automation of FPGAs and MCMs - Global Routing, Detailed Routing,
Clock Routing, Power and Ground Routing, Compaction, Physical Design Automation of the
FPGAs and MCMs.
Text Books
1. Naveed A. Sherwani (1999), Algorithms for VLSI Physical Design Automation",
Third Edition, Kluwer Academic Publications.
Reference
1. S.H.Gerez (1998), Algorithms for VLSI Design Automation, Wiley Publication.
22

2. Sadiq M. Sait and Habib Youssef (1999), VLSI Physical Design Automation: Theory
and Practice by World Scientific Publishers, Singapore/New-Jersey, USA. (Also
published by McGraw-Hill Book Co., Europe, December 1995).
23
ECVE 1006/4
EMBEDDED COMPUTING SYSTEM
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Illustrate linux programming concepts.
Compiling code using gcc, applying optimization techniques and get familiar with
compilation process
Understand fundamentals of open source IDE - Eclipse to develop embedded
application
Use and get acquaint to debugging embedded software tools.
UNIT I
LINUX PROGRAMMING- Evolution of Linux OS, Open source moment, Main
characteristics of Linux, Typical Linux distributions, linux terminal, basic commands, editorsvi, gedit, linux shells and shell scripts, environmental variables, file system, file permissions,
filters, make utility, system calls, kernel overview.
.
UNIT II
GNU COMPILERS- Introduction, Compiling a C program, Compilation options,
Compilation options, Compilation options, Compiling with optimization, Platform-specific
options, Troubleshooting, Compiler-related tools, How the compiler works, Examining
compiled files.
UNIT III
OPEN-SOURCE IDE- Introducing Eclipse, Installation, Getting Started, C/C++ Developers'
Toolkit (CDT), Eclipse CDT, Device Software Development Platform.
UNIT IV
The Host Development Environment - Cross development tools, The GNU tool chain,
Configuring and building the kernel. Debugging Embedded Software- The target setup,
GDB, Debugging a sample program, The Host as a debug environment.
Text Books
1. Sumitabha Das (2005) 'YOUR UNIX :THE ULTIMATE GUIDE', McGraw Hill
Education (India) Private Limited, 1 edition (Unit-I)
2. Brian Gough 'An Introduction to GCC', Network Theory Limited, UK (Unit-II)
3. Doug Abbott, 'Embedded Linux Development Using Eclipse', Newnes publishers
(Unit-III)
4. Doug Abbott. (2003) Linux for Embedded and Real Time Applications, Newnes
publishers (Unit-IV)
24
References
1. Neil Mathew, Richard Stones Beginning Linux Programming, Wiley India Pvt. Ltd.
25
ECVE 1051
VLSI DESIGN LAB
Lecture :
Credits :
Practical:
2
2 Hrs/ Week
Final Examination:
25
50
Course Outcomes:
At the end of the course student will be able to
Get acquainted with Programmable logic design flow.
Implement designed digital circuits using FPGA and CPLD devices.
List of Experiments
Task #1 Design and Synthesis of a RISC Stored-Program Machine
i.
ii.
iii.
iv.
v.
RISC SPM: ALU

RISC SPM: Controller
RISC SPM: Instruction Set
RISC SPM: Controller Design
RISC SPM: Program Execution
Task #2 Design of communication and signal processing sub modules.

1.
2.
3.
4.
5.
6.
7.
8.
Design of 8-bit LFSR

Design of 4 bit Multiply and Accumulate unit
Design of A Hardware Multiplier
Design of Filter
Design an Huffman coder
Write Verilog Code for 3-bit Arbitary Counter to generate 0,1,2,3,6,5,7 and repeats.
Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence.
Design a FIFO and LIFO buffers in Verilog and Verify its Operation.
Task #4 Design a coin operated public Telephone unit using Mealy FSM model with
following operations
i.
The calling process is initiated by lifting the receiver.
ii.
Insert 1 Rupee Coin to make a call.
iii.
If line is busy, placing the receiver on hook should return a coin
iv.
If line is through, the call is allowed for 60 seconds at the 45th second prompt
another 1 Rupee coin to be inserted, to continue the call.
v.
If user doesn't insert the coin within 60 seconds the call should be terminated.
vi.
The system is ready to accept new call request when the receiver is placed on
the hook.
vii.
The FSM goes 'out of order' state when there is a Line Fault.
26
ECVE 1052
EMBEDDED SYSTEMS LAB
Lecture :
Credits :
Practical:
2 Hrs/ Week
Final Examination:
25
50
Course Outcomes:
Upon completion of the course, students will be able to write programs and use 8051,
PIC and ARM7 microcontrollers for various applications.
1. Programs on 8051 instruction set.

2. Programs on 8051 peripherals
3. Programs to read sensor and display values on PC.
4. Programs on ARM controller on chip peripherals.
5. Programs on I2C device interface (Memory)
6. Programs on I2C device interface(RTC)
7. Program to transfer data using Ethernet port.
8. Programs on multitasking using RTOS.
9. Program to implement semaphore for task switching using RTOS.
10. Programs to implement priority scheduling and OS time delay functions by writing
4different tasks (using ARM controller).
11. Programs on Pipes using RTOS
12. Programs on Fork function using RTOS
27
ECVE 2001
LOW POWER VLSI DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Apply different circuit techniques to manage the leakage currents
Comprehend existing low power adder and multiplier architectures
Understand the architectural and circuit level techniques for attaining low power
consumption
UNIT I
Low Power CMOS VLSI Design - Introduction, Sources of Power Dissipation, Static Power
Dissipation, Active Power Dissipation.
Circuit Techniques for Low Power Design - Introduction, Designing for Low-Power,
Circuit Techniques for Leakage Power Reduction.
UNIT II
Low Voltage Low Power Adders - Introduction, Standard Adder Cells, CMOS Adders
Architectures, Low Voltage Low Power Design Techniques, Current Mode Adders.
Low Voltage Low Power Multipliers - Introduction, Overview of Multiplication, Types of
Multiplier Architectures, Braun Multiplier, Baugh-Wooley Multiplier, Booth Multiplier,
Wallance Tree Multiplier.
UNIT III
Low Voltage Low Power Static RAM - Basics of SRAM, Memory Cell, Precharge and
Equalization Circuit, Decoder, Address Transition Detection, Sense Amplifier, Output Latch,
Low Power SRAM Technologies.
Low Voltage Low Power Dynamic RAM - Types of DRAM, Basics of DRAM, Self Refresh
Circuit, Half Voltage Generator, Voltage Down Converter, Future Trends and Developments
of DRAM.
UNIT IV
Low- Voltage Low Power Read-Only Memories - Introduction, Types of ROM, Basics
Physics of Floating Gate Nonvolatile Devices, Floating Gate Memories, Basics of ROM, Low
Power ROM Technology.
Text Book
1. Kiat Seng Yeo, Kaushik Roy (2005),Low Voltage, Low Power VLSI Subsystems,
TATA McGraw-Hil.
28
References
1. Yeo Rofail,Gohl (2002), CMOS/BiCMOS ULSI Low Voltage, Low Power, Pearson
Education Asia 1st Indian reprint.
2. J.Rabaey (1996), Digital Integrated circuits: a Design Perspective, PHI.
29
ECVE 2002
CMOS ANALOG IC DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Design single stage amplifiers and op-amp amplifiers
Analyze feedback amplifiers and oscillators.
Understand the stability and frequency compensation techniques.
UNIT I
Single Stage Amplifiers and Current Mirrors - Common source, common gate and source
follower stages- Cascode and folded cascode structures- Frequency response, MOS current
mirrors-sources.
UNIT II
MOS Differential Amplifiers and Operational Amplifiers - Single ended and differential
operation, Basic differential pair, Common mode response, Frequency response- CMOS
operational amplifiers - One-stage op-amps and two stage op-amps
UNIT III
Feedback Amplifiers and Frequency Compensation - General considerations, Feedback
topologies, Stability and frequency compensation- Nonlinearity and mismatch in MOS
differential circuits.
UNIT IV
Oscillators and PLLs General Considerations, Ring oscillators, LC oscillators, Voltage
controlled oscillators, Basics of PLLs.
Text Books
1. Behzad Razavi (2002), Design of Analog CMOS Integrated Circuits Tata-Mc
GrawHill. (UNIT I IV)
References
1. David A Johns & Ken Martin (2001), Analog Integrated Circuit Design John Wiley
and Sons.
2. Philip Allen & Douglas Holberg (2002), CMOS Analog Circuit Design, Oxford
University Press.
30
ECVE 2003
NETWORKING & INTERNETWORKING USING
MICROCONTROLLERS
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Upon completion of the course the students will be able to
develop a network using RS-232 standard
integrate network protocols into an embedded processor to establish network.
apply LAN controller in establishing embedded network
understand different layers of TCP/IP module of easy ethernet.
UNIT I
The Essence of Microcontroller Networking RS-232: RS-232 standard operating
procedure, Voltage conversion considerations.
Implementing RS-232 with a Microcontroller: Basic RS-232 Hardware, Building a simple
microcontroller RS-232 transceiver, RS-232 interface hardware, A microcontroller DCE
device, Writing some simple RS-232 firmware, A bit of RS-232 transmit code, RS-232
receive code.
Writing RS-232 microcontrollers routines in BASIC and Building, RS-232 communication
Hardware: Basic RS-232, Instructions.
UNIT II
Microcontroller USART - Interrupt Driven USART code.
I2C Serial Protocol: I2C basics and bus, I2C ACKS and NAKS, I2C addressing, PIC I2C
salve-transmitter mode code.
UNIT III
Ethernet: Basics, CS8900A-CQ - Reset overview, Media interface overview, Transmit
process overview, Receive process overview, External storage overview, Status indicator,
MAC engine, Ethernet engine, Hardware. PIC microcontroller, ICSP interface, Developing
easy Ethernet CS8900A Firmware, Setting up the PIC16F877 microcontroller, Carving up the
PIC16F877s memory resources, Easy Ethernet CS8900A Macros, Defining the CS8900ACQ packet page register set.
Unit IV
Writing the CS8900A-CQ Firmware - Reset the CS8900A-CQ, Load the CS8900A-CQ
basic parameters, Load the CS8900A-CQ individual address register set, Enable the
31

CS8900A-CQ transmitter and receiver, The main service loop, A frame under the microscope,
The art of ARP
TCP and easy Ethernet CS8900A - The physical layer, Data link layer, Network layer,
Transport layer, Application layer, Coding TCP/IP for the easy Ethernet CS8900A
Text Book
1. Fred Eady. (Oct.2004), Networking and Internetworking with Microcontrollers,
Elsevier Inc. (UNIT I, II, III & IV)
References
1. Andrew N Sloss, (2011) ARM system Developers Guide: Designing and Optimizing
System Software, Morgan Kaufmann Publishers.
2. Crystal LAN ISA Ethernet Controller, CS8900A, Datasheet.
32
ECVE 2004
RTOS CONCEPTS FOR EMBEDDED APPLICATIONS
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes
Illustrate real time programming concepts.
Apply RTOS functions to implement embedded applications
Understand fundamentals of design consideration for embedded applications
Unit-I
Introduction to Real-Time Operating Systems- Defining an RTOS, The scheduler, Kernel
Objects and services, Key characteristics of an RTOS
TASK- Defining a Task, Task States and Scheduling, Typical Task Operations, Typical Task
Structure, Synchronization, Communication and Concurrency
Unit-II
Semaphores- Defining Semaphores, Typical Semaphore Operations, Typical Semaphore Use
Message Queues- Defining Message Queues, Message Queue States, Message Queue
Content, Message Queue Storage, Typical Message Queue Operations, Typical Message
Queue Use, Pipes, Event Registers, Signals and condition Variables
Unit-III
Exceptions and Interrupts- Exceptions and Interrupts, Applications of Exceptions and
Interrupts, Closer look at exceptions and interrupts, processing general Exceptions, Nature of
Spurious Interrupts
Timer and Timer Services- Real-Time clocks and System Clocks, Programmable Interval
Timers, Timer Interrupt Service Routines.
I/O Subsystems- I/O concepts, I/O subsystems
Unit-IV
Memory Management- Dynamic Memory Allocation in Embedded Systems, Fixed-Size
Memory management in Embedded Systems, Blocking VS. Non-Blocking Memory
Functions, Hardware Memory Management Units
Synchronization and Communication- Synchronization, Communication, Resource
Synchronization Methods, Critical section, Common practical design patterns, Specific
Solution Design Patterns,
Common Design Problems- Resource Classification, Deadlocks, Priority Inversion.
Textbook:
1. Qing Li, (2003), Real-Time Concepts for Embedded Systems, CMP Books.
33

References
1. Albert Cheng, (2002), Real-Time Systems: Scheduling, Analysis and Verification, Wiley
Interscience.
2. Hermann Kopetz, (1997), Real-Time Systems: Design Principles for Distributed Embedded
Applications, Kluwer.
3. Insup Lee, Joseph Leung, and Sang Son, (2008) Handbook of Real-Time Systems,
Chapman and Hall.
4. Krishna and Kang G Shin, (2001), Real-Time Systems, McGraw Hill.
34
ECVE 2005/1
DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Collapse the available faults in the system and use suitable simulation technique for
testing
Test SSFs, Bridging faults in combinational and sequential circuits
Understand generation of test pattern in BIST
Perform test response compression and analyze test complexity
UNIT I
Fault Modeling - Logical Fault Models, Fault Detection and Redundancy, Fault Equivalence
and Fault Location, Fault Dominance, Single and Multiple Stuck-Fault Model.
Fault Simulation - General Fault Simulation Techniques, Fault Simulation for Combinational
Circuits, Fault Sampling.
UNIT II
Testing For Single Stuck Faults ATG for SSFs in Combinational Circuits, ATG for SSFs
in Sequential Circuits.
Testing For Bridging Faults The Bridging Fault Model, Detection of Non-Feedback
Bridging Faults, Detection of Feedback Bridging Faults, Bridging Fault Simulation, Test
Generation for Bridging Faults,
UNIT-III
Design For Testability: Testability, Adhoc Design for Testability Techniques, Controllability
and Observability by Means of Scan Registers, Generic Scan Based Design.
Compression Techniques - General Aspects of Compression Techniques, Ones-Count
Compression, Transition-Count Compression, Parity-Check Compression, Syndrome Testing,
Signature Analysis.
UNIT-IV
Built-In Self Test - Test Pattern Generation for BIST, Generic Off-Line BIST Architectures,.
Text Books
1. M. Abramovici, M.A. Breuer and A.D. Friedman (1996), Digital Systems and
Testable Design", Jaico Publishing House.
References
1. Parag K Lala (2002), Digital Circuit Testing and Testability, Achedamic Press.
35

2. M.L. Bushnell and V.D. Agrawal (2002), "Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits", Kluwar Academic Publishers.
3. A.L. Crouch (2002), "Design for Test for Digital IC's and Embedded Core Systems",
Prentice Hall International.
36
ECSP 2005/2
SYSTEM ON-CHIP DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Understand of the ARM processor architecture.
Understand of the ARM instruction set architecture and write assembly programs and
high level languages for ARM architectures.
Understand of the memory organization and interfacing issues.
UNIT I
Introduction to Processor Design - Abstraction in hardware design, MUO a simple
processor, Processor design trade off, Design for low power consumption.
ARM Processor as System-on-Chip - Acorn RISC Machine Architecture inheritance
ARM programming model ARM development tools 4and 5 stage pipeline ARM
organization ARM instruction execution and implementation ARM Co-processor
interface.
UNIT II
ARM Assembly Language Programming - ARM instruction types data transfer, data
processing and control flow instructions ARM instruction set co-processor instructions.
Architectural Support for High Level Language - Data types Abstraction in software
design Expressions Loops Functions and Procedures Conditional Statements Use of
Memory.
UNIT III
Memory Hierarchy - Memory size and speed On-chip memory Caches Cache designAn example Memory management
Architectural Support for System Development - Advanced Microcontroller bus
architecture ARM memory interface ARM reference peripheral specification Hardware
system prototyping tools Armulator Debug architecture.
UNIT IV
Architectural Support for Operating System - An introduction to Operating Systems
ARM system control coprocessor CP15 protection unit registers ARM protection unit
CP15 MMU registers ARM MMU Architecture Synchronization Context switching
input and output.
Text Books
1. Steve Furber (2000), ARM System on Chip Architecture, 2nd ed., Addison Wesley
Professional. (UNIT I - IV).
37
References
1. Michael J Flynn, Wayne Luk (2011), Computer System Design: System On Chip,
Wiley India Edition.
2. Prakash Rashinkar, Peter Paterson and Leena Singh L. (2001), System on Chip
Verification Methodologies and Techniques, Kluwer Academic Publishers.
3. Ricardo Reis (2004), Design of System on a Chip: Devices and Components 1st ed.,
Springer.
38
ECVE 2005/3
ADVANCED DIGITAL SIGNAL PROCESSING
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Design a sample rate converter that reduces/increase by a given factor
Design a linear phase fir filter for given specifications analyze and
Synthesize FIR filter for given multi structure filter bank.
Evaluate the performance of parametric and non parametric power spectral estimation
methods.
UNIT I
Multirate Signal Processing - Introduction, Decimation by a factor D, Interpolation by a factor I,
Sampling rate conversion by a rational factor I/D, Implementation of Sampling rate conversion:
Polyphase filter structures, Interchange of filters and down samplers/up samplers, Polyphase
structures for decimation and interpolation filters, Direct form and Polyphase FIR structures with
Time varying Coefficients.
UNIT II
Multirate Fir Filter Design - Multistage Implementation of Sampling Rate Conversion, Design
of FIR Filters for Sampling Rate Conversion, Applications Of Multirate signal processing: Design
of phase shifters, interfacing of Digital system with different sampling rates,Subband coding of
speech signals, Filter bank implementation :Digital Filter banks, Two channel filter banks(QMF),
Tree structured Filter banks,Unifrom DFT Filter banks , Decimated Filter banks.
UNIT III
Power Spectrum Estimation - Estimation of Spectra from Finite Duration Observations of a
Signals, The Periodgram,Use DFT in power Spectral Estimation, Non Parametric methods for
Power spectrum estimation: Bartlett, Welch and Blackman and Tukey Methods, Comparison of
performance of Non-Parametric Power Spectrum Estimation Methods.
UNIT IV
Parametric Method Of Power Spectrum Estimation - Parametric Methods for power spectrum
estimation, Relationship between Auto Correlation and Model Parameters, AR(Auto-Regressive)
Model parameters: Yule-Walker, Burg and Unconstrained Least Squares Methods, Sequential
Estimation, Moving Average (MA) and ARMA Models for power spectrum estimation Minimum
Variance Spectral estimates, Pisarenko Harmonic Decomposition Method, MUSIC Algorithm.
Text Books
1.
John G Proakis, Dimitris G Manolakis, Digital Signal Processing: Principles,
Algorithms and Applications, Fourth Edition, Prentice Hall India. (UNIT I-IV)
39

References
1.
2.
3.
4.
Sophocles.J.Orfamadis. (1988), Optimum signal processing: An introduction 2nd

edition, McGraw Hill, Newyork.
S.Thomas Alexander. (1986), Adaptive signal processing-Theory and Applications,
Springer Verlag.
Bernard Widrow, Samuel D.Strearns. (2005), Adaptive Signal Processing, Pearson
Education.
Simon Haykins, Tuley Adali (2010), Adaptive Signal Processing: Next Generation
Solutions, Wiley Publications.
40
ECVE 2005/4
HIGH SPEED DIGITAL DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Understand the interconnect characteristics.
Apply the design concepts to power distribution network and signaling circuits.
Understand the timing and synchronization of clock signals.
UNIT I
Modeling and Analysis of Wires - Geometry and Electrical Properties of Resistance,
Capacitance and Inductance, Electrical Models of Wires, Simple Transmission lines Lossless LC Transmission Lines, Lossy LRC Transmission lines, Special Transmission lines.
UNIT II
Power Distribution - Power Supply Network - Local Regulation - IR Drops - Area Bonding
On-chip Bypass Capacitors - Symbiotic Bypass Capacitors - Power Supply Isolation, Noise
Sources In Digital System - Power Supply Noise - Cross Talk - Intersymbol Interference.
UNIT III
Signaling Convention and Circuits - Signaling Modes for Transmission Lines -Signaling
Over Lumped Transmission Media - Signaling Over RC Interconnect - Driving Lossy LC
Lines - Simultaneous Bi-Directional Signaling, Terminations, Transmitter and Receiver
Circuits.
UNIT IV
Timing Convention And Synchronization - Timing Fundamentals - Timing Properties of
Clocked Storage Elements Encoding Timings: Signals and Events, Open Loop Timing Level Sensitive Clocking, Pipeline Timing. Closed Loop Timing, Clock Distribution,
Synchronization Failure and Metastability.
Text Books
1. William J. Dally & John W. Poulton (1998); Digital Systems Engineering,
Cambridge University Press, (UNIT I IV)
References
2. Howard Johnson & Martin Graham(1993), High Speed Digital Design: A Handbook
of Black Magic, Prentice Hall PTR.
3. Masakazu Shoji(1996), High Speed Digital Circuits, Addison Wesley Publishing
Company,
4. Jan M, Rabaey (2003), et all; Digital Integrated Circuits: A Design Perspective ,
Second Edition,
41
ECVE 2006/1
HARDWARE SOFTWARE CO-DESIGN
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Understand architectural languages and co-synthesis algorithms for co-design.
Understand prototyping and emulation systems and target architectures.
Apply compilation tools and techniques for embedded processor architectures.
UNIT I
Co-Design issues - Co-Design Models, Architectures, Languages, A Generic Co-Design
Methodology.
Co-Synthesis Algorithms - Hardware Software Synthesis Algorithms: Hardware Software
Partitioning Distributed System Co-Synthesis.
UNIT II
Prototyping and Emulation - Prototyping and Emulation Techniques, Prototyping and
Emulation Environments, Future Developments in Emulation and Prototyping Architecture
Specialization Techniques, System Communication Infrastructure
Target Architectures - Architecture Specialization Techniques, System Communication
Infrastructure, Target Architecture and Application System classes, Architecture for Control
Dominated Systems (8051-Architectures for High performance control), Architecture for Data
Dominated Systems (ADSP21060, TMS320C60), Mixed Systems.
UNIT III
Compilation Techniques and Tools for Embedded Processor Architectures - Modern
Embedded Architectures, Embedded Software Development Needs, Compilation
Technologies Practical Consideration in a Compiler Development Environment.
Design Specification and Verification - Design, Co-Design, The Co-Design Computational
Model, Concurrency Coordinating Concurrent Computations, Interfacing Components,
Design Verification, Implementation Verification, Verification Tools, Interface Verification
UNIT IV
Languages for System Level Specification and Design-I - System Level Specification,
Design Representation for System Level Synthesis, System Level Specification Languages,
Languages for System Level Specification and Design-II - Heterogeneous Specifications
and Multi-Language Co-Simulation the Cosyma System and Lycos System.
Text Books
1. Jorgen Staunstrup. (2009), Hardware / Software Co-Design Principles and Practice
Wayne Wolf Springer. (UNIT I - IV).
References
1. Jean-Michel Berge (1997), Hardware/Software Co-Design and Co- Verification,
Kluwer Publications.
42
ECVE 2006/2
EMBEDDED DEVICE DRIVERS
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Understands the Device Drivers need and loadable modules
Learn the debugging techniques and Advanced char driver operations
Understand fundamentals of hardware interface with kernel
Use and get acquaint to interrupt handling and kernel data types
UNIT I
An Introduction to Device Drivers - The Role of the Device Driver, Splitting the Kernel,
Classes of Devices and Modules, Security Issues, Version Numbering
Building and Running Modules - Setting Up Your Test System, The Hello World Module,
Kernel Modules Versus Applications, Compiling and Loading, The Kernel Symbol Table,
Preliminaries, Initialization and Shutdown, Module Parameters, Doing It in User Space
Char Drivers - The Design of scull, Major and Minor Numbers, Some Important Data
Structures, Char Device Registration, open and release, sculls Memory Usage, read and
write, Playing with the New Devices.
UNIT II
Debugging Techniques - Debugging Support in the Kernel, Debugging by Printing,
Debugging by Querying, Debugging by Watching, Debugging System Faults, Debuggers and
Related Tools.
Concurrency and Race Conditions - Pitfalls in scull, Concurrency and Its Management,
Semaphores and Mutexes, Completions, Spinlocks, Locking Traps, Alternatives to Locking
Advanced Char Driver Operations - octl, Blocking I/O, poll and select, Asynchronous
Notification, Seeking a Device, Access Control on a Device File.
UNIT III
Time, Delays, and Deferred Work - Measuring Time Lapses, Knowing the Current Time,
Delaying Execution, Kernel Timers, Tasklets, Workqueues
Allocating Memory - The Real Story of kmalloc, Lookaside Caches, get_free_page and
Friends, vmalloc and Friends, Per-CPU Variables, Obtaining Large Buffers
Communicating with Hardware - I/O Ports and I/O Memory, Using I/O Ports, An I/O Port
Example, Using I/O Memory.
UNIT IV
Interrupt Handling - Preparing the Parallel Port, Installing an Interrupt Handler,
Implementing a Handler, Top and Bottom Halves, Interrupt Sharing, Interrupt-Driven I/O
Data Types in the Kernel - Use of Standard C Types, Assigning an Explicit Size to Data
Items, Interface-Specific Types, Other Portability Issues, Linked Lists.
43

Text Books
1. Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman (2005), "LINUX
DEVICE DRIVERS" OReilly Third EditionBrian Gough 'An Introduction to GCC',
Network Theory Limited, UK
References
1. Robert Love, "Linux Kernel Development", , 3rd Edition, Addison-Wesley
Professiona.
2. Sreekrishnan Venkateswaran, "Essential Linux Device Drivers", Prentice Hall
44
ECVE 2006/4
VLSI SIGNAL PROCESSING
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Apply the concepts of pipelining, parallel processing, Retiming, Folding and unfolding
to optimize digital signal processing architectures
Analyze data flow in systolic architectures.
Minimize the computational complexity using fast convolution algorithms.
Analyze pipelining and parallel processing of IIR filters
UNIT I
Introduction to DSP - Typical DSP algorithms, DSP algorithms benefits, Representation of
DSP algorithms
Pipelining and Parallel Processing - Introduction, Pipelining of FIR Digital filters, Parallel
Processing, Pipelining and Parallel Processing for Low Power
UNIT II
Retiming - Introduction Definitions and Properties Solving System of Inequalities
Retiming Techniques
Folding - Introduction -Folding Transform - Register minimization Techniques Register
minimization in folded architectures folding of Multirate systems
Unfolding - Introduction An Algorithm for Unfolding Properties of Unfolding critical
Path, Unfolding and Retiming Applications of Unfolding
UNIT III
Systolic Architecture Design - Introduction Systolic Array Design Methodology FIR
Systolic Arrays Selection of Scheduling Vector Matrix Multiplication and 2D Systolic
Array Design Systolic Design for Space Representations contain Delays
Fast Convolution - Introduction Cook-Toom Algorithm Winogard algorithm Iterated
Convolution Cyclic Convolution Design of Fast Convolution algorithm by Inspection.
UNIT IV
Pipelined and Parallel Recursive and Adaptive Filters Introduction - Pipeline
Interleaving in Digital Filters, Pipelining in 1st-Order IIR Digital Filters, Pipelining in HigherOrder IIR Digital Filters, Parallel processing for IIR Filters, Combined Pipelining and Parallel
Processing for IIR Filters.
Text Books
1. Keshab K. Parthi. (1998), VLSI Digital Signal Processing- System Design and
Implementation, Wiley Inter Science. (Unit:I - IV)
45

References
1. Jose E. France, Yannis Tsividis. (1994) Design of Analog Digital VLSI Circuits for
Telecommunications and Signal Processing, Prentice Hall.
2. Medisetti V. K . (1995), VLSI Digital Signal Processing, IEEE Press (NY), USA.
46
ECVE 2006/4
PERL SCRIPTING LANGUAGE
Lecture :
Credits :
Final Examination:
40
60
Course Outcomes:
Upon Completion of the course the students will be able to
understand the PERL script constructs at every level of abstraction
understand the data structures in PERL scipt
apply PERL script to compile, execute and debug the code
UNIT-I
An Overview of Perl- Natural and artificial languages, variable syntax, verbs, an average
example, File handles, Operators- Some Binary Arithmetic Operators, String Operators
Assignment Operators, Unary Arithmetic Operators, Logical Operators, Some Numeric and
String Comparison Operators, Some File Test Operators, Regular Expressions - Quantifiers,
Minimal Matching, Nailing Things Down, Back references, List Processing, Unary & Binary
Operators.
UNIT-II
Statements and Declarations - Simple Statements, Compound Statements, if and unless
Statements, The given Statement, Loop Statements, The goto Operator, Paleolithic Perl Case
Structures, The Ellipsis Statement, Global Declarations, Scoped Declarations, Pragmas.
Pattern Matching - Pattern Matching Operators, Metacharacters and Metasymbols,
Character Classes, Quantifiers, Positions, Grouping and Capturing, Alternation, Staying in
Control, Fancy Patterns.
Subroutines - Syntax, Semantics, Passing References, Prototypes, Subroutine Attributes.
UNIT-III
Data Structures - Arrays of Arrays, Hashes of Arrays, Arrays of Hashes, Hashes of Hashes,
Hashes of Functions, More Elaborate Records, Saving Data Structures.
Packages - Symbol Tables, Qualified Names, The Default Package, Changing the Package,
Autoloading.
Modules - Loading Modules, Unloading Modules, Creating Modules, Overriding Built-in
Functions.
Objects - Brief Refresher on Object-Oriented Lingo, Perls Object System, Method
Invocation, Object Construction, Class Inheritance, Instance Destructors, Managing Instance
Data, Managing Class Data, The Moose in the Room.
Tied Variables - Tying Scalars, Tying Arrays, Tying Hashes, Tying Filehandles
UNIT-IV
Interprocess Communication - Signals, Files, Pipes, System V IPC, Sockets.
47

Compiling - The Life Cycle of a Perl Program, Compiling Your Code, Executing Your Code,
Compiler Backends, Code Generators, Code Development Tools.
The Command-Line Interface - Command Processing, Environment Variables.
The Perl Debugger - Debugger Commands, Debugger Customization, Unattended
Execution, Debugger Support, Profiling Perl.
Text Books
1. Larry Wall, Tom Christiansen, John Orwant, (2012) Programming PERL, 4th Edn.,
Oreilly Publications.
References
1. Randal L, Schwartz Tom Phoenix, (2000) Learning PERL,3rd Edn., Oreilly
Publications.
2. Tom Christiansen, Nathan Torkington, (2000) PERL Cookbook, 3rd Edn, Oreilly
Publications.
48
ECVE 2051
ANALOG AND DIGITAL CMOS CIRCUITS LAB
Lecture :
Credits :
Practical: 2 Hrs/ Week
Final Examination:
25
50
List of Experiments
Design an analog CMOS circuits with given specifications, completing the design flow
mentioned below:
a. Draw the schematic and perform the following
i. DC Analysis
ii. Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint
.
1. Common source, Common gate and Common Drain amplifier
2. Design a Common source amplifier with negative feed back
3. Design a Current mirror
4. Design a oscillator
5. Design a differential amplifier
6. Design a two stage op-amplifier
Design an digital CMOS circuits with given specifications, completing the design flow
mentioned below:
a. Draw the schematic and perform the following
i. DC Analysis
ii. Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint
1.
2.
3.
4.
5.
6.
4-bit adder and Subtractor

4-bit Register
4-bit Synchronous up-down counter
4-bit Comparator
Design a 4 bit R-2R based DAC
Design a 4-bit SAR based ADC
Text Books
1. J.Rabaey (1996), Digital Integrated circuits: a Design Perspective, PHI
2. Behzad Razavi (2002), Design of Analog CMOS Integrated Circuits Tata-Mc
GrawHill.
49

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Tech (VLSI Design& Embedded Systems) VR15

VLSI DESIGN AND EMBEDDED SYSTEMS

COURSE STRUCTURE VR15

SIDDHARTHA ENGINEERING COLLEGE

VIJAYAWADA 520 007

VELAGAPUDI RAMAKRISHNA SIDDHARTHA ENGINEERING COLLEGE: VIJAYAWADA - 7

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Low Power VLSI Design

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ELECTRONICS AND COMMUNICATION ENGINEERING

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4 Hrs/ Week Practical: 4

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4 Hrs/ Week Practical: 4

M.Tech (VLSI Design & Embedded Systems) VR15

M.Tech (VLSI Design & Embedded Systems) VR15

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M.Tech (VLSI Design & Embedded Systems) VR15

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M.Tech (VLSI Design & Embedded Systems) VR15

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M.Tech (VLSI Design & Embedded Systems) VR15

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M.Tech (VLSI Design & Embedded Systems) VR15

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M.Tech (VLSI Design & Embedded Systems) VR15

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RISC SPM: ALU

Task #2 Design of communication and signal processing sub modules.

Design of 8-bit LFSR

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