CAD & Design Flow: Motivation: Microelectronics Design Efficiency

11.
CAD & Design Flow
Institute of
Microelectronic
Systems
Motivation: Microelectronics Design

Efficiency
Efficiency
Moores
Law
???
Platform-based Design
Logic and Architectural Synthesis
Schematic Entry
Layout Editor
1970
1980
1990
2000
2010
Achieving required productivity by system-level

design methodologies
11: CAD & Design Flow
Institute of
Microelectronic
Systems
Example for Complex Systems: Embedded SoC

Embedded System-on-Chip
Properties
Sensors
Microcontroller
I/OModule
Potentially consisting of a large number of

components
Specialised to an application domain
reactive
Real-time capability
Memory
Constraints
ASIC
DSP
RF
Transc.
Costs
Power consumption
Latency
Required flexibility
Design Tasks
Definition of communication architecture which
is adequate to the applications structure
Mapping of the system specification on
available implementation components
Actuators
Institute of
Microelectronic
Systems
Platform-Based System Design: Platform Life-Cycle

DSP
core
Easy Implementation:
bus
CPU
core
Memory
API
OS
Generic
Platform
Platform
+
ApplicationSpecific
Additions
Lifecycle
Experiences
New Requirements
Feedback for future
platform generations
DSP
core
Specific
blocks
bus
CPU
core
Memory
Applications
API
OS
Drivers
multiple devices with similar basic functions
Institute of
Microelectronic
Systems
Project Management: System Design: V Model

System Properties and Constraints
Customer Application
Quality Assurance
Analysis of
System Requirements
System Delivery
Product
Cost Analysis
Validation
Quality Assurance
Design of
System Architecture
System Integration
Abstract Interfaces
Validation
Validation
Product
Level
Prototype Generation and/or

Manufacturing
Analysis of HW/SW
Component Requirements
HW/SW Co-Design
Quality Assurance
HW/SW
Component
Level
HW/SW
Integration
Implemented HW/SW Modules
HW/SW
IP Database
and Implementation
Level
HW and SW Component
Implementation
System
Level
Institute of
Microelectronic
Systems
Hardware/Software Co-Design
Specification
Co-Simulation
HW/SW-Partitioning
Communication Synth.
O.k., lets go
bottom-up now
HW-Specification
SW-Specification
Synthesis
Compilation
Placement/Routing
Real-Time OS
Heterogeneous HW-/SW-System
Institute of
Microelectronic
Systems
Classes of CAD Tools

Design Entry:
Graphical Editor (drawing schematic diagrams, physical layout, stick
layout diagrams, ...)
Language based circuit capture tools (for hardware description
languages like VHDL, Verilog, EDIF)
Design Validation:
Physical design verification tools (design rule checker, extractor,
LVS, schematic and electrical rule checker)
Design Simulation:
analog simulation: circuit level; behavioural level
digital simulations: circuit level, switch level, logic level, register transfer
level, architectural level, behavioural level;
thermal simulation: displaying heat dissipation on chip
Formal Verification Methods
Institute of
Microelectronic
Systems
Classes of CAD Tools

Design Implementation:
Layout Compilers (stick2layout, macrocell generators, datapath
compilers)
Layout Structuring & Optimization:
Layout Compaction
Placement and Routing
Logic Synthesis
Finite State Machine (FSM) Synthesis
Architectural Synthesis
Management of Design Projects:
Design Databases:
keep different versions (current, backup 1, ..., backup n) and views of a
design object (schematic, simulation netlist, stick diagram, physical
layout, ...) in database
Institute of
Microelectronic
Systems
Full Custom Design: Design Entry

Full Custom Design
With Full Custom Design techniques, the
designer is able to individually specify the
geometrical layout of the integrated circuit
(transistor size
[channel length, channel width, shape, ...],
transistor placement, wire width, ...).
The designer has the option to manually
optimize
the layout
the most dense/area efficient layouts
can be generated using the full
custom design styles.
Layout Editor
and Design Rule Check
www.tanner.com
Hand-Crafted Layout:
The layout is drawn in form of rectangles and polygons on different layers using a graphics
editor.
The designer has to know a large set of process dependent design rules.
The mask layout is generated as drawn on the screen: direct influence to component
placement, to important parameters as W and L of transistors, wire widths, ...
Institute of
Microelectronic
Systems

Tool internal Design Representation: Geometrical Specification Language
The layout is specified in textual form giving either the position and layer of rectangles
(similar to hand crafted layout) or lines (as in stick diagrams).
Since
programming language constructs like

parameterized macros (to be used for layout segments as cells, ...),
loops (while, repeat, for, ...), and
conditional statements (if, case, ...) may be available,
parameterized layouts (e.g. generic transistor with W and L as parameters, cells for
different bit widths, sss) can be described using geometrical specification languages.
Used in a large number of macrocell compilers.
Institute of
Microelectronic
Systems
10

Example for a simplified geometrical specification language:
B x y dx dy
Ln
Mn
E
Cnxym
Q
Box with length dx, width dy, an lower left hand corner placed at (x,y)
Layout level (layer) for the box definiitions that follow
Start of macro definition n
End of macro definition
Call for macro number n with translation x,y and orientation m.
End of layout file
MOS Layer definitions:
Layer
CMOS
NMOS
1
2
3
4
5
8
9
n-diffusion
p-diffusion
polysilicon
metal
contact
n-well
overglass
n-diffusion
ion implant
polysilicon
metal
contact
-overglass
Institute of
Microelectronic
Systems
11

Cell Orientations:
Orientation
1
2
3
4
5
6
7
8
Description
no rotation
rotate 90 counterclockwise
mirror about y-axis
rotate 90 counterclockwise and mirror about y-axis
Institute of
Microelectronic
Systems
12
Full custom layout

(hand crafted or generated out of a stick
diagram resp. a layout description)
Corresponding geometrical specification

file and schematic diagram
Institute of
Microelectronic
Systems
13

Stick Diagram:
The layout is drawn in form of lines and polygons on differentlayers using a
graphics editor.
A stick--to--layout converter together with a compactor and a description of the
process design rules is then used to generate the rectangle
based layout.
The designer can draw almost process and design rule independent symbolic
layouts. Process adaption is done by the converter/compactor.
Converter constraints (cell dimensions, channel widths / lengths of transistors, ...)
can be specified.
Stick Diagram Conventions:
Diffusion Areas:
Polysilicon Lines:
Metal Lines:
Contacts:
green
red
blue
black
(b/w: dotted line)

(b/w: dashed line)
(b/w: solid line)
Example: Stick Diagram of a Transistor:
Institute of
Microelectronic
Systems
14
Full Custom Design: Stick Diagrams
Memory cell schematic and corresponding

stick diagram
Institute of
Microelectronic
Systems
15
Full Custom Design: Design Flow

Stick Diagram
Editor
Symbol Generation
Schematic Entry
stick2layout
Converter
and Compactor
Simulation Netlist
Extraction and Simulation (SPICE)
Layout Editor
Block Layout
Cells
Floorplanning
Placement & Routing
Mask Layout Data
Fabrication
Fabrication Test Pattern
Circuit Simulation (SPICE)

Timing Analysis
Test Pattern Generation
Design Analysis
DRC, ERC
Circuit Extraction
LVS
Institute of
Microelectronic
Systems
16
Cell Based Design

Cell based Design approaches rely on layout components predefined and provided
by a silicon foundry. Several implemenation styles can be distinguished:
Standard Cells:
layout blocks predefined by silicon foundry
full process sequence (amount of mask layers) for chip fabrication required
Gate Arrays:
Linear Gate Arrays:
pre-fabricated diffusion and poly layers (regular structures, e.g. transistors)
customized interconnect structures (wires in metal 1 and metal 2)
fixed size interconnect areas (channels)
Sea of Gate Array
discussed later in
this lecture
pre-fabricated diffusion and poly layers (regular structures e.g. transistors)

customized interconnect structures (wires in metal 1 and metal 2)
variable size interconnect areas (channels) over unused transistors
Institute of
Microelectronic
Systems
17
Cell based Full Custom Design: Design Flow

Symbol Generation
Cell
Library
Graphical
Data
Macrocell
Specification/Compilation
Simulation Netlist
Extraction
Schematic Entry
Simulation Models
Layout
Data
Placement:
Standard Cells
Macro Cells
I/O Cells
Logic Simulation
Fault Simulation
Timing Analysis
Test Pattern Generation
Routing:
Channel Generation
Global Routing
Detailed Routing
Place &
Route
Optimization
Design Analysis
DRC, ERC
Circuit Extraction
LVS
Mask Layout Data
Fabrication
Parasitic
Wire Capacitances /
Delay Backannotation
Fabrication Test Pattern
Institute of
Microelectronic
Systems
18
Standard Cell Full Custom Design
Institute of
Microelectronic
Systems
19
Design Verification
Physical Design Rule Check:
Physical design rule checks (DRCs) are
performed to guarantee the conformity of a
layout design to the
silicon vendor's set of design rules. Design
rules are defined between objects on the
same layer (minimum width, minimum
spacing) as well as for objects on different
layers (minimum spacing, overlapping,
extension).
Minimum width
Minimum spacing
Overlapping
Extension
Design rule violations are usually reported in

the physical layout using a graphics editor.
Sometimes, also a tabular form indicating the
location and type of design rule violation can
be generated.
Institute of
Microelectronic
Systems
20
Design Verification
Extraction:
Circuit Level Extraction can be used to create a netlist for circuit level simulations
(e.g. SPICE, ...). The netlist consists of MOS transistors (including geometrical
parameters as W / L, parasitic capacitances), resistors, capacitances, diodes, ...
Switch Level Extraction: can be used to create a netlist which can be processed by a
switch level simulator. The resulting netlist consists of MOS transistors and parasitic
capacitances (to model storage effects in MOS circuits).
Parasitics Extraction: is used in conjunction with cell based design techniques. Since
wire delay is dependent on the parasitic capacitance of a wire, parasitic capacitances of
nets and input capacitances of other gates connected to an output can be used to
estimate the extrinsic delays (Note: intrinsic delays [i.e. the delay of unloaded gates] are
fetched from the cell library's simulation model data).
Schematic Extraction: is executed to generate the connectivity data out of a

graphical representation (schematic diagram) of a circuit module. The connectivity data is
forwarded to a netlister which provides the information required e.g. by simulation tools
(the simulators cannot operate on graphical data, they require netlists in a textual
format). This kind of extraction is usually required in pre-layout design specification
phases.
Institute of
Microelectronic
Systems
21
Design Verification
LVS:
The layout-versus-schematic (LVS) comparison tool checks the equivalence of the layout and its schematic.
The tool can be used to find wrong connections or parameter mismatch (as W/L of transistors, ...) between
a schematic and its physical layout representation.
Schematic / Electrical Rule Check (SRC / ERC):

To verify schematics used e.g. in cell based designs, a schematic rulechecker can find schematic rule
violations (like the following examples):
Warnings:
unconnected (floating) wire segments
open outputs
exceeded fanout
Errors:
open inputs (undefined input value!)
number of bits differ for 2 buses connected together
number of input/output pins in a schematic differs from its symbol representation ( --> pins are
not accessible / not present at higher levels of schematic hierarchy)
more than one active driver connected to a net at the same time
Institute of
Microelectronic
Systems
22
Simulation
Goal of Simulation:
Validation of the system, logic timing, and electricial behaviour
Verify testability aspects
Software development based on hardware simulation models
Simulator Classification:
Level
Primitives
observable
Values
Timing
Model
RT
Gate
registers, user coded

primitives, busses, etc.
gates
bit strings,
vectors
bits
Switch
transistors, capacitators
bits
Electricial
capacitators, resistors,
inductors, diodes etc.
real values
discrete
time set
continuous
or discrete
continuous
or discrete
continuous
time set
Institute of
Microelectronic
Systems
23
Simulation: Models
Signal Modelling:
values which exist in real circuits (0, 1, high impedance, oscillation, ...)
values which exist only in the simulator (unknown, transition, ...)
boolean logic set not sufficient
3-valued Logic:
Example:
logic zero
logic one
unknown
=
=
=
0
1
U
AND
0
1
U
1
0
1
U
U
0
U
U
0
0
0
0
Problems:
Pessimism of U value (for example: circuit initialisation, spikes)
Logic values are often not sufficient (value strength needed)
Institute of
Microelectronic
Systems
24
Simulation: Models
Circuit and Delay Modelling:
Circuit is built up by simulator primitives
Modelling of the timing/delay behaviour:
:
(n) = n * :
t1, t2, t3, ...:
(t+1-t):
basic time unit

delay of the gate
clock time of a synchronous circuit
t = m*
Timing Models:
=0
(n) = constant
(n) = user-specified
Zero Delay:
Unit Delay:
Nominal delay:
Institute of
Microelectronic
Systems
25
Simulation: Models
Advanced Logic Simulators:
Introduction of signal strength additional to logic values for driver and bus modelling
A : active, e.g. low impedance driver
P : passive, e.g. high impedance driver (depletion load)
S : storing, e.g. capacitive stored state
X : active indeterminate (e.g. active or storing)
Y : passive indeterminate (e.g. passive or storing)
Z : high impedance
Instead of simple logical values, signals are used for simulation. A signal consists of a logical value and a
strength.
Logical Values = {0,1,X}
A0 A1 AX P0 P1 PX S0 S1 SX X0 X1 XX Y0 Y1 YX ZZ
16 states
A0 A0 AX AX A0 A0 A0 A0 A0 A0 A0 AX AX A0 A0 A0 A0
Overview
on
Signal
Combinations
A1
AX
P0
P1
PX
S0
S1
SX
X0
X1
XX
Y0
Y1
YX
ZZ
A1
A1
AX
A1
AX
P0
A1
AX
PX
P1
A1
AX
PX
PX
PX
A1
AX
P0
P1
PX
S0
A1
AX
P0
P1
PX
SX
S1
Institute of
Microelectronic
Systems
A1
AX
P0
P1
PX
SX
SX
SX
AX
AX
X0
XX
XX
X0
XX
XX
X0
A1
AX
XX
X1
XX
XX
X1
XX
XX
X1
AX
AX
XX
XX
XX
XX
XX
XX
XX
XX
XX
A1
AX
P0
PX
PX
Y0
YX
YX
X0
X1
XX
Y0
A1
AX
PX
P1
PX
YX
Y1
YX
X0
XX
XX
YX
Y1
A1
AX
PX
PX
PX
YX
YX
YX
XX
XX
XX
YX
YX
YX
A1
AX
P0
P1
PX
S0
S1
SX
X0
X1
XX
Y0
Y1
YX
ZZ
26
Simulation: Models
Example: Driver Modelling:
Competing Drivers at a Bus
Institute of
Microelectronic
Systems
27
Simulation
www.modelsim.com
Institute of
Microelectronic
Systems
28
Simulation: Techniques
Simulation Techniques:
Compiler-driven technique:
Problems:
Feedbacks
Sorting of gate netlist
Zero delay model
Entire circuit is simulated
Event-driven simulation ...
Switch-Level Simulation:
well-suited so simulate digital MOS
circuits
no fixed direction of signal flow
transistor modeled as a switch
with three states: open, closed,
unknown
algebraic or RC models
Institute of
Microelectronic
Systems
29
Simulation: MOS Transistor Model

Ideal Switch Transistor Model:
Drain
Logic
(Gate)
1
0
X
Gate
n-Channel
Enhancement
Closed
Open
Unknown
p-Channel
Enhancement
Open
Closed
Unknown
n-Channel
Enhancement
REFF
infinity
[REFF, infinity]
p-Channel
Enhancement
infinity
REFF
[REFF, infinity]
Depletion
Weak
Weak
Weak
Remarks:
Switch transition time is
assumed to be zero or
some nominal value
Unknown states can
cause problems
Source
Linear Switch Transistor Model:

Drain
Gate
REFF
Logic
(Gate)
1
0
X
Depletion
REFF
REFF
REFF
Remarks:
In the linear model,
node capacitance and
devices resistance are
used to compute output
logic levels and
transition time
Ratio errors can be
detected
Source
Institute of
Microelectronic
Systems
30
Executable Specifications: VHDL

VHDL: Very high speed integrated Circuits Hardware Description Language
architecture structural of first_tap is

Different types of modeling:
signal x_q,red : std_logic_vector(bitwidth-1 downto 0);

signal mult
: std_logic_vector(2*bitwidth-1 downto 0);
Data Flow
Behaviour
Structure
begin
delay_register:
process(reset,clk)
begin
if reset='1' then
x_q <= (others => '0');
elsif (clk'event and clk='1') then
x_q <= x_in;
end if;
end process;
VHDL is used for:

Modelling
Simulation
Hardware Synthesis
mult <= signed(coef)*signed(x_q);
Institute of
Microelectronic
Systems
31
Design Flow: IC Design with High-Level-Entry

architecture structural of first_tap is
signal x_q,red : std_logic_vector(bitwidth-1 downto 0);
signal mult : std_logic_vector(2*bitwidth-1 downto 0);
VHDL-Description
Gate-Level
Netlist
begin
delay_register:
process(reset,clk)
begin
if reset='1' then
x_q <= (others => '0');
elsif (clk'event and clk='1') then
x_q <= x_in;
end if;
end process;
RTL-Synthesis
(Synopsys)
mult <= signed(coef)*signed(x_q);
Placement &
Routing
Production
(Cadence/Mentor)
Layout
ASIC
Institute of
Microelectronic
Systems
32
Future Outlook: Networks-on-Chip

Regular platform integrating
independent subsystems
combine structures of
todays SoC complexity
Generic
Interface
Separation between
Communication and
Computation
ASIC
Router
FPGA
MEM
High-Speed
Interconnect
Institute of
Microelectronic
Systems
33
NoC-based design flow: Hardware/Software

Classical Flow
NoC-based Flow
Co-Design
Specification
Specification
Co-Simulation
Implementation
HW/SW-Partitioning
Communication Synth.
HW-Specification
SW-Specification
Synthesis
Compilation
Placement/Routing
Real-Time OS
SW Library
NoC Mapping
NoC Placement
HW Library
Dynamic
Allocation/ReMapping during
Operation
Heterogeneous HW-/SW-System
Institute of
Microelectronic
Systems
34
Application Scenario: Mobile Video Terminal

Different Configurations for:
High Quality (Resolution) Downstreaming
Low-Power Mode (Quality Reduction)
Image Compression and Upstreaming
Multi-Stream Modes
Single Chip Mobile Terminal
Mobile
Service
Base
Station(s)
RF
Centr.
CTRL
DISPLAY
Displ.
CTRL
Institute of
Microelectronic
Systems
35

CAD & Design Flow: Motivation: Microelectronics Design Efficiency

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CAD & Design Flow: Motivation: Microelectronics Design Efficiency

Uploaded by

Copyright:

Available Formats

11.

CAD & Design Flow

Motivation: Microelectronics Design

Logic and Architectural Synthesis

Achieving required productivity by system-level

11: CAD & Design Flow

Example for Complex Systems: Embedded SoC

Potentially consisting of a large number of

11: CAD & Design Flow

Platform-Based System Design: Platform Life-Cycle

multiple devices with similar basic functions

11: CAD & Design Flow

Project Management: System Design: V Model

Prototype Generation and/or

Implemented HW/SW Modules

11: CAD & Design Flow

11: CAD & Design Flow

Classes of CAD Tools

Formal Verification Methods

11: CAD & Design Flow

Classes of CAD Tools

11: CAD & Design Flow

Full Custom Design: Design Entry

11: CAD & Design Flow

Full Custom Design: Design Entry

programming language constructs like

Used in a large number of macrocell compilers.

11: CAD & Design Flow

Full Custom Design: Design Entry

MOS Layer definitions:

11: CAD & Design Flow

Full Custom Design: Design Entry

11: CAD & Design Flow

Full Custom Design: Design Entry

Full custom layout

Corresponding geometrical specification

11: CAD & Design Flow

Full Custom Design: Design Entry

(b/w: dotted line)

Example: Stick Diagram of a Transistor:

11: CAD & Design Flow

Full Custom Design: Stick Diagrams

Memory cell schematic and corresponding

11: CAD & Design Flow

Full Custom Design: Design Flow

Mask Layout Data

Fabrication Test Pattern

Circuit Simulation (SPICE)

Cell Based Design

Sea of Gate Array

pre-fabricated diffusion and poly layers (regular structures e.g. transistors)

11: CAD & Design Flow

Cell based Full Custom Design: Design Flow

Mask Layout Data

11: CAD & Design Flow

Fabrication Test Pattern

Standard Cell Full Custom Design

11: CAD & Design Flow

Design rule violations are usually reported in

11: CAD & Design Flow

Schematic Extraction: is executed to generate the connectivity data out of a

11: CAD & Design Flow

Schematic / Electrical Rule Check (SRC / ERC):