EERF 6330- RF IC Design

Frequency Synthesizers

Prof. Bhaskar Banerjee

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Components of a Frequency Synthesizer

Function of a frequency synthesizer is to generate a stable
frequency f0 from a reference frequency fref

Components:
- Phase/frequency detector (PFD): outputs a signal that is
proportional to the difference between the phase/frequency of the
two input periodic signals
- LPF: reduce phase noise and enhance spectral purity
- VCO: takes a filtered o/p of the PFD and generates an output
frequency
- Divider: scales the output frequency by a factor of N
Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Phase Frequency Detectors

Types:
Analog multipliers
Exclusive OR gates (XOR)
Sequential phase detectors

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Analog Multiplier as a Phase Detector

Mathematically:
AB cos(t) cos(t + ) =

AB
2 [cos(

cos(2t + )]

Looking only at the low-frequency term,

the o/p of the multiplier is:
Vout = AB
2 cos( )
The phase detector gain constant
is given as:
KD

d
= (Vout ) =
dt

AB
2

sin( ) (V/rad)

Note that KD is zero when is zero and greatest

when is 90.
To maximize the useful phase range, the loop should be arranged to
lock to a phase difference of 90 - Quadrature Phase Detector.
Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Analog Modulator as a Phase Detector

Schematic diagram:
Note that sgn(x) = 1 if x > 0 and -1 if x < 0.

Vout,avg

4 AB
2
=
cos() = AB cos()
2

The gain of this phase detector is 4/ times larger than the analog multiplier.
The phase detector constant is given as:
KD

d
= (Vout )|=
dt

/2

AB

Note: Because the modulator phase detector has more than just the
fundamental, it can lock on to a harmonic (or subharmonic) of the
fundamental (which may be desirable or undesirable).
Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Exclusive OR-gate as a Phase Detector

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Sequential Phase Detectors

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Phase Detectors vs Frequency Detectors

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

Conceptual Illustration of a PFD

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

PFD Implementation

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

10

Capture Process of a PLL

In the unlocked condition, the VCO runs at the frequency
corresponding to zero applied dc voltage at its control input.
This frequency is called the free running frequency of the VCO.

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

11

Loop Filters
Loop filter: Used to reduce the unwanted components in the PLL.

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Loop Filters - contd.

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Loop Filters - example

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Loop Filters - example

Example:
For the PLL of the previous example, find vo(t) if the input signal is
frequency modulated so that:
i (t) = 2 (500 Hz)[1 + 0.1 sin(2 102 )t].

Solution:

1
Kv
Kv
=
Kv + j
Ko Kv + j2 100 =200

500
1
1
=
=
(0.39 j0.48)
2000
500 + j628
2000

Vo (j)
1
=
i (j)
Ko

|i (j)| = 0.1(1000 ) = 100 = 50(2 )

50
50
) Vo (j ) =
(0.39 j0.48) =
(0.62\ 51 ) = 0.031\ 51
1000
1000
vo (t) = 0.031 sin[(2 102 )t
Bhaskar Banerjee, EERF 6330, Sp2013, UTD

51 ]
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Higher order loop filters

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Loop Lock Range

Loop lock range is the frequency range about 0 for which the PLL
maintains:
!i = !osc

L = osc = KD Ko

= Kv

where /2 is the limit for the phase detector.

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Capture Range
The capture range, C, is the range of input frequencies for which the
initially unlocked loop will lock on to an input signal of i.

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

18

Charge Pumps
In PLLs with a filter, the avg value of the PFD output is obtained by depositing
charge onto a capacitor during each phase/frequency comparison and allowing the
charge to decay afterwards.
An ideal charge pump combined with the PFD provides an infinite dc gain with
passive filters, which result in the unbounded pull-in range for 2nd order and
higher-order PLLs.

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Charge Pumps
Non-idealities:
Leakage Current: Small currents that flow when the switch is off.
Mismatches in the charge pump: the up and down (charge/discharge) currents are unequal.
Timing mismatch in the PFD: any mismatch in the time at which the PFD provides the up and
down currents.
TYPES of charge pumps:
Conventional Tri-State
Low power consumption, moderate speed, moderate clock slew
Low power frequency synthesizers, digital clock generators
Current Steering
Static current consumption, high speed, moderate clock slew
High speed PLL (> 100 MHz), translation loop, digital clock generators
Differential input, SE output
Medium power, moderate speed, low clock slew
Low-skew digital clock generators, frequency synthesizers
Fully Differential
Static current consumption, high speed (>100 MHz)
Digital clock generators, translation loop, frequency synthesizers (with on-chip filter)

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Basic Architecture of a Frequency

Synthesizer

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Basic Architecture of a Frequency

Synthesizer

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Frequency Synthesizer with Dual Modulus

Prescalar

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Example

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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Fractional-N Frequency Synthesizer

Bhaskar Banerjee, EERF 6330, Sp2013, UTD

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