29/06/2015

IntroductiontoICandSPIprotocolsByteParadigmSpeedupembeddedsystemverification

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IntroductiontoICandSPIprotocols
ICvsSPI
Today,atthelowendofthecommunicationprotocols,wefindIC(forInterIntegratedCircuit,protocol)andSPI(forSerialPeripheral
Interface).Bothprotocolsarewellsuitedforcommunicationsbetweenintegratedcircuits,forslowcommunicationwithonboard
peripherals.AttherootsofthesetwopopularprotocolswefindtwomajorcompaniesPhilipsforICandMotorolaforSPIandtwo
differenthistoriesaboutwhy,whenandhowtheprotocolswerecreated.
TheICbuswasdevelopedin1982itsoriginalpurposewastoprovideaneasywaytoconnectaCPUtoperipheralschipsinaTVset.
PeripheraldevicesinembeddedsystemsareoftenconnectedtothemicrocontrollerasmemorymappedI/Odevices.Onecommonwaytodo
thisisconnectingtheperipheralstothemicrocontrollerparalleladdressanddatabusses.ThisresultsinlotsofwiringonthePCB(printed
circuitboard)andadditionalgluelogictodecodetheaddressbusonwhichalltheperipheralsareconnected.Inordertospare
microcontrollerpins,additionallogicandmakethePCBssimplerinorderwords,tolowerthecostsPhilipslabsinEindhoven(The
Netherlands)inventedtheInterIntegratedCircuit,IICorICprotocolthatonlyrequires2wiresforconnectingalltheperipheraltoa
microcontroller.Theoriginalspecificationdefinedabusspeedof100kbps(kilobitspersecond).Thespecificationwasreviewedseveral
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times,notablyintroducingthe400kbpsspeedin1995andsince1998,3.4Mbpsforevenfasterperipherals.
ItseemstheSerialPeripheralProtocol(SPI)wasfirstintroducedwiththefirstmicrocontrollerderivingfromthesamearchitectureasthe
popularMotorola68000microprocessor,announcedin1979.SPIdefinedtheexternalmicrocontrollerbus,usedtoconnectthe
microcontrollerperipheralswith4wires.UnlikeIC,itishardtofindaformalseparatespecificationoftheSPIbusforadetailed
officialdescription,onehastoreadthemicrocontrollersdatasheetsandassociatedapplicationnotes.
SPI
SPIisquitestraightforwarditdefinesfeaturesanydigitalelectronicengineerwouldthinkofifitweretoquicklydefineawayto
communicatebetween2digitaldevices.SPIisaprotocolon4signallines(pleaserefertofigure1):
AclocksignalnamedSCLK,sentfromthebusmastertoallslavesalltheSPIsignalsaresynchronoustothisclocksignal
Aslaveselectsignalforeachslave,SSn,usedtoselecttheslavethemastercommunicateswith
Adatalinefromthemastertotheslaves,namedMOSI(MasterOutSlaveIn)
Adatalinefromtheslavestothemaster,namedMISO(MasterInSlaveOut).

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SPIisasinglemastercommunicationprotocol.Thismeansthatonecentraldeviceinitiatesallthecommunicationswiththeslaves.When
theSPImasterwishestosenddatatoaslaveand/orrequestinformationfromit,itselectsslavebypullingthecorrespondingSSlinelow
anditactivatestheclocksignalataclockfrequencyusablebythemasterandtheslave.ThemastergeneratesinformationontoMOSIline
whileitsamplestheMISOline(refertofigure2).

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Fourcommunicationmodesareavailable(MODE0,1,2,3)thatbasicallydefinetheSCLKedgeonwhichtheMOSIlinetoggles,the
SCLKedgeonwhichthemastersamplestheMISOlineandtheSCLKsignalsteadylevel(thatistheclocklevel,highorlow,whenthe
clockisnotactive).Eachmodeisformallydefinedwithapairofparameterscalledclockpolarity(CPOL)andclockphase(CPHA).

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Amaster/slavepairmustusethesamesetofparametersSCLKfrequency,CPOL,andCPHAforacommunicationtobepossible.If
multipleslavesareused,thatarefixedindifferentconfigurations,themasterwillhavetoreconfigureitselfeachtimeitneedsto
communicatewithadifferentslave.
ThisisbasicallyallwhatisdefinedfortheSPIprotocol.SPIdoesnotdefineanymaximumdatarate,notanyparticularaddressingscheme
itdoesnothaveaacknowledgementmechanismtoconfirmreceiptofdataanddoesnotofferanyflowcontrol.Actually,theSPImasterhas
noknowledgeofwhetheraslaveexists,unlesssomethingadditionalisdoneoutsidetheSPIprotocol.Forexampleasimplecodecwont
needmorethanSPI,whileacommandresponsetypeofcontrolwouldneedahigherlevelprotocolbuiltontopoftheSPIinterface.SPI
doesnotcareaboutthephysicalinterfacecharacteristicsliketheI/Ovoltagesandstandardusedbetweenthedevices.Initially,mostSPI
implementationusedanoncontinuousclockandbytebybytescheme.Butmanyvariantsoftheprotocolnowexist,thatuseacontinuous
clocksignalandanarbitrarytransferlength.
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IC
ICisamultimasterprotocolthatuses2signallines.ThetwoICsignalsarecalledserialdata(SDA)andserialclock(SCL).Thereis
noneedofchipselect(slaveselect)orarbitrationlogic.Virtuallyanynumberofslavesandanynumberofmasterscanbeconnectedonto
these2signallinesandcommunicatebetweeneachotherusingaprotocolthatdefines:
7bitsslaveaddresses:eachdeviceconnectedtothebushasgotsuchauniqueaddress
datadividedinto8bitbytes
afewcontrolbitsforcontrollingthecommunicationstart,end,directionandforanacknowledgmentmechanism.
Thedataratehastobechosenbetween100kbps,400kbpsand3.4Mbps,respectivelycalledstandardmode,fastmodeandhighspeed
mode.SomeICvariantsinclude10kbps(lowspeedmode)and1Mbps(fastmode+)asvalidspeeds.
Physically,theICbusconsistsofthe2activewiresSDAandSCLandagroundconnection(refertofigure4).Theactivewiresarebothbi
directional.TheI2CprotocolspecificationstatesthattheICthatinitiatesadatatransferonthebusisconsideredtheBusMaster.
Consequently,atthattime,alltheotherICsareregardedtobeBusSlaves.

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First,themasterwillissueaSTARTcondition.ThisactsasanAttentionsignaltoalloftheconnecteddevices.AllICsonthebuswill
listentothebusforincomingdata.
ThenthemastersendstheADDRESSofthedeviceitwantstoaccess,alongwithanindicationwhethertheaccessisaReadorWrite
operation(Writeinourexample).Havingreceivedtheaddress,allICswillcompareitwiththeirownaddress.Ifitdoesntmatch,they
simplywaituntilthebusisreleasedbythestopcondition(seebelow).Iftheaddressmatches,however,thechipwillproducearesponse
calledtheACKNOWLEDGEsignal.
Oncethemasterreceivestheacknowledge,itcanstarttransmittingorreceivingDATA.Inourcase,themasterwilltransmitdata.Whenall
isdone,themasterwillissuetheSTOPcondition.ThisisasignalthatstatesthebushasbeenreleasedandthattheconnectedICsmay
expectanothertransmissiontostartanymoment.
Whenamasterwantstoreceivedatafromaslave,itproceedsthesameway,butsetstheRD/nWRbitatalogicalone.Oncetheslavehas
acknowledgedtheaddress,itstartssendingtherequesteddata,bytebybyte.Aftereachdatabyte,itisuptothemastertoacknowledgethe
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receiveddata(refertofigure5).

STARTandSTOPareuniqueconditionsonthebusthatarecloselydependentoftheICbusphysicalstructure.Moreover,theIC
specificationstatesthatdatamayonlychangeontheSDAlineiftheSCLclocksignalisatlowlevelconversely,thedataontheSDAline
isconsideredasstablewhenSCLisinhighstate(refertofigure6hereafter).

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Atthephysicallayer,bothSCLandSDAlinesareopendrainI/Oswithpullupresistors(refertofigure4).Pullingsuchalinetogroundis
decodedasalogicalzero,whilereleasingthelineandlettingitflowisalogicalone.Actually,adeviceonaICbusonlydriveszeros.
HerewecometowhereICistrulyelegant.Associatingthephysicallayerandtheprotocoldescribedaboveallowflawlesscommunication
betweenanynumberofdevices,onjust2physicalwires.
Forexample,whathappensif2devicesaresimultaneouslytryingtoputinformationontheSDAand/orSCLlines?
Atelectricallevel,thereisactuallynoconflictatallifmultipledevicestrytoputanylogiclevelontheICbuslinessimultaneously.Ifone
ofthedriverstriestowritealogicalzeroandtheotheralogicalone,thentheopendrainandpullupstructureensuresthattherewillbeno
shortcutandthebuswillactuallyseealogicalzerotransitingonthebus.Inotherwords,inanyconflict,alogiczeroalwayswins.
Thebusphysicalimplementationalsoallowsthemasterdevicestosimultaneouslywriteandlistentothebuslines.Thisway,anydeviceis
abletodetectcollisions.Incaseofaconflictbetweentwomasters(oneofthemtryingtowriteazeroandtheotheroneaone),themaster
thatgainsthearbitrationonthebuswillevennotbeawaretherehasbeenaconflict:onlythemasterthatlooseswillknowsinceitintends
towritealogiconeandreadsalogiczero.Asaresult,amasterthatloosesarbitrationonaICwillstoptryingtoaccessthebus.Inmost
cases,itwilljustdelayitsaccessandtrythesameaccesslater.
Moreover,theICprotocolalsohelpsatdealingwithcommunicationproblems.AnydevicepresentontheIClistenstoitpermanently.
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PotentialmastersontheICdetectingaSTARTconditionwillwaituntilaSTOPisdetectedtoattemptanewbusaccess.SlavesontheIC
buswilldecodethedeviceaddressthatfollowstheSTARTconditionandcheckifitmatchestheirs.Alltheslavesthatarenotaddressed
willwaituntilaSTOPconditionisissuedbeforelisteningagaintothebus.Similarly,sincetheICprotocolforeseesactivelow
acknowledgebitaftereachbyte,themaster/slavecoupleisabletodetecttheircounterpartpresence.Ultimately,ifanythingelsegoes
wrong,thiswouldmeanthatthedevicetalkingonthebus(masterorslave)wouldknowitbysimplycomparingwhatitsendswithwhatis
seenonthebus.Ifadifferenceisdetected,aSTOPconditionmustbeissued,whichreleasesthebus.
Additionally,IChasgotsomeadvancedfeatures,likeextendedbusaddressing,clockstretchingandtheveryspecific3.4Mbpshighspeed
mode.
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10bitsdeviceaddressing
AnyICdevicemusthaveabuiltin7bitsaddress.Intheory,thismeansthattherewouldbeonly128differentICdevicestypesinthe
world.Practically,therearemuchmoredifferentICdevicesanditisahighprobabilitythat2deviceshavethesameaddressonaICbus.
Toovercomethislimitation,devicesoftenhavemultiplebuiltinaddressesthattheengineercanchosebythoughexternalconfigurationpins
onthedevice.TheICspecificationalsoforeseesa10bitsaddressingschemeinordertoextendtherangeofavailabledevicesaddress.
Practically,thishasgotthefollowingimpactontheICprotocol(refertofigure7):
Twoaddresswordsareusedfordeviceaddressinginsteadofone.
ThefirstaddresswordMSBsareconventionallycodedas11110soanydeviceonthebusisawarethemastersendsa10bitsdevice
address.

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Actually,thereareotherreservedaddresscodesforspecifictypesofaccesses(refertotable1).Fordetailsaboutthem,pleaserefertothe
ICspecification.

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Clockstretching
InanICcommunicationthemasterdevicedeterminestheclockspeed.TheSCLsignalisanexplicitclocksignalonwhichthe
communicationsynchronizes.
However,therearesituationswhereanICslaveisnotabletocooperatewiththeclockspeedgivenbythemasterandneedstoslowdown
alittle.Thisisdonebyamechanismreferredtoasclockstretchingandismadepossiblebytheparticularopendrain/pullupstructureofa
ICbusline.
AnICslaveisallowedtoholddowntheclockifitneedstoreducethebusspeed.Themasterontheotherhandisrequiredtoreadbackthe
clocksignalafterreleasingittohighstateandwaituntilthelinehasactuallygonehigh.
Highspeedmode
Fundamentally,theuseofpullupstosetalogiconelimitsthemaximumspeedofthebus.Thismaybealimitingfactorformany
applications.Thisiswhythe3.4Mbpshighspeedmodewasintroduced.Priortousingthismode,thebusmastermustissueaspecificHigh
SpeedMastercodeatalowerspeedmode(forexample:400kbpsFastMode)(refertoTable1),whichinitiatesasessionat3.4Mbps.
SpecificI/Obuffersmustalsobeusedtoletthebustoshortenthesignalsrisetimeandincreasethebusspeed.Theprotocolisalso
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somewhatadaptedinsuchawaythatnoarbitrationisperformedduringthehighspeedtransfer.RefertotheICspecificationformore
informationaboutthehighspeedmode.
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ICvsSPI:isthereawinner?
LetscompareICandSPIonseveralkeyprotocolaspects:
Bustopology/routing/resources:
ICneeds2linesandthatsit,whileSPIformallydefinesatleast4signalsandmore,ifyouaddslaves.SomeunofficialSPIvariantsonly
need3wires,thatisaSCLK,SSandabidirectionalMISO/MOSIline.Still,thisimplementationwouldrequireoneSSlineperslave.SPI
requiresadditionalwork,logicand/orpinsifamultimasterarchitecturehastobebuiltonSPI.TheonlyproblemICwhenbuildinga
systemisalimiteddeviceaddressspaceon7bits,overcomewiththe10bitsextension.
Fromthispointofview,ICisaclearwinneroverSPIinsparingpins,boardroutingandhoweasyitistobuildanICnetwork.
Throughput/Speed:
Ifdatamustbetransferredathighspeed,SPIisclearlytheprotocolofchoice,overIC.SPIisfullduplexICisnot.SPIdoesnotdefine
anyspeedlimitimplementationsoftengoover10Mbps.ICislimitedto1MbpsinFastMode+andto3.4MbpsinHighSpeedModethis
lastonerequiringspecificI/Obuffers,notalwayseasilyavailable.
Elegance:
ItisoftensaidthatICismuchmoreelegantthanSPI,andthatthislastoneisaveryrough(ifnotdumb)protocol.Actually,wetendto
thinkthetwoprotocolsareequallyelegantandcomparableonrobustness.
ICiselegantbecauseitoffersveryadvancedfeaturessuchasautomaticmultimasterconflictshandlingandbuiltinaddressing
managementonaverylightinfrastructure.Itcanbeverycomplex,howeverandsomewhatlacksperformance.
SPI,ontheotherhand,isveryeasytounderstandandtoimplementandoffersagreatdealofflexibilityforextensionsandvariations.
SimplicityiswheretheeleganceofSPIlies.SPIshouldbeconsideredasagoodplatformforbuildingcustomprotocolstacksfor
communicationbetweenICs.So,accordingtotheengineersneed,usingSPImayneedmoreworkbutoffersincreaseddatatransfer
performanceandalmosttotalfreedom.
BothSPIandI2Coffergoodsupportforcommunicationwithlowspeeddevices,butSPIisbettersuitedtoapplicationsinwhichdevices
transferdatastreams,whileICisbetteratmultimasterregisteraccessapplication.
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Usedproperly,thetwoprotocolsofferthesamelevelofrobustnessandhavebeenequallysuccessfulamongvendors.EEPROM
(ElectricallyErasableProgrammableReadOnlyMemory),ADC(AnalogtoDigitalConverter),DAC(DigitaltoAnalogConverter),RTC
(Realtimeclocks),microcontrollers,sensors,LCD(LiquidCrystalDisplay)controllersarelargelyavailablewithIC,SPIorthe2
interfaces.
Conclusions.
Intheworldofcommunicationprotocols,ICandSPIareoftenconsideredaslittlecommunicationprotocolscomparedto
Ethernet,USB,SATA,PCIExpressandothers,thatpresentthroughputinthex100megabitpersecondrangeifnotgigabitper
second.Though,onemustnotforgetwhateachprotocolismeantfor.Ethernet,USB,SATAaremeantforoutsidethebox
communicationsanddataexchangesbetweenwholesystems.Whenthereisaneedtoimplementacommunicationbetween
integratedcircuitsuchasamicrocontrollerandasetofrelativelyslowperipheral,thereisnopointatusinganyexcessivelycomplex
protocols.There,ICandSPIperfectlyfitthebillandhavebecomesopopularthatitisverylikelythatanyembeddedsystem
engineerwillusethemduringhis/hercareer.
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