Logic Design

10ES33

Assignment Questions
UNIT 1
1. Convert the given boolean function f(x, y, z) = [x + x Z (y + z)] into maxterm canonical
formula and hence highlight the importance of canonical formula.
2. Define canonical minterm and canonical maxterm.
3. The prime implicants and essential prime implicants. Determine the same of the function f(w, x,
y, z) = m(O, 1, 3,7,8,12) + d (5,10,13,14) using K-map and hence the minimal sum
expression.
4. Simplify using Karnaugh map. Write the Boolean equation and realize using NAND
gates D = f(v, w, x, y, z) = m(3,7,8,10,11,12,14,15,17,19,21,23,25,27,29,31) +
d(2,6,16,20).
5. Simplify P = f(a, b, c) = m (0,1, 4, 5, 7) using two variable Karnaugh map. Write the
equation and realize using logic gates.
6. What is the advantage, disadvantages of K map?
7. Write the steps for converting a verbal problem statement into truth table.
8. Show that ab+ ac + abc(ab+c) = 1
9. Stair case light is controlled by 2 switches, one is at the top of the stair and other at the bottom
of the stairs i) Make a truth table for this system ii) write the logic equations in the SOP form
iii) Realize the circuit using basic gates iv) realize the circuit using minimum number of
NAND gates.

UNIT 2
1. Using Quine-Mcluskey method and prime implicant reduction table, obtain the minimal sum
expression for the Boolean function f(w, x, y, z) = x y z + W x Z + W x + W x Y + x Y z + W Y z
2. Obtain the minimal product of the following Boolean functions using VEM
technique: f(w, x, y, z) = m (1, 5, 7, 10, 11) + d (2, 3, 6, 13) .
3. Simplify P = f(a, b, c) = L (0,1, 4, 5, 7) using two variable Karnaugh map. Write the Boolean

equation and realize using logic gates.

4. Simplify using Quine Mc Cluskey tabulation algorithm v = m(2, 3, 4, 5, 13, 15) + d (8, 9,
10, 11)
5. Minimize f(a,b,c,d) = (0,6,7,8,9,13) + dc(5,15) using quine Mc Cluskey method.
6. Design a combinational logic circuit, which converts BCD code into excess-3 code and draw
the circuit diagram.
Department of ECE, SJBIT

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Logic Design

10ES33

UNIT 3
1. Realize the following functions expressed in maxterm canonical form in two
possible ways using 3-8 line and decoder.
2. What are the problems associated with the basic encoder? Explain how these problems
can be overcome by priority encoder, considering 8 input lines.
3. Implement following multiple output function using 74LS138 and extend gates. F1 (A,
B, C) = m (1,4,5, 7)
f2 (A, B, C) = M (2, 3, 6, 7)
4. Design and implement a 4 bit look ahead carry adder.
5. Implement 16:1 multiplexer using 4:1 multiplexers.
6. Design a single decode BCD adder and explain the methodology in detail.
7. With the aid of block diagram clearly distinguish between a decoder and encoder.

UNIT 4
1. The 1-bit comparator had 3 outputs corresponding, to x > y, x = y and x < y. It is possible to code
these three outputs using two bits s1 s0 such as s1' s0 = 00, 10, 01 for x = y, x > y and x < y
respectively. This implies that only two-output lines occur from each 1-bit comparator. However
at the output of the last 1-bit comparator, an additional network must be designed to convert the
end results back to three outputs.
Design such a 1-bit comparator as well as the output converter network.
2. Realize F = (x, y, z) = (1, 2, 4, 5, 7) using 8 - to - 1 multiplexer (74L5151).
3. Implement the following Boolean function using 8 : 1 multiplexer f(ABCD)= L(0,1,3,5,7).
4. What is comparator? Design a two bit binary comparator.
5. Design a full adder using multiplexer for a full adder S=m (1,2,4,7) C= m (7,5,6,7)
6. Implement a full subtractor using 3-8 line decoders with the decoder having high outputs and
active low enable thermal.

UNIT 5
1. Design a 4-bit universal shift register using positive edge triggered D flip-flops to
operate as shown in the table.
2. What is the significance of edge triggering? Explain the working of edge triggered D-flipflop and T-flip-flop with their functional table.
Department of ECE, SJBIT

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Logic Design

10ES33

3. Compare sequential and combinational circuits.

4. Explain Johnson counter and ring counter.

5.

Design a 4 - bit BCD adder circuit using 7483 IC chip, with self correcting circuit.

6. Explain the functioning of positive edge triggered D- flip flop.

7. Explain the working of a pulse triggered JK master slave flip flop with a truth table.

UNIT 6
1. Explain the working principle of a mod-6 binary ripple counter, configured using
positive edge triggered T-FF. Also draw the timing diagram.
2. Explain the working of 4-bit asynchronous counter.
3. Compare synchronous and asynchronous counters.
4. Describe SR flip flop and JK flip flop.
5. Explain 4 bit universal shift register using negative edge triggered D- flipflops.
6. Give the circuit of a 4 bit JOHNSON counter using negative edge triggered D flipflops.
Draw the timing waveforms with respect to clock starting with an initial state of 0000.
What is the modulus of this counter?

UNIT 7
1. Explain the different types of shift register. SISO, SIPO, PIPO, PISO with relevant
circuit diagram.
2. Compare synchronous and ripple counters.
3. Draw the circuit of 3 bit asynchronous down counter using negative edge triggered JK
flip flops and draw the timing waveform.

UNIT 8
1) Design a cyclic mod-6 synchronous binary counter ? state diagram,
transition table JK flip-flop.
2) Construct a mealy state diagram that will detect a serial sequence of 10110.
Write the input pattern has been detected, cause an output Z to be asserted
high.
3) Design a cyclic modulo-8 synchronous counter using J-K flip-flop that will count the
number of occurrences of an input; that is, the number of times it is a 1. The input
variable X must be coincident with the clock to be counted. The counter is to count in
binary.

Department of ECE, SJBIT

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