Professional Documents
Culture Documents
Chapter-1
Embedded Systems
1.1 Introduction
An embedded system is a special-purpose system in which the
computer is completely encapsulated by the device it controls. Unlike a
general-purpose computer, such as a personal computer, an embedded
system performs pre-defined tasks, usually with very specific requirements.
Since the system is dedicated to a specific task, design engineers can
optimize it, reducing the size and cost of the product. Embedded systems are
often mass-produced, so the cost savings may be multiplied by millions of
items.
Physically, embedded systems range from portable devices such
as digital watches and MP3 players, to large stationary installations
like
systems
contain
signal
processing
cores
that
are
key
systems,
flight
control
missiles
cellular telephones and telephone switches
computer equipment such as routers and printers
engine controllers and antilock brake controllers for automobiles
home automation products, like thermostats, air conditioners,
sprinklers, and security monitoring systems
handheld calculators
household appliances, including microwave
VII.
VIII.
IX.
X.
XI.
ovens,
washing
and
are
stored
in
read-only
memory
or Flash
memory chips.
3. The embedded systems are special purpose computer systems
designed to perform only the specific purposes. For Example- a system
designed to display numbers cannot be used to operate motors.
4. Embedded systems range from no user interface at all dedicated
only to one task to complex graphical user interfaces that resemble
modern computer desktop operating systems.
CHAPTER-2
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Microcontroller Families
2.1 8051
These microcontrollers are old but still trendy and most of the
companies fabricate these microcontrollers. The Intel MCS-51 is a Harvard
architecture, CISC instruction
set,
single
series
2.2 PIC
Programmable Interface Controller is usually referred as PIC. They are
slightly older than 8051 microcontrollers but excel cause of their small low
pin count devices. They perform well and are affordable. The Microchip
technology fabricated the single chip microcontroller PIC with Harvard
architecture.
2.3 AVR
Advanced Version RISC.In 1996, Atmel fabricated this single chip
microcontroller with a modified Harvard Architecture. This chip is loaded with
C- compiler, Free IDE and many more features. This microcontroller is a bit
difficult for the starters to handle.
2.4 ARM
The ARM
instruction
set
CHAPTER-3
8051 Microcontroller
3.1 Introduction
Circumstances that we find ourselves in today in the field of microcontr
ollers had their
beginnings in the development of technology of integrated circuits. This
development
has
made
it
possible
to store hundreds
of thousands
and
the
first
computers
were
made
by
adding
enable
them
to
function
as
small
standalone
EPROM as
development
package
of
microcontrollerso f t e n i n c l u d e s a n a s s e m b l e r , a s i m u l a t o r , a
p ro g r a m m e r t o " b u rn " t h e
chip and a
demonstration
board.
3.3
AT89C51
In 40 pin AT89C51, there are four ports designated as P 1, P2, P3 and P0. All
these ports are 8-bit bi-directional ports, i.e., they can be used as both input
and output ports. Except P0 which needs external pull-ups, rest of the ports
have internal pull-ups. When 1s are written to these port pins, they are
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pulled high by the internal pull-ups and can be used as inputs. These ports
are also bit addressable and so their bits can also be accessed individually.
The main features of 8051 are:-
instructions),
bus and
with
2x16-bit address
mapped).
Fast interrupt with optional register bank switching.
Interrupts with selectable priority.
128 bytes of on-chip RAM
3.4
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We have 4 ports in 8051 micro controller. They are port0, port1, port2, port3
which can be accessed as i/o ports. The pins of the micro controller are
explained below.
Port 0:-The P0 port is characterized by two functions. If external memory is
used then the lower address byte (addresses A0-A7) is applied on it.
Otherwise, all bits of this port are configured as inputs/outputs.
The other function is expressed when it is configured as an output.
Unlike other ports consisting of pins with built-in pull-up resistor connected
by its end to 5 V power supply, pins of this port have this resistor left out.
This apparently small difference has its consequences. When the pin is
configured as an output, it acts as an open drain. By applying logic 0 to a
port bit, the appropriate pin will be connected to ground (0V). By applying
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logic 1, the external output will keep on floating. In order to apply logic 1
(5V) on this output pin, it is necessary to built in an external pull-up resistor.
11(TXD)
- Serial
asynchronous
communication
output
or
Serial
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XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator. Either a
quartz crystal or ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is
driven as .There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
3.4.2 Reset circuit
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3.5Architecture of AT89C51
3.5.1Block Diagram.
Address bus-For a device (memory or I/O) to be recognized by the CPU, it
must be assigned an address. The address assigned to a given device must
be unique. The CPU puts the address on the address bus, and the decoding
circuitry finds the device.
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Data bus-The CPU either gets data from the deviceor sends data to it.
Control bus-Provides read or write signals to the device to indicate if the
CPU is asking for information or sending it information
f a s t e s t RA M a v a i l a b l e , a n d i t i s a l s o t h e m o s t fl e x i b l e i n t e rm s
o f reading, writing, and modifying its contents. Internal RAM is volatile, so
when the 8051 is reset this memory is cleared. The 128 bytes of
internal ram is subdivided as shown on the memory map. The fi rst 8
bytes (00h - 07h) are "register bank 0". These alternative register
banks are located in internal RAM in addresses 08h through 1Fh.Bit memory
actually resides in internal RA M , f ro m a d d re s s e s 2 0 h t h r o u g h 2 F h .
T h e 8 0 b y t e s re m a i n i n g o f I n t e r n a l RA M , f r o m addresses 30h
through
7Fh, may
be
used
by user
variables
that need
to
be
accessed frequently o r a t h i g h - s p e e d . T h i s a re a i s a l s o u t i l i z e d b y
t h e m i c ro c o n t r o l l e r a s a s t o r a g e a re a f o r t h e operating stack
17H. Finally, RAM locations 18H to 1FH are set aside for the fourth bank of R0
R7.
Generally for normal operations, Register bank Bank0 is set by default. But
we can switch to other banks by using PSW Commands.
3.6.2 SFRs (Special Function Register) - These Registers are in extra 128
bytes of the memory. This part of memory is not user accessible and these
registers are used for special purposes. These registers range from 80h to
FFh. There are a total of only 21 SFRs in this range and all other addresses
from 80h to FFh are invalid and there use can cause errors and not valuable
results.
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Some of the SFRs are TCON, SBUF, ACC, B, SCON, TMOD SP, P0, PSW,
TL0, and TL1. These all the registers have some specific function that has to
be performed after they are programmed.
(i) Byte Addressable SFR with byte address
SP Stack printer 81H
DPTR Data pointer 2 bytes
DPL Low byte 82H
DPH High byte 83H
TMOD Timer mode control 89H
TH0 Timer 0 Higher order bytes 8CH
TL0 Timer 0 Low order bytes 8AH
TH1 Timer 1 High bytes = 80H
TL1 Timer 1 Low order byte = 86H
SBUF Serial data buffer = 99H
PCON Power control 87H.
3.6.3 Registers
The Accumulator
The Accumulator, as its name suggests.
The "R" registers
T h e " R " re g i s t e r s a re a s e t o f e i g h t re g i s t e r s t h a t a re
n a m e d R 0 , R 1 , e t c . u p t o a n d including R7. These registers are used
as auxiliary registers in many 8-bit(1-operations.
The "B" Register
The "B" register is very similar to the Accumulator in the sense that it
may hold an byte) value. The "B" register is only used by two 8051
instructions: MUL AB and DIV AB.
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number
of
commands
which
allow
the
8051
to
access
external memory.
Program Counter
T h e P ro g r a m C o u n t e r ( P C ) i s a 2 - b y t e a d d re s s w h i c h t e l l s
the
8051
w h e re
the
next
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Direct Addressing Mode- This mode allows you to specify the operand by
giving its actual memory address (typically specified in hexadecimal format)
or by giving its abbreviated name (e.g. P3).Used for SFR accesses
Example:
MOV A, P3; Transfer the contents of Port 3 to the accumulator
MOV A, 020H; Transfer the contents of RAM location 20H to the accumulator.
Indirect Addressing Mode-In the Indirect Addressing mode, a register is
used to hold the effective address of the operand. This register, which holds
the address, is called the pointer register and is said to point to the operand.
Only registers R0, R1 and DPTR can be used as pointer registers.R0
and R1 registers can hold an 8-bit address whereas DPTR can hold a 16-bit
address.DPTR is useful in accessing operands which are in the external
memory.
Examples:
MOV @R0, A; Store the content of accumulator into the memory location
pointed to by the contents of register R0. R0 could have an 8-bit address,
such as 60H.
MOVX A, @DPTR; Transfer the contents from the memory location pointed to
by DPTR into the accumulator. DPTR could have a 16-bit address, such as
1234H.
Immediate Addressing Mode-In the Immediate Constant Addressing
mode, the source operand is an 8- or 16-bit constant value. This constant is
specified in the instruction itself (rather than in a register or a memory
location).
The destination register should hold the same data size which is specified by
the source operand.
Examples:
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ADD A, #030H; Add 8-bit value of 30H to the accumulator register (which is
an 8-bit register).
MOV DPTR, #0FE00H; Move 16-bit data constant FE00H into the 16-bit Data
Pointer Register.
3.7.3 Instruction Types
The 8051 instructions are divided into four functional groups:
Arithmetic operations
Logical operations
Data transfer operations
Program branching operations
Arithmetic
Instructions-This
operations. Arithmetic operations affect the flags, such as Carry Flag (CY),
Overflow Flag (OV) etc., in the PSW register. The appropriate status bits in
the PSW are set when specific conditions are met, which allows the user
software to manage the different data formats.
Logical
Instructions-Logical
instructions
perform
standard
Boolean
Mask bit 1
ORL TCON, A;
TCON=TCON OR A
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bytes of data RAM are accessed only by indirect addressing and the SFRs
areaccessed only by direct addressing.
Program Branching Instructions- Program branching instructions are
used to control the flow of program execution.
The program status word (PSW) register, also referred to as the flag
execute.
The PSW3 and PSW4 are designed as RS0 and RS1, and are used to
PSW 7
PSW 6
PSW 5
PSW 4
PSW 3
PSW 2
PSW 1
PSW 0
Figure 3.9: PSW Register
F0
RS1
RS0
OV
---------
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LSB
C/T
M0
M1
GATE
C/T
Timer 1
M0
MI
Timer 0
Figure 3.11:TMOD Register
GATE=1 _Hardware control: is enabled only while INTx pin is 1and TRx
C/T = 0 _Timer (input from internal system clock) the crystal (1/12) is
101
210
31
LSB
TF1
TF0
TR1
TIMER 1
TR0
IE1
TIMER 0
IE0
IT1
IT0
TIMER1
TIMER0
Figure 3.12: TCON Register
Timer Mode 0
0000 ~ 1FFFH
Timer Mode 2
Mode 2: 8-bit auto reload Timer/counter mode (00 ~ FFH).
In auto reload, TH is loaded with the initial count and a copy of it is given to
TL.
This reloading leaves TH unchanged still holding a copy of original values.
This mode has many applications, including setting the baud rate in serial
communication.
3.8.2 Counters
Counter is used to count input pulses.
C/T=0: As Time, using 8051s crystal as the source of the frequency.
C/T=1: As counter, a pulse outside of the 8051 that increments the TH and
TL register.
When the C/T=1, the counter counts up as pulses are fed from Pins P3.4 (for
counter 0) or P3.5 (for counter 1).
3.9 INTERUPTS
An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.
devices.
Each device can get the attention of the microcontroller based on the
assigned priority.
The microcontroller can also ignore (mask) a device request for
service.
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CHAPTER-4
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Figure
4.1:
LED Interfacing
Assembly Code
org 00h
mov P1,#3fh
call delay
mov P0,#06h
call delay
mov P0,#5bh
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A 16x2 LCD means it can display 16 characters per line and there are 2
such lines. In this LCD each character is displayed in 5x7 pixel matrix.
This LCD has two registers.
1. Command/Instruction Register - stores the command instructions
given to the LCD. A command is an instruction given to LCD to do a
predefined task like initializing, clearing the screen, setting the cursor
position, controlling display etc.
2.Data Register - stores the data to be displayed on the LCD. The data is
the ASCII value of the character to be displayed on the LCD.
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Assembly Code
ORG 0H
MOV A,#38H
ACALL COMNWRT
ACALL DELAY
MOV A,#0EH
ACALL COMNWRT
ACALL DELAY
MOV A,#01
ACALL COMNWRT
ACALL DELAY
MOV A,#84H
ACALL COMNWRT
ACALL DELAY
MOV A,#c
ACALL DATAWRT
ACALL DELAY
MOV A,#d
ACALL DATAWRT
AGAIN: SJMP AGAIN
MOV A,#a
ACALL DATAWRT
ACALL DELAY
MOV A,#c
ACALL DATAWRT
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has been pressed and the process continues till key press is detected. If one
of the column bits has a zero, this means that a key press has occurred.
Assembly Code
org 00h
here:mov p1,#0ffh
clr p1.0
h1:jb p1.4,h2
mov p2,#3fh
h2:jb p1.5,h3
mov p2,#06h
h3:jb p1.6,h4
mov p2,#5bh
h4:jb p1.7,h5
mov p2,#4fh
h5:setb p1.0
clr p1.1
jb p1.4,h6
mov p2,#66h
h6:jb p1.5,h7
mov p2,#6dh
h7:jb p1.6,h8
mov p2,#7dh
h8:jb p1.7,h9
mov p2,#07h
h9:setb p1.1
clr p1.2
jb p1.4,h10
mov p2,#7fh
h10:jb p1.5,h11
mov p2,#67h
h11:jb p1.6,h12
mov p2,#77h
h12:jb p1.7,h13
mov p2,#7fh
h13:setb p1.2
clr p1.3
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be
interfaced
with
the
8051
using
l293d
connected
to
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Assembly Code
ORG 00H
AGAIN:MOV TMOD,#20H
MOV TH1,#-3
MOV SCON,#50H
SETB TR1
AGAIN: MOV SBUF,#A
HERE: JNB TI,HERE
CLR TI
SJMP AGAIN
CHAPTER-5
AVR MICROCONTROLLER
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5.1 Introduction
The acronym AVR has been reported to stand for Advanced Virtual
RISC, but it has also been rumored to stand for the initials of the chip's
designers. The AVR architecture was conceived by two students at
the Norwegian institute of technology, Alf-Egil Bogen and Vegard Wollan
Microcontroller
Harvard architecture 8-bit RISC single chip microcontroller . The AVR was one
of the first microcontroller families to use on-chip flash memory for program
storage,
as
opposed
to one-time
programmable
ROM, EPROM,
or EEPROM used by other microcontrollers at the time. Among the first of the
AVR line was the AT90S8515, which in a 40-pin DIP package has the same
pinout as an 8051 microcontroller, including the external multiplexed address
and data bus. The polarity of the RESET line was opposite (8051's having an
active-high RESET, while the AVR has an active-low RESET), but other than
that, the pin out was identical.
5.2 Features
High-performance, Low-power AVR 8-bit Microcontroller
RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
8K Bytes of In-System Self-programmable Flash
512 Bytes EEPROM
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- Limited Peripheral
Mega AVR with special features such as LCD controller , Advanced AVR
Field
Programmable
Specific
Language
Integrated
Circuit
is
5K to 40K
gates
-
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Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port C output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port C pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port D output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port D pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port E output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port E pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
RESET Reset input. A low level on this pin for longer than the minimum pulse
length will generate a reset, even if the clock is not running.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal
clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
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5.5 Architecture
The AVR core combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly connected to the
Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clockcycle. The resulting
architecture is more code efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers.
The ATmega8515 provides the following features: 8K bytes of InSystem Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes
SRAM, an External memory interface, 35 general purpose I/O lines, 32
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logical,
architecture
also
and
bit-functions.
provide
Some
powerful
implementations
multiplier
of
supporting
the
both
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arithmetic instruction. This information can be used for altering program flow
in order to perform conditional operations. The Status Register is updated
after all ALU operations, as specified in the Instruction Set Reference. This
will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The AVR Status Register SREG is defined as:
Bit 7 I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be
enabled. The individual interrupt enable control is then performed in
separate Control Registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by
hardware after an interrupt has occurred, and is set by the RETI instruction to
enable subsequent interrupts. The I bit can also be set and cleared by the
application with the SEI and CLI instructions
Bit 6 T: Bit Copy Storage
The Bit Copy instructions BLD (Bit Load) and BST (Bit Store) use the Tbit as source or destination for the operated bit. A bit from a register in the
Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic
operations. Half Carry is
useful in BCD arithmetic.
Bit 4 S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and
the Twos Complement Overflow Flag V.
Bit 3 V: Twos Complement Overflow Flag
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decremented by two when the return address is pushed onto the Stack with
subroutine call or interrupt. The stack Pointer is incremented by one when
data is popped from the Stack with the POP instruction, and it is incremented
by two when address is popped from the Stack with return from subroutine
RET or return from interrupt RETI.The AVR Stack Pointer is implemented as
two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent.
(PORTx).
-
Port
Where x is
X
the
Data
port A,
B,C,etc. .
Direction
Register
DDRx is an 8-bit register which stores configuration information for the pins
of Portx. Writing a 1 in the pin location in the DDRx makes the physical pin of
that port an output pin and writing a 0 makes that pin an input pin.
PINx
Port
Input
Pins
Register
PINx is an 8-bit register that stores the logic value, the current state, of the
physical pins on Portx. So to read the values on the pins of Portx, you read
the
values
that
are
in
its
PIN
register.
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PORTx
Port
Data
Register
PORTx is an 8-bit register which stores the logic values that currently being
outputted on the physical pins of Portx if the pins are configured as output
pins. So to write values to a port, you write the values to the PORT register of
that port.
5.8 Memories
5.8.1 Program memory
It is a continuous chunk of flash memory. The exact size varies from
controller to controller. Program memory is accessed every clock cycle and
an instruction is loaded in the Instruction Register. The Instruction Register
feeds the Register File, selecting which of the registers will be used for the
program execution. The program memory besides storing the instructions
also stores the Interrupt Vectors. The ATmega8515 contains 8K bytes On-chip
In-System Reprogrammable Flash memory for program storage. Since all AVR
instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For
software security, the Flash Program memory space is divided into two
sections, Boot Program section and Application Program section.
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1.Register Direct
Register Direct (single operand) .Instructions can operate on any of the
32 registers. The group of 32 registers are referred to as the Register File
The microcontroller:
Reads the data in the register
Operates on the data in the register
Stores the results back in the register
Register Direct (two operands):Instructions can operate on any of the 32
registers One of these registers is the source register (Rs) and one is the
destinationregister (Rd) Relative to the data.
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2. I/O Direct
Used to access I/O space (I/O registers and ports).I/O registers may
only be accessed with two instructions:
IN: for reading data from an input port: PINx
OUT: for sending data out the output port: PORTx
3.Data Direct
Instructions are two word (16-bit).One of the operands is the address of
the data (address of where the data is stored).The other operand is a
register.
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5. Data Indirect
In Data Direct, one of the operands is an explicitly specified address (to
store or retrieve data).In Data Indirect, the address is specified as the
contents of the X, Y, or Z .registerX is the combination of r26 & r27.Y is the
combination of r28 & r29.Z is the combination of r30 &r31.
X, Y, or Z are referred to as the pointer register.
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is
general
purpose,
single
channel,
8-bit
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Register TCNT0
The Timer/Counter Register gives direct access, both for read and write
operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks
(removes) the Compare Match on the following timer clock.
Output Compare Register OCR0
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(event
management),wave
generation,
and
signal
timing
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The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1)
give direct access, both for read and for write operations, to the
Timer/Counter unit 16-bit counter.
Output Compare Register 1 A OCR1AH and OCR1AL
5.11 USART
AVR has a dedicated hardware for serial communication this part is
called
the
USART
Universal
Synchronous
Asynchronous
Receiver
Transmitter. We supply the data we need to transmit and it will do the rest.
serial communication occurs at standard speeds of 9600,19200 bps etc and
this speeds are slow compared to the AVR CPUs speed.
Also the USART automatically senses the start of transmission of RX line
and then inputs the whole byte and when it has the byte it informs The PC
CPU to read that data from one of its registers. The USART of AVR is very
versatile and can be setup for various different mode as required by our
application.
5.11.1
USART Registers
The USART of the AVR is connected to the CPU by the following six
registers.UDR - USART Data Register : Actually this is not one but two register
but when we read it we will get the data stored in receive buffer and when
we write data to it goes into the transmitters buffer.
UCSRA - USART Control and status Register A : As the name suggests it
is used to configure the USART and it also stores some status about the
USART. There are two more of this kind the UCSRB and UCSRC.
UBRRH and UBRRL : This is the USART Baud rate register, it is 16BIT wide
so UBRRH is the High Byte and UBRRL is Low byte.
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RXC- this bit is set when the USART has completed receiving a byte from the
host (may be your PC) and the program should read it from UDR .
TXC -This bit is set (1) when the USART has completed transmitting a byte to
the host and your program can write new data to USART via UDR.
UCSRB: USART Control and Status Register B
RXCIE: Receive Complete Interrupt Enable - When this bit is written one
the associated interrupt is enabled.
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TXCIE: Transmit Complete Interrupt Enable - When this bit is written one
the the associated interrupt is enabled.
RXEN: Receiver Enable - When you write this bit to 1 the USART receiver is
enabled. The normal port functionality of RX pin will be overridden. So you
see that the associated I/O pin now switch to its secondary function,i.e. RX
for USART.
TXEN: Transmitter Enable
UCSZ2: USART Character Size
UCSRC: USART Control And Status Register C
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CHAPTER-6
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U1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
19
18
9
PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
39
38
37
36
35
34
33
32
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD
D2
LED-red
LED-BLUE
LED-BLUELED-red
LED-BLUE
D3
D4
D5
D6
D7
D8
LED-red
LED-BLUE
LED-red
21
22
23
24
25
26
27
28
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
XTAL1
XTAL2
RESET
D1
31
30
29
PE0/ICP/INT2
PE1/ALE
PE2/OC1B
ATMEGA8515
Assembly Code
.include "m8515def.inc"
.org 0x00
ldi r16,0xff
out sph,r16
ldi r16,0x00
out spl,r16
ldi r17,0xff
out ddra,r17
ldi r18,0xaa
next:out porta,r18
delay:ldi r19,0x1
l2:
ldi r20,0x1
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U1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
19
18
9
PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD
XTAL1
XTAL2
RESET
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
PE0/ICP/INT2
PE1/ALE
PE2/OC1B
39
38
37
36
35
34
33
32
D1
D2
D3
LED-RED
LED-RED
LED-RED
ATMEGA8515
D5
D6
D7
D8
LED-RED
LED-RED
LED-RED
LED-RED
LED-RED
21
22
23
24
25
26
27
28
31
30
29
D4
R1
R2
R3
6.98K
6.98K
6.98K
Assembly Code
.include "m32def.inc"
.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)
out spl,r16
ldi r17,0x00
out ddrc,r17
ldi r18,0xff
out ddra,r18
here:in r19,pinc
bst r19,0
brts next1
bst r19,1
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Assembly Code
.include "8515def.inc"
.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)
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LCD1
19
18
9
XTAL1
XTAL2
RESET
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
PE0/ICP/INT2
PE1/ALE
PE2/OC1B
21
22
23
24
25
26
27
28
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
VEE
39
38
37
36
35
34
33
32
7
8
9
10
11
12
13
14
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
4
5
6
10
11
12
13
14
15
16
17
PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
1
2
3
1
2
3
4
5
6
7
8
RS
RW
E
LM016L
U1
31
30
29
ATMEGA8515
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Baba Banda Singh Bahadur Engineering College, Fatehgarh Sahib
U1
1
2
3
4
5
6
7
8
PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
10
11
12
13
14
15
16
17
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/W R
PD7/RD
19
18
9
XTAL1
XTAL2
RESET
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
PE0/ICP/INT2
PE1/ALE
PE2/OC1B
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
31
30
29
ATMEGA8515
Assembly Code
.include "8515def.inc"
.org 0
LDI
R16, low(RAMEND)
OUT
SPL, R16
LDI
R16, high(RAMEND)
OUT
SPH, R16
ldi r17,0xff
out portd,r17
here:
ldi r18,0x3f
out portd,r18
rcall delay
rcall delay
ldi r18,0x06
out portd,r18
rcall delay
rcall delay
ldi r18,0x5b
out portd,r18
rcall delay
rcall delay
ldi r18,0x4f
out portd,r18
rcall delay
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ON
+
4
LCD1
D0
D1
D2
D3
D4
D5
D6
D7
LM016L
1
2
3
ATMEGA8515
7
8
9
10
11
12
13
14
31
30
29
RS
RW
E
PE0/ICP/INT2
PE1/ALE
PE2/OC1B
21
22
23
24
25
26
27
28
4
5
6
XTAL1
XTAL2
RESET
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
39
38
37
36
35
34
33
32
VSS
VDD
VEE
19
18
9
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD
PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
10
11
12
13
14
15
16
17
PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
U1
1
2
3
4
5
6
7
8
ret
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CHAPTER-7
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Softwares Used
7.1 Keil Vision
Keil MicroVision is a free software which solves many of the pain points for an
embedded program developer. This software is an integrated development
environment (IDE), which integrated a text editor to write programs, a
compiler and it will convert your source code to hex files too.
7.1.1 Steps to use Keil
Step 1: After opening Keil uV4, Go to Project tab and Create new uVision
project .Now Select new folder and give name to Project
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on options for target. Click output tab here & check create Hex file Right click
on group and click on Add files to source group.
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To create a new project, we click on New Project (new Projects can also be
created later by selecting Project\New from the Menu system). On the next
dialog Box, we select Atmel AVR assembler, enter the project name
and
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The minimized Session Log icon in the lower left portion of the Capture
session frame is the session log. The session log provides information about
everything you have donein the current Capture session.
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CHAPTER-8
PCB Designing
8.1 Introduction
A PCB is a printed circuit board, also known as a printed wiring
board. It is used in electronics to build electronic devices. A PCB serves
two purposes in the construction of an electronic device; it is a place to
mount the components and it provides the means of electrical connection
between the components.
The inventor of the printed circuit was the Austrian engineer Paul
Eisler (19071995) who, while working in England,made one circa 1936 as
part
of
a
radio
set.
8.2 Material
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8.3 Patterning
The vast majority of printed circuit boards are made by bonding a
layer of copper over the entire substrate, sometimes on both sides,
(creating
a
"blank
PCB")
then
removing unwanted
copper
after applying a temporary mask (e.g. by etching), leaving only the
desired copper traces. A few PCBs are made by adding traces to the
bare substrate (or asubstrate with a very thin layer of copper) usually
by a complex process of multiple electroplating steps. The
PCBmanufacturing method primarily depends on whether it is
for production volume or sample/prototype quantities. PCB milling uses
a two or three- axis mechanical milling system to mill away the copper
foil from the substrate. A PCB milling machine (referred to as a 'PCB
Prototyper') operates in a similar way to a plotter, receiving
commands from the host software that control the position of the
milling head in the x, y, and (if relevant) z axis. Data to drive
the Prototyper is extracted from files generated in PCB design software
and stored in HPGL or Gerber file format.
8.4 Etching
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8.5Laminating
Some PCBs have trace layers inside the PCB and are called multi-layer
PCBs. These are formed by bonding together separately etched thin
boards.
8.6Drilling
Holes through a PCB are typically drilled with tiny drill bits made of solid
tungsten carbide. The drilling is performed by automated drilling machines
with placement controlled by a drill tape or drill file. These computergenerated files are also called numerically controlled drill (NCD) files or
"Excellon files". The drill file describes the location and size of each drilled
hole. These holes are often filled with annular rings (hollow rivets) to
create vias. Vias allow the electricaland thermal connection of conductors
on opposite sides of the PCB.Most common laminate is epoxy filled
fiberglass.Drill bit wear is partly due to embedded glass, which is harder
than steel. High drill speed necessary for cost effectivedrilling of hundreds
of holes per board causes very high temperatures at the drill bit tip, and
high temperatures (400-700 degrees) soften steel and decompose
(oxidize)
laminate
filler. Copper
is
softer
than
epoxy
and interior conductors may suffer.When very small vias are required,
drilling with mechanical bits is costly because of high rates of wear and
breakage. In this case, the vias may be evaporated by lasers. Laser-drilled
vias typically have an inferior surface finish inside thehole. These holes
are called micro vias.It is also possible with controlled-depth drilling, laser
drilling, or by pre-drillingthe individual sheets of the PCB
before lamination, to produce holes that connect only some of the copper
layers, rather than passing through the entire board. These holes
are called blind vias when they connect an internal copper layer to an
outer layer, or buried vias when they connect two or more internal copper
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Baba Banda Singh Bahadur Engineering College, Fatehgarh Sahib
layers and no outer layers.The walls of the holes, for boards with 2 or
more layers, are made conductive then plated with copper to form platedthrough holes that electrically connect the conducting layers of the PCB.
For multilayer boards, those with 4 layers or more, drilling typically
produces a smear of the high temperature decomposition products of
bonding agent in the laminate system. Before the holes can be
plated through, this smear must be removed by a chemical de-smear
process, or by plasma-etch. Removing(etching back) the smear also
reveals the
interior
conductors
as
well.
8.8Solder resist
Areas that should not be soldered may be covered with a polymer
solder resist (solder mask) coating. The solder resist prevents solder from
bridging between conductors and creating short circuits. Solder resist also
provides some protection from the environment. Solder resist is typically
20-30 micrometres thick
for components likely to endure physical stress, while components that are
expected to go untouched will take up less space using surface-mount
techniques.After the board has been populated it may be tested in a
variety of ways:While the power is off, visual inspection, automated
optical inspection. JEDECguidelines for PCB component placement,
soldering, and inspection are commonly used to maintain quality control in
this stage of PCB manufacturing. While the power is off, analog signature
analysis, power-off testing.While the power is on, in-circuit test, where
physical measurements (i.e. voltage, frequency) can be done.While the
power is on, functional test, just checking if the PCB does what it had been
designed for.To facilitate these tests, PCBs may be designed with extra
pads to make temporary connections.Sometimes these pads must be
isolated with resistors. The in-circuit test may also exercise boundary
scan test features of some components. In-circuit test systems may also
be used to program nonvolatile memory components on the board.In
boundary scan testing, test circuits integrated into various ICs on the
board form temporary connections between the PCB traces to test that the
ICs are mounted correctly. Boundary scan testing requires that all the ICs
to be tested use a standard test configuration procedure, the most
common one being the Joint Test Action Group (JTAG) standard.When
boards fail the test, technicians may desolder and replace failed
components, a task known as rework.
Figure:8.1SMT Technology
Figure8.2: Breadboard
2)Stripboard
Stripboard has parallel strips of copper track on one side. The strips
are 0.1" (2.54mm) apart and there are holes every 0.1" (2.54mm). It can
be cut with a junior hacksaw, or simply snap it along the lines of holes by
putting it over the edge of a bench or table and pushing hard.
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Figure8.3: Stripboard
CHAPTER-9
ARM PROCESSOR
9.1 Introduction
The idea behind the Reduced Instruction Set computer (RISC )
originated in processor research programmers at Stanford and Brekeley
universities around 1980 through some of the central ideas can be traced
back to earlier machines.ARM1 prototype was designed in 1985.
ARM stands for Advanced RISC Machine.It was invented as a joint
venture between Apple, Acorn and VLSI in November 1990.ARM is the
industrys leading provider of 16/32bit RISC processor.The company licences
the high performance,low cost and high efficiency RISC processor.ARM
provides a comprehensive support required in building a whole system.
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processor's
instruction
set
defines
the
operations
that
the
programmer can use to change the state of the system incorporating the
processor. This state usually comprises the values of the data items in the
processor's visible registers and the system's memory. Each instruction can
be viewed as performing a defined transformation from the state before the
instruction is executed to the state after it has completedWhen writing userlevel programs, only the 15 general-purpose 32-bit registers (r0 to r!4), the
program counter (r15) and the current program status register (CPSR) need
be considered. The remaining registers are used only for system-level
programming and for handling exceptions (for example, interrupts).
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.1Processor modes
(10010)
Supervisor (p) (entered after reset and and is generally the mode that
System (p) (privileged mode using the same registers as user mode)
(11111)
Every Processor mode except user mode can change mode by writing
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User32 / System
FIQ32Supervisor32
Abort32 IRQ32Undefined32
r0
r0
r0
r0
r0
r0
r1
r1
r1
r1
r1
r1
r2
r2
r2
r2
r2
r2
r3
r3
r3
r3
r3
r3
r4
r4
r4
r4
r4
r4
r5
r5
r5
r5
r5
r5
r6
r6
r6
r6
r6
r6
r7
r7
r7
r7
r7
r7
r8
r8_fiq
r8
r8
r8
r8
r9
r9_fiq
r9
r9
r9
r9
r10
r10
r10
r10
r10_fiq r10
r11
r11
r11
r11
r11_fiq r11
r12
r12_fiq r12
r12
r12
r12
r13 (sp) r13_fiq r13_svc r13_abt r13_irq r13_undef
r14 (lr) r14_fiq r14_svc r14_abt r14_irq r14_undef
r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc)
Program Status Registers
cpsr
cpsr
cpsr
cpsr
cpsr
cpsr
sprsr_fiq
spsr_fiq spsr_svc spsr_abt sprsr_fiq
spsr_irq sprsr_fiq
spsr_u
ndef
Figure 9.4 :Register usage of different modes
9.5 Exceptions
Exceptions are usually used to handle unexpected events which arise
during the execution of a program, such as interrupts or memory faults. In
the ARM architecture the term is also used to cover software interrupts and
undefined instruction traps (which do not really qualify as 'unexpected') and
the system reset function which logically arises before rather than during the
execution of a program (although the processor may be reset again while
running). These events are all grouped under the 'exception' heading
because they all use the same basic mechanism within the processor. ARM
exceptions may be considered in three groups:
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interrupts,
undefined
instructions
(including
coprocessor
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Once the exception has been handled the user task is normally
resumed. This requires the handler code to restore the user state exactly as
it was when the exception first arose:
Any modified user registers must be restored from the handler's stack.
The CPSR must be restored from the appropriate SPSR.
The PC must be changed back to the relevant instruction address in the
user instruction stream.
Since multiple exceptions can arise at the same time it is necessary to
define a priority order to determine the order in which the exceptions are
handled. On ARM this is:
1. reset (highest priority)
2. data abort
3. FIQ
4. IRQ
5. prefetch abort
6. SWI, undefined instruction (including absent coprocessor). These are
mutually exclusive instruction encodings and therefore cannot occur
simultaneously.
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Reset starts the processor from a known state and renders all other
pending exceptions
irrelevant.
ARM
ii)
Instruction size
32-bit
16-bit
Core instruction
58
30
Conditional execution
most
No direct access
Register usage
9.6
.2Coprocessors
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source
operands
and
the
destination
register
are
specified
r0 := r1 and r2
r0 := r1 or r2
or
r0 = r1 |
r2
EOR r0, r1, r2
r0 := r1 xor r2 or
r0 = r1^r2
post
r1 =0b1111
BIC r0,r1,r2
r0=0b1010
r2 =0b0101
set cc flag on r1 - r2
Set cc flag on r1 + r2
32 bit value
TEQ r1, r2 test for equality of 32-
bit values
or r1^r2
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r0 := r1 + r2
r0 := r1 + r2 + C
r0 := r1 r2
r0 := r1 - r2 + C 1
or
r0 = r1-r2-!
(carry flag)
RSB r0, r1, r2
r0 := r2 r1
Pre
r0=0x00000000
r1=0x00000077
RSB r0,r1, #0 ;
Rd= 0x0 r1
Post r0 = -r1=0xffffff89
r0 := r2 r1 + C 1
or
r0= r2-r1-!
(carry flag)
9.7.4 Multiply Instructions
ARM multiply instructions produce the product of two 32-bit binary
numbers held in registers. The result of multiplying two 32-bit binary
numbers is a 64-bit product. Some forms of the instruction, available only on
certain versions of the processor, store the full result into two independently
specified registers; other forms store only the least significant 32 bits into a
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MLA
Multiply &accumulate
Rd=(Rm* Rs)+Rn
MUL
Multiply
Rd =Rm *Rs
LDR
Rd<-mem32[address]
STR
Rd->mem32[address]
reg.
LDRB
Rd<-mem8[address]
STRB
Rd->mem8[address]
LDRH
Rd<-mem16[address]
STRH
Rd->mem16[address]
LDRSB
Rd<-SignExtend
reg.
(mem8[address])
Architecture version
- Version 1 (obsolete)
Basic data processing
Byte, word and multi-word load/store
Software interrupt
26 bit address bus
No Multiply & Coprocessor Support
- Version 2 (obsolete)
Multiply
Coprocessor support
26 bit address bus
First ARM with on-chip Cache (Coprocessor CP15)
SWAP Instruction Introduced
- Version 3
32 bit address bus
Separate CPSR, SPSR
Add MRS, MSR. Modify exception handler
Add Abort Mode and Undef Mode
Was Backward Compatible with 26-bit
MUL & MLA
- Version 4
Half word transfer
Introduce THUMB processor state
Add Privileged mode for operating system
First fully formalized architecture
- Version 5
Improve ARM/THUMB inter-working
Add CLZ instruction for efficient integer divide
Add software breakpoint
Add more coprocessor support
More tight definition of arithmetic flags
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BIBILOGRAPHY
I.
II.
III.
IV.
V.
VI.
VII.
VIII.
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Baba Banda Singh Bahadur Engineering College, Fatehgarh Sahib
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Baba Banda Singh Bahadur Engineering College, Fatehgarh Sahib