EECT 6326

ANALOG IC DESIGN FINAL PROJECT

Design of a Fully-differential Operational

Amplifier

CONTENTS

SL. No

Topic

Page

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Cover Page
Contents
Project Narrative
Specification Comparison
Schematics

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DC hand calculation

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Approach
Cadence Simulated result for DC operation/annotation
Comparison of calculated and simulated values
Problem faced

AC Hand Calculation
Cadence Simulated result for AC operation/annotation
Comparison of calculated and simulated values
Problem faced
Conclusion

Individual Contribution
Reference
Appendix
HSPICE simulation Code for the Amplifier

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PROJECT NARRATIVE
Design a low power fully-differential operational amplifier with minimum power
consumption and meet all or most of the specifications given.
Summary of comparison between calculated and simulated specifications
Parameters
Supply Voltage
Power consumption
Low-frequency Gain A0
Unity-Gain frequency
Slew Rate SR
Phase Margin
CMRR
PSRR
DC Output
Differential output Swing
Input Offset Voltage
(Single-Ended) Load Cap.
CL

Specifications
1.8V
<750uW
>65dB
>150MHz
>12.5 V/us
>60
>80dB
>75dB at dc
>55dB at 1Mz
0.9V+/- 50mV
+/- 0.75V
<50mV
0.5pF

Calculated
1.8V
0.81mW
75.8dB
155MHz
32V/us
0.9V
0.5pF

Achieved
1.8V
0.79mW
73.59dB
220MHz
129.4 V/us
59.5
76.5dB
38.7dB
32.76dB
0.85V
0.65V to -0.90
21.1mV
0.5pF

Schematic of the Amplifier

Figure1. Schematic of the amplifier

Approach
This fully-differential operational amplifier design is inspired from the paper1
discussed in the class and the lab assignment2 on differential amplifier. We have also
taken help of the online material3, 4 discussing the differential amplifier design and

Fundamentals of Microelectronics (reference text book of our class). A current

mirror circuit is used to bias the transistors of the amplifiers and to make the current
constant in the branches.
Why double stage?
The minimum gain requirement in specification is 65dB which cannot be achieved by
a single stage amplifier. We simulated a single differential stage amplifier but the
maximum gain attained was around 40dB. The amplifier design used in the lab session
of the class has a gain of 60dB (very high gain for a single stage amplifier).
Topologies like cascode could provide a very good gain in one stage itself but it is
tough to meet other specification like output voltage swing, DC output. This is the
reason we went ahead with a design which has 2 stage, so that we could meet the gain
requirement very easily and refine the circuit for other specifications.
DC Hand Calculation
The nCox and pCox values used in the hand calculations are calculated by cadence
simulation which is mentioned in the appendix 1 and 2.
The current MOS M5 (calling it I5) which charging the load capacitor and the
compensation capacitor (C0+C3= 2pF+0.5pF = 2.5pF) 4 is calculated from the slew
rate specification which is >12.5V/us. I5 >12.5/2.5 = 5uA.
I5 calculated from the slew rate of 12.5V/us was giving us a very low current and we
found that Vov (for symmetric offset) for M5 is very high that is VDD/2 (0.9V) and
since we had liberty to choose high current as we were well within the power constraint
we took I5 as 80 uA. Moreover for I5 = 5uA, MOSs were in off or triod region. The
current through the second stage MOS M7, M14 and M12 are 80uA.
To avoid the effect of channel length modulation it is advised to take the length of the
MOS as 3 to 4 times of the technology length (which is 350 nm in our project) so we
fixed the length of all the transistors as 4*350nm = 1.4 um.
Width (W) of the second stage transistors are found by the current equation of the
MOSFET. For 80uA current, Vgs = 0.9V, Vtp = 0.6V and Vtn = 0.55V W for pMOS
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comes out as 42 and W for nMOS comes out as 10. So (W/L) for pMOS M5, M14
is (42/1.4) and for nMOS M7, M12 (W/L) comes out as (10/1.4)
From the single stage amplifier simulation we found that gain (gm1*(ro1||ro2) at one stage
will be around 40 dB. So, we tried to get the gm (deciding factor in gain calculation) of
first stage MOS in such a way that we achieve a gain of 40dB that is 100. Supposing
the ro of the transistor is in the range of 1M, tried to fix g m (2ID/VOV) means fix ID
for first stage (VOV is taken as 0.9V here). From this we got ID for first stage as 90uA.
But this current was very high considering the tail current will be 2 times of this current.
So we fixed the first stage current as 70uA. This gives W for pMOS in first as 36.2 and
for nMOS as 9.
Current through M6 is 2*current in first stage. We assumed the referenced current as
50 mA so, and the biasing circuit current we took 2 times of the reference current.
Power consumed is VDD*ITOTAL = 1.8 * (50+100+140+80+80)u = 0.81mW

Cadence Simulated result for DC operation/annotation

Fig2. DC parameters of the components of the amplifier

Fig3.
DC parameters of the components of the amplifier

Comparison of calculated and simulated values

W/L
calculated
W/L
simulated

M5,
M14

M7,M12 M0, M1 M9,

M8

I2, I3

I4& I6

I5,
I7, I0, I1, I8, I9
I12, I14

42/1.4

10/1.4

36.2/1.4 9/1.4

80 uA

50/1.4

12/1.4

37.5

83.01uA

100uA 50 & 70uA

140 uA
65/1.4 100uA 122uA 61uA

Problem faced
The biggest challenge in the design was to keep all the MOS in the saturation region.
To make it possible, we swept the value of W in nearby range using cadence to make
the all MOS region of operation as saturation and also to achieve a maximum gain.
Major issue was making first stage transistors to operate in saturation region. We did
hundreds of iteration to find the value for W for first stage nMOS to make all the
transistor work in saturation region.
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AC Hand Calculation
AV for this 2 stage amplifier is gm9*gm7*(ro9||ro0)*(r07||ro5).
We have already assumed the ro value is in the range of 1M. gm = 2ID/VOV, so gm9 =
160uA/V , gm7 = 155uA/V, So Av = 20log(77.5*80) = 75.8db
BW= gm/2CL = 155u/(2*0.5p) = 155MHz
Cadence Simulated result for AC operation/annotation

Fig4. Low frequency Gain, Phase margin and Unity Gain frequency of the amplifier

Fig5. CMRR and PSRR of Amplifier

CMRR is calculated by giving a mismatch in the input MOSFET to create a

nonsymmetric circuit. The given in the project specification we have taken 3%
mismatch in the active devices and 1% mismatch in the passive components to
calculate the differential gain as well as common mode gain.

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Diff. output Swing

Fig6. Differential output Swing

Fig7. Differential output Swing

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Comparison of calculated and simulated values

Parameters
Low-frequency Gain A0
Unity-Gain frequency
Slew Rate SR

Calculated Values
75.8dB
155MHz
32V/us

Simulated Values
73.59dB
220MHz
129.4 V/us

Problem faced
The amplifier system was not stable which was evident from the bode plot wherein at
180 of phase plot, the gain was positive. In order to compensate this gain and to bring
the amplifier system in to stability we included miller capacitor and miller resistance.
The system was not stable because it encountered two poles before the unity gain
frequency. Our motive is to have only one pole before the unity gain frequency. This
can be achieved through introduction of miller components. The miller capacitor is
calculated using the formula CM = (2gm2/gm1) * CL = (2*155/160) 0.5 = 1pF. The miller
resistor is calculated using the formula RM = 1/gm = 1/160u = 6.25 K.
The above values of miller capacitance and resistance were obtained by hand
calculation, then by fine tuning the CM and RM values (sweeping value in cadence), we
stabilized the system with have same gain and compromising the bandwidth to the
value 220MHz.
We are not meeting the PSRR value for this amplifier, we tried to get better value of
PSRR but any changes made force 1 or 2 MOSFET into triode region.
Conclusion
The specifications are met by adopting two stage differential amplifiers employing current
mirror load topology.
Miller compensation is made to bring the operation of the amplifier stable.
The gain attenuated as the frequency increased, we were able to attain the unity gain
frequency of 220MHz.
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The miller components helped us in getting phase margin of 60 deg.

All the transistors are sized such that the power consumption is well within the limit in the
specification.
The current through each limb in the system is decided by the current mirror load in the
second stage and the tail current load in the first stage.
The system has a gain margin of nearly 10db. Further improvements can be done to
increase the gain margin and meeting the PSRR values.

Individual Contribution
We started the project together in the beginning and later decided that each one should
come up with best topologies possible for the specification given so that we will be
analyzing more number of topologies. Finally we came up with almost similar design
as our references was same.
This technique really helped us in choosing the topology.
Prabhat covered the hand calculation for DC part
Shamanthan covered the hand calculation for AC part
We both worked on schematic together and poured ideas as and when faced any
problem.
References
1.
2.
3.
4.

http://www.utdallas.edu/~d.ma/6326/MOS_Opamp.pdf
http://www.utdallas.edu/~d.ma/6326/tutorial3.pdf
http://www.youtube.com/watch?v=Qbx0YI6UjoE
http://www.youtube.com/watch?v=XLK91PfbsCY

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Appendix
1. Calculation of nCox for 350 nm technology

nCox for the technology used is 185 uA/V2

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2. Calculation of pCox for 350 nm technology

pCox for the technology used is 60 uA/V2

These are the values used in the hand calculation in this project.

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HSPICE CODE
To Design Amplifier:*sub circuit
.subckt opamp vdd gnd vin+ vin- vop1 von1
m1 vop1 vin+ 1 gnd cmosn w=10u l=1.4u as='10u*1u' ad='10u*1u' ps='2*10u
+ 2*1u' pd='2*10u + 2*1u'
m2 von1 vin- 1 gnd cmosn w=10u l=1.4u as='10u*1u' ad='10u*1u' ps='2*10u +
2*1u' pd='2*10u + 2*1u'
m3 vop1 2 vdd vdd cmosp w=9u l=1.4u as='9u*1u' ad='9u*1u' ps='2*9u +
2*1u' pd='2*9u + 2*1u'
m4 von1 2 vdd vdd cmosp w=9u l=1.4u as='9u*1u' ad='9u*1u' ps='2*9u +
2*1u' pd='2*9u + 2*1u'
m5 3 3 gnd gnd cmosn w=10.15u l=1.4u as='10.15u*1u' ad='10.15u*1u'
ps='2*10.15u + 2*1u' pd='2*10.15u + 2*1u'
m6 2 3 gnd gnd cmosn w=20.15u l=1.4u as='20.15u*1u' ad='20.15u*1u'
ps='2*20.15u + 2*1u' pd='2*20.15u + 2*1u'
m7 2 2 vdd vdd cmosp w=60u l=1.4u as='60u*1u' ad='60u*1u' ps='2*60u +
2*1u' pd='2*60u + 2*1u'
m8 1 3 gnd gnd cmosn w=5.25u l=1.4u as='5.25u*1u' ad='5.25u*1u'
ps='2*5.25u + 2*1u' pd='2*5.25u + 2*1u'
*stage2:
*m11 vop1
ps='2*10u
*m12 von1
ps='2*10u

vop gnd
+ 2*1u'
von gnd
+ 2*1u'

gnd cmosn
pd='2*10u
gnd cmosn
pd='2*10u

*m13 vop1 2 vdd vdd

+ 2*1u' pd='2*35u +
*m14 von1 2 vdd vdd
+ 2*1u' pd='2*35u +

w=10u l=2.8u as='10u*1u' ad='10u*1u'

+ 2*1u'
w=10u l=2.8u as='10u*1u' ad='10u*1u'
+ 2*1u'

cmosp w=35u l=1.4u as='35u*1u' ad='35u*1u' ps='2*35u

2*1u'
cmosp w=35u l=1.4u as='35u*1u' ad='35u*1u' ps='2*35u
2*1u'

*m18 4 3 gnd gnd cmosn w=20.3u l=1.4u as='20.3u*1u' ad='20.3u*1u'

ps='2*20.3u + 2*1u' pd='2*20.3u + 2*1u'
Iss vdd 3 DC 30u
cm1 vop 5 0.425p
Rm1 5 vop1 1.3k
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cm2 von 6 0.425p

Rm2 6 von1 1.3k
*Rload vdd vo 1.8MEG
*R1 vo 2 0.1MEG cout1
vop1 gnd 0.5p cout2
von1 gnd 0.5p
.ends
*testbench
Testbench for simulating the amplifier:.option post probe nomod dcon=1
.include 'cmos.txt'
.include 'safesingle.sp'
xi vdd gnd vin+ vin- vop1 von1 opamp
vdd vdd gnd 1.8v
*vpulse vin+ 0 pwl (0 0 1n 1.8 500n 1.8 500.1n 0)
vcm1 101 gnd 1.2v vcm2
102 gnd 1.2v e+ vin+ 101
100 gnd 0.5 e- vin- 102
100 gnd -0.5
vs 100 gnd dc=0 ac=1
*.tf v(vo1) vs
.tf v(vop1,von1) vs
.probe v(vop)
*.dc vs -100m 100m 0.1m
.pz v(von1) vs
.probe v(vin+) v(vo)
*.trans 0.1n 1u
.op
.end

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