Amit Kumar Karna (4403)

Devender Budhwar (4411)

Dinesh Kumar (4412)

NIT Warangal
ACKNOWLEDGEMENT

Special thanks to,

Mr. P. Murlidhar
Faculty, Department of E.C.E., NIT Warangal

NIT Warangal
 AGENDA

‰ Introduction
‰ Approach
‰ VHDL implementation
‰ RTL Viewer
‰ Simulation results
‰ Conclusion
 INTRODUCTION

An MMU is a controller that allows

a common resource memory to be shared
by two or more processors depending on
various input control signals.
 INTRODUCTION…

Problem statement:
Three processors are required to share a
synchronous RAM of size 1024*16.The address
bus is 10 bits wide and the data bus is 16 bits
wide. There is a r/w’ signal which allows the
processors to read data from the memory or write
data into the memory. The controller is supposed to
control access to the common memory depending on
the request signals received by the three processors
depending on certain algorithms.
 Requirements

‰ Synchronous RAM

‰ Address and Data Bus Multiplexer

 AGENDA

‰ Introduction
‰ Approach
‰ VHDL implementation
‰ RTL Viewer
‰ Simulation results
‰ Conclusion
PRIORITY INTERRUPT ALGORITHM

Each processor is assigned a priority

and depending on the priority a CPU is given
access. When a lower priority processor is
active and the controller receives the request
signal from a higher priority processor, the
latter is given access until its job is finished
after which the lower priority processor is given
access.
Nested interrupts should be allowed.
PRIORITY INTERRUPT
state diagram
 AGENDA

‰ Introduction
‰ Approach
‰ VHDL implementation
‰ RTL Viewer
‰ Simulation results
‰ Conclusion
 VHDL

‰ VHSIC Hardware Description Language.

‰ Common language for designers.
‰ High level language.
‰ Simulation synthesis and analysis tools
are available.
‰ Softwares: Quartus-II/Xlinix
 DESIGN Unit Names
¾ Entity
ƒ Meaningful name describing the purpose of the circuit.

¾ Architecture
ƒ According to the modeling style used (i.e., Behavioral, Procedural,
Dataflow, or Structural) or to some specific architecture property.

¾ Configuration
ƒ Name of the corresponding entity with suffix "Cfg“.
¾ Package
ƒ Name of the design (i.e., top-level entity) with suffix "Pkg“.
¾ Testbench (entity, architecture, package)
ƒ Name of corresponding entity with suffix "Tb“.

¾ Library (package)
ƒ Library name with suffix "Lib".
 FPGA

‰ Benefits of using FPGA

¾ Programmed by user at their site using
programming hardware.
¾ Can implement tens of thousands of gates on
logic on a single IC.
¾ Can be programmed many times.
¾ Short development time.
¾ Low cost.
¾ FPGA kit in lab: EP1C6Q240C8
Hierarchy ‘n’ fpga occupancy

COMPONENTS:-
• Synchronous RAM
• Address and Data Bus Multiplexer
Project navigator
 AGENDA

‰ Introduction
‰ Approach
‰ VHDL implementation
‰ RTL Viewer
‰ Simulation results
‰ Conclusion
MMU- Entity
MAIN – RTL VIEW
 MAIN – TECHNOLOGY VIEW
m u l ti p l e x:m u l t

a d d A [0 ] addA[0]
a d d A [1 ] addA[1]
a d d A [2 ] addA[2]
a d d A [3 ] addA[3]
a d d A [4 ] addA[4]
a d d A [5 ] addA[5]
a d d A [6 ] addA[6]
a d d A [7 ] addA[7]
a d d A [8 ] addA[8]
a d d A [9 ] addA[9]
a d d B [0 ] addB[0]
a d d B [1 ] addB[1]
a d d B [2 ] addB[2]
a d d B [3 ] addB[3]
a d d B [4 ] addB[4]
a d d B [5 ] addB[5]
a d d B [6 ] addB[6]
m e m o r y:m e m
a d d B [7 ] addB[7]
a d d B [8 ] addB[8] c lk
a d d B [9 ] addB[9] data_out_mux[0]~ 688 data_out_mux[0]~ 688
a d d C [0 ] addC [0] data_out_mux[1]~ 689 data_out_mux[1]~ 689
a d d C [1 ] addC [1] data_out_mux[2]~ 690 data_out_mux[2]~ 690
a d d C [2 ] addC [2] data_out_mux[3]~ 691 data_out_mux[3]~ 691
a d d C [3 ] addC [3] data_out_mux[4]~ 692 data_out_mux[4]~ 692
a d d C [4 ] addC [4] data_out_mux[5]~ 693 data_out_mux[5]~ 693 q _b[0] d a ta _ r d _ o u t[0 ]
a d d C [5 ] addC [5] data_out_mux[6]~ 694 data_out_mux[6]~ 694 q _b[1] d a ta _ r d _ o u t[1 ]
a d d C [6 ] addC [6] data_out_mux[7]~ 695 data_out_mux[7]~ 695 q _b[2] d a ta _ r d _ o u t[2 ]
a d d C [7 ] addC [7] data_out_mux[8]~ 696 data_out_mux[8]~ 696 q _b[3] d a ta _ r d _ o u t[3 ]
a d d C [8 ] addC [8] data_out_mux[9]~ 697 data_out_mux[9]~ 697 q _b[4] d a ta _ r d _ o u t[4 ]
a d d C [9 ] addC [9] data_out_m ux[10]~ 698 data_out_mux[10]~ 698 q _b[5] d a ta _ r d _ o u t[5 ]
d a ta A [0 ] dataA[0] data_out_m ux[11]~ 699 data_out_mux[11]~ 699 q _b[6] d a ta _ r d _ o u t[6 ]
d a ta A [1 ] dataA[1] data_out_m ux[12]~ 700 data_out_mux[12]~ 700 q _b[7] d a ta _ r d _ o u t[7 ]
d a ta A [2 ] dataA[2] data_out_m ux[13]~ 701 data_out_mux[13]~ 701 q _b[8] d a ta _ r d _ o u t[8 ]
d a ta A [3 ] dataA[3] data_out_m ux[14]~ 702 data_out_mux[14]~ 702 q _b[9] d a ta _ r d _ o u t[9 ]
d a ta A [4 ] dataA[4] data_out_m ux[15]~ 703 data_out_mux[15]~ 703 q _b[10] d a ta _ r d _ o u t[1 0 ]
d a ta A [5 ] dataA[5] M ux0~ 131 M ux0~ 131 q _b[11] d a ta _ r d _ o u t[1 1 ]
d a ta A [6 ] dataA[6] M ux1~ 132 M ux1~ 132 q _b[12] d a ta _ r d _ o u t[1 2 ]
d a ta A [7 ] dataA[7] M ux2~ 132 M ux2~ 132 q _b[13] d a ta _ r d _ o u t[1 3 ]
d a ta A [8 ] dataA[8] M ux3~ 132 M ux3~ 132 q _b[14] d a ta _ r d _ o u t[1 4 ]
d a ta A [9 ] dataA[9] M ux4~ 132 M ux4~ 132 q _b[15] d a ta _ r d _ o u t[1 5 ]
d a ta A [1 0 ] dataA[10] M ux5~ 132 M ux5~ 132
d a ta A [1 1 ] dataA[11] M ux6~ 132 M ux6~ 132
d a ta A [1 2 ] dataA[12] M ux7~ 132 M ux7~ 132
d a ta A [1 3 ] dataA[13] M ux8~ 132 M ux8~ 132
d a ta A [1 4 ] dataA[14] M ux9~ 132 M ux9~ 132
d a ta A [1 5 ] dataA[15] M ux10~ 139 rw
d a ta B [0 ] dataB[0] M ux11~ 139
d a ta B [1 ] dataB[1] M ux12~ 139
d a ta B [2 ] dataB[2] M ux13~ 139 d a ta _ w r _ o u t[1 5 ]
d a ta B [3 ] dataB[3] M ux14~ 139
D AT AIN
d a ta B [4 ] dataB[4] M ux15~ 139 PAD O U T d a ta _ w r _ o u t[1 5 ]
!OE
d a ta B [5 ] dataB[5] M ux16~ 139
d a ta B [6 ] dataB[6] M ux17~ 139 O U T PU T
d a ta B [7 ] dataB[7] M ux18~ 139
d a ta _ w r _ o u t[1 4 ]
d a ta B [8 ] dataB[8] M ux19~ 139
d a ta B [9 ] dataB[9] M ux20~ 139 D AT AIN
PAD O U T d a ta _ w r _ o u t[1 4 ]
d a ta B [1 0 ] dataB[10] M ux21~ 139 !OE
d a ta B [1 1 ] dataB[11] M ux22~ 139
O U T PU T
d a ta B [1 2 ] dataB[12] M ux23~ 139
d a ta B [1 3 ] dataB[13] M ux24~ 139 d a ta _ w r _ o u t[1 3 ]
d a ta B [1 4 ] dataB[14] M ux25~ 139
D AT AIN
d a ta B [1 5 ] dataB[15] M ux26~ 180 PAD O U T d a ta _ w r _ o u t[1 3 ]
!OE
d a ta C [0 ] dataC [0]
d a ta C [1 ] dataC [1] O U T PU T
d a ta C [2 ] dataC [2]
d a ta _ w r _ o u t[1 2 ]
d a ta C [3 ] dataC [3]
d a ta C [4 ] dataC [4] D AT AIN
PAD O U T d a ta _ w r _ o u t[1 2 ]
d a ta C [5 ] dataC [5] !OE
d a ta C [6 ] dataC [6]
O U T PU T
d a ta C [7 ] dataC [7]
d a ta C [8 ] dataC [8] d a ta _ w r _ o u t[1 1 ]
d a ta C [9 ] dataC [9]
D AT AIN
d a ta C [1 0 ] dataC [10] PAD O U T d a ta _ w r _ o u t[1 1 ]
!OE
s ta r t dataC [11]
c u r r _ s ta te .s 2
rw B dataC [12] O U T PU T
! AC LR
rw C dataC [13]
com b~313 C LK d a ta _ w r _ o u t[1 0 ]
c u r r _ s ta te .s 3 C O M BO U T p e n a b le A dataC [14]
D A T AA D AT A B
re s e t ! A C LR R EG O U T D AT AA dataC [15] D AT AIN
D A T AC C O M BO U T D AT A D PAD O U T d a ta _ w r _ o u t[1 0 ]
c lk C LK c u r r _ s ta te .s 4 D AT AB C O M BO U T penableA !OE
R EG O U T D A T AD S YN C H _D AT A com b~319
re q A D AT AA ! AC LR D AT AD penableB
LC E LL ( AAF 0) LC E LL ( C F C 0) com b~320 D AT AA O U T PU T
re q B D AT AC C LK LC ELL ( 3322) penableC
D A T AA D AT AB
LC ELL ( 5050) D AT A A C OM BOU T d a ta _ w r _ o u t[9 ]
D A T AB R EGO U T D AT AC
C O M BO U T D AT A B
c u r r _ s ta te .s 1 D A T AC D AT AD D AT AIN
rw A D AT A C PAD O U T d a ta _ w r _ o u t[9 ]
! A C LR D A T AD LC ELL (32F F ) !OE
D AT A D
C LK LC E LL ( 0100)
LC ELL (0100) com b~316 O U T PU T
D AT AA
R EG O U T D AT AA
D AT AB p e n a b le B d a ta _ w r _ o u t[8 ]
D AT AB
D AT AC C OM BOU T D AT AA
D AT AC D AT AIN
re q C D AT AD D AT AB C O M BO U T PAD O U T d a ta _ w r _ o u t[8 ]
D AT AD !OE
LC ELL ( F F F E) D AT AD
LC ELL ( 5455)
LC ELL ( 5544) O U T PU T
com b~318
d a ta _ w r _ o u t[7 ]
D AT AA
com b~317 p e n a b le C
D AT AB D AT AIN
D A T AA C OM BOU T D AT AB PAD O U T d a ta _ w r _ o u t[7 ]
D AT AC !OE
D A T AC C O M BO U T D AT AC C O M BO U T
D AT AD
D A T AD D AT AD O U T PU T
LC ELL ( 1044)
LC ELL ( F F A5) LC E LL ( 0F 0C )
d a ta _ w r _ o u t[6 ]
com b~315 D AT AIN
rw PAD O U T d a ta _ w r _ o u t[6 ]
D AT AA !OE
D AT AA
D AT AB
C OM BOU T D AT AC C O M BO U T O U T PU T
D AT AC
D AT AD
D AT AD d a ta _ w r _ o u t[5 ]
LC E LL ( F A0A )
LC ELL (F E00)
D AT AIN
PAD O U T d a ta _ w r _ o u t[5 ]
!OE

O U T PU T

d a ta _ w r _ o u t[4 ]
d a ta C [1 1 ]
d a ta C [1 2 ] D AT AIN
PAD O U T d a ta _ w r _ o u t[4 ]
d a ta C [1 3 ] !OE
d a ta C [1 4 ]
O U T PU T
d a ta C [1 5 ]
d a ta _ w r _ o u t[3 ]

D AT AIN
PAD O U T d a ta _ w r _ o u t[3 ]
!OE

O U T PU T

d a ta _ w r _ o u t[2 ]

D AT AIN
PAD O U T d a ta _ w r _ o u t[2 ]
!OE

O U T PU T

d a ta _ w r _ o u t[1 ]

D AT AIN
PAD O U T d a ta _ w r _ o u t[1 ]
!OE

O U T PU T

d a ta _ w r _ o u t[0 ]

D AT AIN
PAD O U T d a ta _ w r _ o u t[0 ]
!OE

O U T PU T
p r e s e n t~ 1 4
p r e s e n t[2 ]
D AT AB
C OM BOU T D AT AIN
D AT AD PAD O U T p r e s e n t[2 ]
!OE
LC ELL ( 0033)
O U T PU T

p r e s e n t[1 ]

D AT AIN
PAD O U T p r e s e n t[1 ]
!OE

O U T PU T

p r e s e n t[0 ]

D AT AIN
PAD O U T p r e s e n t[0 ]
!OE

O U T PU T
MAIN - FLOW RESULT
Memory-entity
MEMORY – RTL VIEW
MEMORY – Technology view
Memory flow summary
Mux entity
Mux flow diagram
Mux rtl
MuX – tech view
 AGENDA

‰ Introduction
‰ Approach
‰ VHDL implementation
‰ RTL Viewer
‰ Simulation results
‰ Conclusion
SIMULATION STATE DIAGRAM
CONDITIONS GENERATED
BY SIMULATION
Memory simulation
Mux simulation
MMU-SIMULATION
 AGENDA

‰ Introduction
‰ Approach
‰ VHDL implementation
‰ RTL Viewer
‰ Simulation results
‰ Conclusion
 CONCLUSION

‰ Memory can be simultaneously serviced to multi

processes.

‰ Being an Interrupt service procedure, time of processor

is managed efficiently.

‰ FPGA/VHDL combination is a very powerful design

tool.
• Versatile, Adaptable, Efficient, Economic

‰ The given algorithm can be used to implement process

scheduling.
 REFERENCES

‰ A VHDL Primer, 3rd edition : J. Bhasker

‰ Computer Organization and Architecture:

William Stallings
 Thanks
"It's not that i am genius,
but i stay a little longer
with problems" - Einstein.