Professional Documents
Culture Documents
APPLICATION
NOTE
Pentium® Processor
Flexible Motherboard
Design Guidelines
June 1997
INTEL CONFIDENTIAL
(until publication date)
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."
Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Pentium® processor may contain design defects or errors known as errata. Current characterized errata are available on
request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-7641
or call 1-800-879-4683
or visit Intel’s website at http:\\www.intel.com
Third-party brands and names are the property of their respective owners.
INTEL CONFIDENTIAL
(until publication date)
E AP-579
CONTENTS
PAGE PAGE
3.9. Thermal and Physical Space
1.0. INTRODUCTION ............................................... 5 Considerations .............................................27
1.1. Benefits of a Flexible Motherboard................. 7 3.9.1. VOLTAGE REGULATOR THERMAL
DESIGN CONSIDERATIONS ..............27
2.0. PROCESSOR DESIGN CONSIDERATIONS .. 7
3.9.2. DESKTOP SYSTEM THERMAL
2.1. Overview of the Pentium® Processor DESIGN CONSIDERATIONS ..............27
Family............................................................. 8
3.10. BIOS/Software Considerations..................28
2.2. Pinout Considerations.................................... 9
3.11. Dual Processor Design Considerations.....29
2.3. Processor Identification................................ 10
A1.0. VOLTAGE REGULATOR MODULE............33
3.0. FLEXIBLE MOTHERBOARD
IMPLEMENTATION ........................................ 11 A1.1. Header 7 ....................................................34
3.1. Voltage Supply Implementation Overview... 11 A1.2. Shorting Block or Pass-Through Module...35
3.2. The Distinct Power Planes........................... 11 A1.3. VRM for Processors Running at VRE .......35
3.3. Split Plane Processor/Unified Plane A1.4. VRM for Pentium® Processor with MMX™
Processor Design Configurations................ 13 Technology...................................................35
3.4. Power Plane Connections and Voltage A1.5. VRM Header Placement............................35
Regulator Shutdown..................................... 15
A2.0. VOLTAGE REGULATOR MODULE
3.5. Voltage Supply Implementation Options...... 18 HEADER PIN DIAGRAM ................................32
3.5.1. 2.8V/3.3V AUTO-CONFIGURABLE
REGULATOR ....................................... 16 A3.0. VOLTAGE REGULATOR MODULE QUICK
3.5.2. 2.8V REGULATOR AS A BUILD PIN REFERENCE............................................37
OPTION ................................................ 19
B1.0. SOCKET 7 PIN DIAGRAM...........................39
3.5.3. SAFEGUARDING PENTIUM®
PROCESSOR WITH MMX™ B2.0. SOCKET 7 QUICK PIN REFERENCE.........41
TECHNOLOGY ON THE FLEXIBLE
MOTHERBOARD ................................. 20 C1.0. LINEAR AND SWITCHING REGULATOR
3.6. Split Power Plane Layout............................. 21 SOLUTIONS ....................................................41
3.7. Decoupling ................................................... 22
D1.0. REGULATOR VENDOR SOLUTIONS
3.7.1. BULK DECOUPLING............................ 23 CONTACT LIST ..............................................47
3.7.2. HIGH FREQUENCY DECOUPLING.... 23
3.7.3. DECOUPLING E1.0. LIST OF RELATED TOOLS &
RECOMMENDATIONS ........................ 23 COLLATERAL ................................................51
3.7.4. PLACEMENT OF DECOUPLING E1.1. Public Documentation................................53
CAPACITORS ...................................... 24 E1.2. Collateral Available Under Non-Disclosure
3.8. Signal Routing Guidelines............................ 26 Agreement....................................................54
E2.0. REFERENCES..............................................54
INTEL CONFIDENTIAL
(until publication date)
AP-579
FIGURES TABLES
E
Figure 1. Pentium® Processor Flexible Table 1. Pentium® Processors and Pentium
Motherboard..........................................5 OverDrive® Processors and Their Key
Figure 2. EAX Bit Assignments for CPUID.........10 Differences .............................................9
Figure 3. The Typical Power Planes in a Desktop Table 2. BF1-0 Core/Bus Ratio Selection Pins..10
Pentium® Processor Flexible Table 3. CPUID Information................................11
Motherboard........................................12 Table 4. The Three Types of Pentium®
Figure 4. Pentium® Processor Family Power Processor Power Planes......................14
Plane Characteristics..........................14 Table 5. Decoupling Recommendations for
Figure 5. Unified Plane Current Flow vs. Split Processor Core and I/O Voltage
Plane Current Flow .............................15 Islands ..................................................23
Figure 6. Use of MOSFETs to Table 6. Typical Processor Voltage Supply
Connect/Disconnect Power Planes ....16 Configuration with VRM........................34
Figure 7. Regulator Shutdown Phenomenon.....17 2.8V/3.3V/VRE Linear Regulator Solutions.........43
Figure 8. Auto-configurable Voltage Regulator 2.8V/3.3V/VRE Switching Regulator Solutions...45
Solution ...............................................18 On-board Regulators...........................................47
Figure 9. 2.8V Voltage Regulator Designed as a Voltage Regulator Modules.................................48
Build Option.........................................20
Socket 7 48
Figure 10. External Safeguard Circuit to Prevent
Processor from Booting ......................21 Header 749
Figure 11. External Safeguard by Reducing the Decoupling Capacitors ........................................49
Output Voltage ....................................21 Shorting Blocks....................................................50
Figure 12. Processor Power Island Layout........22 Resistors..............................................................50
Figure 13. Typical Capacitor Characteristics .....25 3.3V Clock Driver Suppliers ................................51
Figure 14. Example of Processor Decoupling Product Information .............................................54
Capacitor Placement...........................26 System Design Documentation...........................54
Figure 15. Thermal and Physical Space System Design Tools...........................................54
Requirements for Pentium OverDrive®
Processor with MMX™ Technology....28
Figure 16. Layout of a DP Flexible
Motherboard........................................30
Figure 17. Voltage Regulator Modules...............33
VRM Pinout Top Side View.................................36
Socket 7 Pinout—Top Side View ........................39
Socket 7 Pinout—Pin Side View .........................40
INTEL CONFIDENTIAL
(until publication date)
E
1.0. INTRODUCTION
AP-579
166MHz 200MHz
166MHz
150MHz
133MHz
120MHz
100MHz
90MHz
318701
INTEL CONFIDENTIAL
(until publication date)
AP-579
INTEL CONFIDENTIAL
(until publication date)
E required when a Pentium OverDrive 1.1. Benefits of a Flexible
AP-579
INTEL CONFIDENTIAL
(until publication date)
AP-579
The Pentium processor 75 / 90 / 100 / 120 / 133 / 150 / For the processors that are supported on the
166 / 200 is a 3.3V processor that operates at 75, 90, flexible motherboard, most of the signals are
100, 120, 133, 150, 166 and 200 MHz core speeds (50, compatible to each other. The differences are noted
60, and 66 MHz external bus speeds). This is a unified below:
plane processor that uses 3.3V [Standard (3.135V –
• VCC2 , VCC3 : On the Pentium processor with
3.6V) or VRE (3.4V – 3.6V) voltage] for all VCC pins.
MMX technology, the internal bus logic is
The Pentium processor with MMX technology isolated from the core logic so that the core can
166/200 is the newest addition to the Pentium run at a lower voltage (2.8V) in order to obtain
processor family. Several architectural faster core frequencies and reduce overall power
enhancements have been made: the internal data consumption. The bus logic remains at 3.3V to
and code cache sizes have each been doubled from 8 remain compatible with existing chipsets and
Kbytes to 16 Kbytes, the branch prediction has been cache SRAM. The voltage for the core logic is
improved, and support for Intel MMX technology supplied through the VCC2 pins and the voltage
has been added. MMX technology is an extension to for the bus logic is supplied through the VCC3
the Intel Architecture (IA) instruction set which pins. The motherboard design therefore splits
adds 57 new opcodes and a new MMX register set. the processor power plane into a separate 2.8V
The Pentium processor with MMX technology
core voltage island and a 3.3V I/O voltage
operates at core frequencies of 166 and 200 MHz
island.
(60 and 66 MHz external bus speeds). The Pentium
processor with MMX technology uses 2.8V for its • VCC2DET#: This is a new signal defined on the
internal core while its I/O operates at 3.3V (to Pentium processor with MMX technology to
provide full compatibility with existing chipset and indicate to the system that the processor
SRAM). It is pin, package, and functionally installed in the processor socket uses an isolated
compatible with the Pentium processor 75 / 90 / 100 2.8V core supply on the VCC2 pins. This pin is
/ 120 / 133 / 150 / 166 / 200 and is operating system internally connected to ground on the Pentium
transparent. The Pentium processor with MMX
processor with MMX technology. On Pentium
technology’s CLK and PICCLK buffers are not 5V
processors 75 / 90 / 100 / 120 / 133 / 150 / 166 /
tolerant and should only use 3.3V clock inputs.
200, Pentium OverDrive processors, and future
Pentium OverDrive processors with MMX
8
INTEL CONFIDENTIAL
(until publication date)
E technology, this pin is defined as INC (Internal
AP-579
Table 1. Pentium® Processors and Pentium OverDrive® Processors and Their Key Differences
Pentium Processor Pentium Future Pentium
with MMX OverDrive® OverDrive Processor
Pentium® Processor Technology Processor with MMX Technology
(7)
Core Frequency 75, 90, 100, 120, 133, 166, 200 125, 150, 166 125, 150, 166, 180, 200
150, 166, 200
Bus Frequency 50, 60, 66 60, 66 50, 60, 66 50, 60, 66
(4) (4)
Frequency Ratio 1/2, 2/3, 2/5,1/3 2/5,1/3 2/5 2/5, 1/3
(7)
Clock Level 3.3V or 5V 3.3V 3.3V or 5V 3.3V or 5V
Core Supply 3.135V – 3.60V (STD); 2.7V – 2.9V 3.135 – 3.6V
3.40V – 3.60V (VRE)
I/O Supply 3.135V – 3.60V (STD); 3.135V – 3.60V 3.135 – 3.6V
3.40V – 3.60V (VRE)
(1, 5) (6)
ICC2 Connected to ICC3 5700mA (200 MHz) Connected to Note
4750mA (166 MHz) ICC3
(2, 5) (6)
I CC3 4600mA (200 MHz) 650mA (200 MHz) 4330mA 5000mA (200 MHz)
2650mA (75 MHz) 540mA (166 MHz) 4330mA(125−180 MHz)
(3, 5)
I CC5 Not Applicable 200mA 200mA
(5)
Max. Power 15.5W (200 MHz) 15.7 W (200 MHz) 15.0 W 17.0W (200 MHz)
15.0W (125−180 MHz)
No. of VCC2 Pins None 25 None 28
No. of VCC3 Pins 53 28 60 32
No. of VCC5 Pins None 2 2
External Plane Unified Split Unified Unified or Split
Type
Internal Plane Unified Split Unified Split
Type
Package Type 296-pin PPGA or 296-pin PPGA or 320-pin CPGA 320-pin CPGA
CPGA CPGA
NOTES:
1. I CC3 refers to VCC3 (I/O) supply current.
2. I CC2 refers to VCC2 (Core) supply current.
3. I CC5 refers to 5V supply current. This is used to power the fan/heatsink on the Pentium OverDrive processors.
4. Pentium OverDrive processors and future Pentium OverDrive processors with MMX technology do not require the bus
frequency ratio to be changed when upgraded.
5. The number shown represents worst case or maximum current/power at highest available frequency.
6. When the future Pentium OverDrive processor with MMX technology is installed in split plane designs, 4600 mA at 3.3V is
drawn through VCC2 pins and 400 mA from VCC3 pins.
7. The 200 MHz future Pentium OverDrive processor with MMX technology will only be supported in Socket 7 designs.
INTEL CONFIDENTIAL
(until publication date)
AP-579
• CLK, PICCLK: The clock inputs on the Pentium Figure 2. EAX Bit Assignments for CPUID
processor with MMX technology are not 5V
tolerant. The clock inputs to the processor on the Table 3 provides the CPUID information for the
flexible motherboard are driven by an appropriate different processors that are supported on the
3.3V clock driver. Driving the clock at 3.3 volts is flexible motherboard.
also compatible with the Pentium processor 75 / 90 /
100 / 120 / 133 / 150 / 166 / 200, the Pentium
OverDrive processor, and the future Pentium
OverDrive processor with MMX technology.
10
INTEL CONFIDENTIAL
(until publication date)
E AP-579
INTEL CONFIDENTIAL
(until publication date)
AP-579
VCORE V I /O
(Vcc2) (Vcc3)
3.3V 5V
3Vpower supply (Vcc5)
Socket 7
D kt th b d 318703
INTEL CONFIDENTIAL
(until publication date)
E
VI/O — This power plane is connected to the VCC3 NOTE
AP-579
13
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
VCC2 VCC3 VCC2 VCC3 VCC2 VCC3
3.3V
3.3V
3.3V
3.3V
3.3V
2.8V
Pentium Processor, Pentium processor Pentium OverDrive processor
Pentium OverDrive Processor with MMX technology with MMX technology
(Unified-plane Processors) (Split-plane Processor) (Split-plane Processor)
Vcc2 = Vcc3 = 3.3V / VRE Vcc2 = 2.8V, Vcc3 = 3.3V / VRE Vcc2 = 3.3V / VRE, Vcc3 = 3.3V / VRE
318704
14
INTEL CONFIDENTIAL
(until publication date)
E AP-579
318705
Figure 5. Unified Plane Current Flow vs. Split Plane Current Flow
15
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
voltage regulators current share; however, this is
an implementation specific option and up to the
designer’s discretion.
VCC3 VCC2
MOSFET
3.5. Voltage Supply
VCC2DET# = 1 VCC2 connects to VCC3 Implementation Options
VCC2DET# = 0 VCC2 disconnects from VCC3
There are several voltage supply implementation
318706 options to support all the different Pentium family
processors on the flexible motherboard. The
following options will be discussed in this section:
Figure 6. Use of MOSFETs to
Connect/Disconnect Power Planes 1. Using a 2.8V/3.3V auto-configurable voltage
regulator.
If a unified-plane processor is plugged into a flexible 2. Using an on-board 2.8V regulator as a build
motherboard with two voltage regulators, one of the
option.
voltage regulators may “shut down”. The voltage
regulator attached to the VCC2 power pins will 3. Using the Voltage Regulator Module (VRM).
always have a much higher current rating than the Refer to Appendix A.
voltage regulator attached to the VCC3 power pins
because the VCC2 plane directly powers the
processor core. When a Pentium processor 75 / 90 / 3.5.1. 2.8V/3.3V AUTO-CONFIGURABLE
REGULATOR
100 / 120 / 133 / 150 / 166 / 200 or Pentium
OverDrive processor is plugged into the system, the
An auto-configurable regulator circuit is an option
current will flow from the VCC2 plane to the VCC3
for supply voltage implementation on the flexible
power plane and shut down the weaker voltage
motherboard. This approach allows all Pentium
regulator (the weaker voltage regulator will detect
processors 75 / 90 / 100 / 120 / 133 / 150 / 166 / 200,
the increased current and shut itself down). This is
Pentium OverDrive processors, Pentium processors
acceptable provided the 8A maximum specification
with MMX technology, and future Pentium
for current flow across a unified plane processor is
OverDrive processors with MMX technology to be
maintained (see Figure 7). However, when a split
easily supported without the need for any
plane processor, like the Pentium processor with
jumper/resistor configuration. Figure 8 shows two
MMX technology or the future Pentium OverDrive
regulators that work together to form an auto-
processor with MMX technology, is inserted in the
configurable voltage solution.
socket, the two regulators are electrically isolated
and each continues to function. Also, the designer
may design the motherboard such that the two
16
INTEL CONFIDENTIAL
(until publication date)
E AP-579
2.8V/VRE 3.3V
Regulator Regulator
4.6A at VRE
Unified-plane processor
2.65A - processor (Vcc3)
(200 MHz) Cache
Chipset
Chipset
Socket 7
VCORE
VIO
Cache
17
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
Cache and chipset feed from this plane
3.3V/VRE
I/O
Vout
2.8V/3.3V/VRE Voltage
(Core)
Plane
On-board 2.8V/3.3V auto-
configurable regulator for core
Socket 7
Both regulators current
VCC2DET# from CPU share when 3.3V or VRE
selects 2.8V or 3.3V No jumpers required to
CPU is installed or 3.3V/VRE connect the 2 planes in
for core regulator regulator shuts down auto-configurable mode
The VCC2DET# pin, defined on the Pentium 1. The VCC2DET# signal is not asserted and the
processor with MMX technology and Socket 7, is 2.8V/3.3V/VRE voltage regulator toggles to
used to steer the voltage regulator supplying the either 3.3V or VRE voltage.
processor core to the correct voltage depending on
which processor is in the socket. On the Pentium 2. The VCORE and VI/O power planes automatically
processor with MMX technology, the VCC2DET# become electrically shorted (VCORE + VI/O)
pin is always driven low (or grounded). On the because the processor unifies these two planes
Pentium processor 75 / 90 / 100 / 120 / 133 / 150 / internal to the package. This is within processor
166 / 200, Pentium OverDrive processor and future specification provided that the total sum of
Pentium OverDrive processor with MMX electrical current flowing through the processor
technology, this pin is an internal no connect; does not exceed 8A. The 2.8V/3.3V/VRE voltage
therefore, the VCC2DET# signal trace needs an regulator would have to be sized to
external pull-up resistor so that the auto- accommodate the current draw of any other
configurable regulator circuit does not confuse a components attached to the VCORE + VI/O plane.
Pentium processor 75 / 90 / 100 / 120 / 133 / 150 / The 8A of current should be adequate to power
166 / 200 with a Pentium processor with MMX
the processor, cache and chipset.
technology and apply the incorrect input voltages.
3. The 3.3/VRE voltage regulator will then shut
When a unified-plane processor (Pentium processor itself down as it detects the power flow of the
75 / 90 / 100 / 120 / 133 / 150 / 166 / 200 or Pentium much larger 2.8/3.3V/VRE voltage regulator.
OverDrive processor) is plugged into a Socket 7 in
the auto-configurable system, the following events When a split-plane, dual voltage processor (Pentium
take place: processor with MMX technology) is plugged into a
18
INTEL CONFIDENTIAL
(until publication date)
E
Socket 7 in the auto-configurable system, the
AP-579
19
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
Cache and chipset feed from this plane
3.3V/VRE
I/O
Vout
Voltage
(Core)
Plane
2.8V
INTEL CONFIDENTIAL
(until publication date)
E AP-579
Vcc3
VCC2DET#
Vcc3 B
Vcc3 A
Vcore
C to chipset or
Bias MB logic which
at ~2.8V RESETs CPU
LMC7211
or LM311 PowerGood
Comparator from Power Supply
318710
OUT Vcore
Vcc3
ADJ
Linear
Adjustable
Regulator
FET
Switch VCC2DET from CPU
318711
3.6. Split Power Plane Layout Figure 12 shows a typical layout of the separate
voltage islands in the processor area. It shows the
Implementing a power island on an existing power core VCC pins (VCC2) clustered on one side of the
layer instead of assigning a separate power layer processor to allow easy layout of the core voltage
for core VCC can be a more economical solution. island. The remaining VCC pins for the periphery
The separate voltage island can be isolated from the (VCC3) are located on the other side and are part of
other section of the power plane using an air gap. the I/O voltage island (refer to Socket 7 pinout, see
The size of the air gap is determined by analysis of Appendix B).
the noise effects and board manufacturing
capabilities (typically 10 −20 mils).
21
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
2.8V or 3.3V Core Vcc Island 3.3V I/O Vcc Island
Includes 3.3V
Cache SRAM,
chipset etc.
Socket 7
318712
The I/O VCC island should also include other 3.3V Routing of the power source to the voltage islands
components that interface with the processor. A should also be carefully done to avoid significant
typical configuration would include 3.3V cache voltage drop at the processor and an increase in
SRAM, 3.3V chipset I/O, and processor I/O on the thermal dissipation in the voltage islands. It is
same 3.3V I/O voltage island. This ensures that recommended that wide traces be used to prevent
signals interfacing between the processor and other excessive voltage drop across the power plane. Also
3.3V components operate at the same voltage levels. vias and through-holes cutting through the power
This is also to avoid split plane crossovers for these plane at critical widths should be avoided.
signals which is recommended for better signal
quality and reduced EMI/RFI effects.
3.7. Decoupling
When using jumpers or 0Ω resistors to connect the
two power planes (in the case of single voltage The small size of the processor core voltage island,
processors), the number of jumpers should be its isolation from the motherboard power plane, and
chosen so as to provide enough current carrying support of varied voltage requirements make
capability. Insufficient number of jumpers will proper decoupling of the island power plane voltage
result in excessive voltage drop and other reliability and ground plane essential. Appropriate decoupling
problems. For the flexible motherboard, a minimum capacitors are implemented on the voltage island
of four (six recommended) zero-ohm, #1206, 1/8 near the processor to ensure that the processor
watt, surface mount resistors should be used. voltage stays within specified limits during normal
and transient conditions. There are two types of
decoupling that need to be considered: bulk
decoupling and high frequency decoupling.
22
INTEL CONFIDENTIAL
(until publication date)
E
3.7.1. BULK DECOUPLING
AP-579
Table 5. Decoupling Recommendations for Processor Core and I/O Voltage Islands
Quantity Value ESR ESL Type
(1) (3)
Processor Core 4 100 µF 25 mOhms 0.45 nH Tantalum
Voltage Island
(2) (4)
25 1 µF 0.6 mOhms 0.084 nH X7R dielectric, ceramic
Processor I/O (5) 12 0.1 µF 603 Type
Voltage Island
23
INTEL CONFIDENTIAL
(until publication date)
AP-579
NOTES:
E
1. ESR per capacitor should be less than 100 mOhms.
2. ESR per capacitor should be less than 15 mOhms.
3. ESL per capacitor (including 0.7 nH Via inductance per capacitor) should be less than 2.7 nH.
4. ESL per capacitor (including 0.7 nH Via inductance per capacitor) should be less than 2.1 nH.
5. This does not include decoupling for components other than the processor in the 3.3V I/O voltage island.
For bulk decoupling, tantalum capacitors are
recommended over electrolytic capacitors. In
general, electrolytic capacitors degrade at a much 3.7.4. PLACEMENT OF DECOUPLING
CAPACITORS
faster rate, are not as accurate, and are not as
stable over temperature as tantalum capacitors.
Figure 14 shows an example of how the
recommended processor decoupling capacitors
For high speed decoupling in the processor core
(Table 5) should be placed inside the respective
voltage island, low inductance, 1µF capacitors of
voltage islands on the flexible motherboard. The
X7R dielectric are recommended. These capacitors
bulk capacitors should be placed near the processor
not only decouple the processor core for high
inside the voltage island to ensure that the supply
frequency noise but also control the voltage during
voltage stays within specified limits during changes
very fast transients (less than 100 ns.) Figure 13
in the supply current during operation. The 1 µF,
shows that ceramic capacitors of X7R (or X7S)
X7R capacitors should be evenly distributed inside
dielectric exhibit relatively stable capacitor
the processor core voltage island inside and around
characteristics over temperature compared to
the processor footprint. Figure 12 also shows the
capacitors of Z5U or Y5V type dielectric. For
twelve 0.1 µF capacitors evenly placed around the
example, at a typical operating temperature of
processor, close to the processor VCC3 pins inside
45°C, the Y5V dielectric can lose 45% of the initial
the processor I/O voltage island.
rated capacitance.
In this example, all the capacitors were placed on
Measurement techniques to ensure that
one side of the board. If components are assembled
motherboard designs are within VCC noise and
on both sides of the board then these capacitors can
transients specification are discussed in the
be distributed between the top and bottom sides. If
following application notes (see Appendix E for
done this way, vias connecting the capacitor pads to
order information).
the power and ground layer can be shared between
• Voltage Guidelines for Pentium Processors the capacitors on the top and bottom sides. This can
with MMX Technology Processors help reduce the total overall capacitor inductance.
• Implementation Guidelines for Pentium
Processors with VRE Specifications
24
INTEL CONFIDENTIAL
(until publication date)
E AP-579
-10
-20
Temp. Coefficient (Spec.)
-30 X7R: +/- 15%
% ∆C Z5U: +22% -56%
-40 Y5V: +22% -82%
-50
-60
-70
-80
-25 0 25 50 75
Temperature (Degrees Celsius)
25
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
100uF Tantalum
0.1uF (603)
318714
The traces connecting the vias to the capacitor pads strobes, data lines, and low address lines) when
should be kept as short as possible. In cases where it their return path is interrupted. On a multi-layer
is difficult to reduce the length of the circuit board board this return path is on the power or ground
trace, the trace should be made wider so as to plane that is adjacent to the signal layer directly
reduce the trace inductance. under the signal trace. If this trace is routed over a
break in the return path, the return current has to
find another longer path in order to maintain
3.8. Signal Routing Guidelines current continuity. The increased area generated by
the signal trace and the length of this extended
As the power plane on the flexible motherboard is return path can lead to increased radiation levels
split into separate voltage islands, signal routing from this signal trace.
should be done in such a way so as to minimize
crossovers between voltage islands for high speed The following guidelines should be followed when
signals. Signal routing between the voltage islands routing high speed signals on the flexible
and the system power plane should be limited to motherboard:
only those signals that absolutely need to cross the
gap between the island and the power plane. This is Clocks and Strobes: These signals should not be
to avoid possible signal degradation from routed over breaks in the reference plane return
impedance discontinuity effects. Significant levels of path. Use of vias to connect between signal planes
EMI could be generated by electromagnetic should be minimized, and the signal planes should
radiation from high speed traces (such as clocks, be within 8 mils of the reference plane. Clock
26
INTEL CONFIDENTIAL
(until publication date)
E
signals should be routed on the layer that is
AP-579
The thermal design of a system using the flexible • Space greater than specified above for end-user
motherboard should be based on the worst case installation.
power dissipation and related thermal requirements
for the processors that are supported. 3.9.1. VOLTAGE REGULATOR THERMAL
DESIGN CONSIDERATIONS
The Pentium processor 75 / 90 / 100 / 120 / 133 / 150
/ 166 / 200 and Pentium processor with MMX Voltage regulators are typically shipped with
technology use OEM specified heatsinks which are passive heatsinks for heat dissipation and may
dependent upon the entire system cooling solution. require adequate airflow. For a 45 to 50°C ambient
The maximum case temperature for these temperature, voltage regulators typically call for an
processors should not exceed 70°C to ensure proper airflow of 200 LFM to ensure proper cooling. The
operation. Heatsinks also may need a certain airflow is parallel to the surface of the voltage
airflow in order to maintain their specified regulator to ensure that the heatsink receives
temperature. For detailed information refer to the adequate airflow. Refer to your voltage regulator
respective datasheet for these processors (see datasheet for actual specifications.
Appendix E). In addition, detailed discussion of
thermal design issues for the Pentium processor is
covered in Pentium® Processor Thermal Design 3.9.2. DESKTOP SYSTEM THERMAL
Guidelines (see Appendix E). DESIGN CONSIDERATIONS
The Pentium OverDrive processors and future To avoid localized heating at the processor, a clear
Pentium OverDrive processors with MMX air path and adequate venting is provided to
technology are shipped with integrated fan/heatsink prevent hot spots from occurring. A typical solution
cooling solutions. Although these fan/heatsinks to this thermal problem is to add an auxiliary fan to
remove the heat from the package, the system the front vents of the chassis, directing airflow
should be able to dissipate the added heat to the across the processor. While this solution would
system. From Table 1, the future Pentium appear to be fairly simple, the addition of a second
OverDrive processor with MMX technology fan can actually cause the problem to intensify.
27
INTEL CONFIDENTIAL
(until publication date)
AP-579
A
0.2"
0.2" Airspace Ta <= 45’C MIN
0.4" MIN @ 0.3"
MIN
Above
Pkg
Surface
Fan/Heat Sink
Airspace
Package Airspace
Surface Mnt
Component
B Socket
318715
When adding an auxiliary fan to the system, the size that it can support all the different processors on
of the chassis vents deserves special consideration. the flexible motherboard. The BIOS code should use
The fan is most effective when all of the air pushed the CPUID instruction to identify the processor’s
through the fan blades comes from outside the CPUID signature (see Section 2.3.).
chassis. If the vents are too small or inadequate for
the fan velocity, gaps between the fan and chassis
will cause air from inside the system to be drawn
through the fan, causing re-circulation of heated
air. The position of the fan is also critical. The
highest air flow is from the blades and not from the
center of the fan. Care should be taken not to block
the blades with frame supports.
3.10. BIOS/Software
Considerations
As the flexible motherboard can accommodate a
variety of processors, the BIOS is designed such
28
INTEL CONFIDENTIAL
(until publication date)
E
Other considerations for BIOS/software on the
AP-579
29
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
I/O Island
Secondary
Socket
Core Island
Primary
Socket
(Socket 7)
318716
The following needs to be considered when should not be designed with the Socket 7
designing a split plane flexible motherboard with footprint.
two sockets: NOTE
• The power islands should be laid out such that Pentium OverDrive processors and future
the processor cores share one common island Pentium OverDrive processor with MMX
and the I/O share another island. This minimizes technology do not support dual processor
operation. The 296-pin LIF or ZIF socket
the number of islands resulting in better signal
should be used at the secondary socket
quality and reduced EMI effects.
location.
• Socket 7 should only be used at the primary • The primary socket location should always be
socket location. The secondary socket footprint populated. The nets should be balanced for
30
INTEL CONFIDENTIAL
(until publication date)
E worst case timing when the primary processor is
AP-579
31
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
32
INTEL CONFIDENTIAL
(until publication date)
E AP-579
APPENDIX A
A1.0. VOLTAGE REGULATOR motherboard is the pinout and ease in changing the
MODULE processor supply voltage after assembly. By following
a common pinout specification, a variety of VRMs
The Voltage Regulator Module (VRM) offers may be developed by the OEM and third party
flexibility in that it allows processors with different vendors to support the Pentium processor family.
voltage and current requirements to be easily
supported on the flexible motherboard. The VRM is a Figure 17 shows how the Voltage Regulator Module
voltage converter with a pinout capable of converting allows processors with different voltage and current
a system power supply voltage to the voltage requirements to be supported on the flexible
necessary for the processor core. The only difference motherboard using interchangeable VRMs.
between the VRM and a voltage regulator on the
318717
33
INTEL CONFIDENTIAL
(until publication date)
AP-579
34
INTEL CONFIDENTIAL
(until publication date)
E
The primary output of the VRM is through the VCORE
AP-579
INTEL CONFIDENTIAL
(until publication date)
AP-579
VRM PCB
B B
VSS VSS VI/O VI/O +3.3V +3.3v VCORE VCORE VCORE VCORE RES DISABLE VSS +5V +5V
A A
VSS VSS +12V V/IO +3.3v +3.3V VCORE VCORE VSS VCORE PWRGOOD SENSE VSS +5V +5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
318718
36
INTEL CONFIDENTIAL
(until publication date)
E
A3.0. VOLTAGE REGULATOR MODULE QUICK PIN REFERENCE
AP-579
The pin definitions of the Voltage Regulator Module socket are as follows.
+3.3V Input +3.3V Supply, may be used for OEM processor regulation supply, a control signal
pull-up or as a supply to the VI/O plane. The +3.3V input is connect to the VI/O
output on the Pentium® OverDrive® processor with MMX™ technology module.
+5V Input +5V Supply may be used for Pentium processor family regulation to 3.3V/VRE
+12V Input +12V Reference Supply, may be necessary for some Voltage Regulator Modules
targeting VRE specifications.
DISABLE Input When driven high, this input will disable the Voltage Regulator Module output and
the output of the module will float.
PWRGOOD Output Power Good is an open collector output driven low when the VRM output is not
within valid levels.
SENSE Input Sense is provided for the regulator to correct for voltage drops across the
connector and motherboard power plane. This signal should be connected to the
center of the VCORE plane.
VI/O Output Processor I/O power connection. Allows for VRM to specify I/O voltage.
37
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
38
INTEL CONFIDENTIAL
(until publication date)
E AP-579
APPENDIX B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A A
VSS D41 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 D22 D18 D15 NC
B B
VCC2 D43 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D20 D16 D13 D11
C C
INC D47 D45 DP4 D38 D36 D34 D32 D31 D29 D27 D25 DP2 D24 D21 D17 D14 D10 D9
D D
D50 D48 D44 D40 D39 D37 D35 D33 DP3 D30 D28 D26 D23 D19 DP1 D12 D8 DP0
E E
D54 D52 D49 D46 D42 VSS VSS VCC2 NC VSS VCC3 VSS NC VCC3 VSS VSS D7 D6 VCC3
F F
DP6 D51 DP5 D5 D4
G G
VCC2 D55 D53 D3 D1 VCC3
H H
VSS D56 PICCLK VSS
J J
VCC2 D57 D58 PICD0 D2 VCC3
K K
VSS D59 D0 VSS
L L
VCC2 D61 D60 VCC3 PICD1 VCC3
M M
VSS D62 TCK VSS
N N
VCC2 D63 DP7 TDO TDI VCC3
P P
VSS IERR# TMS# VSS
Q Q
VCC2 PM0BP0 FERR# TRST# CPUTYP VCC3
R R
VSS PM1BP1 NC VSS
S S
VCC2 BP2 BP3 NC NC VCC3
T T
VSS MI/O# VCC3 VSS
U U
VCC2 CACHE# INV VCC3 VSS VCC3
V V
VSS AHOLD STPCLK# VSS
W W
VCC2 EWBE# KEN# NC NC VCC3
X X
VSS BRDY# BF1 VSS
Y Y
VCC2 BRDYC# NA# BF FRCMC# VCC3
Z Z
VSS BOFF# PEN# VSS
AA AA
VCC2 PHIT# WB/WT# INIT IGNNE# VCC3
AB AB
VSS HOLD SMI# VSS
AC AC
VCC2 PHITM# PRDY NMI RS# VCC3
AD AD
VSS PBGNT# INTR VSS
AE AE
VCC2 PBREQ# APCHK# A23 D/P# VCC3
AF AF
VSS PCHK# A21 VSS
AG AG
VCC2 SMIACT# PCD A27 A24 VCC3
AH AH
VSS LOCK# KEY A26 A22
AJ AJ
BREQ HLDA ADS# VSS VSS VCC2 VSS NC VSS VCC3 VSS NC VSS VSS VCC3 VSS A31 A25 VSS
AK AK
AP D/C# HIT# A20M# BE1# BE3# BE5# BE7# CLK RESET A19 A17 A15 A13 A9 A5 A29 A28
AL AL
VCC2DET PWT HITM# BUSCHK# BE0# BE2# BE4# BE6# SCYC NC A20 A18 A16 A14 A12 A11 A7 A3 VSS
AM AM
ADSC# EADS# W/R# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A8 A4 A30
AN AN
VCC5 VCC5 INC FLUSH# VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 A10 A6 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
318719
39
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A A
NC D15 D18 D22 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 D41 VSS
B B
D11 D13 D16 D20 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D43 VCC2
C C
D9 D10 D14 D17 D21 D24 DP2 D25 D27 D29 D31 D32 D34 D36 D38 DP4 D45 D47 INC
D D
DP0 D8 D12 DP1 D19 D23 D26 D28 D30 DP3 D33 D35 D37 D39 D40 D44 D48 D50
E E
VCC3 D6 D7 VSS VSS VCC3 NC VSS VCC3 VSS NC VCC2 VSS VSS D42 D46 D49 D52 D54
F F
D4 D5 DP5 D51 DP6
G G
VCC3 D1 D3 D53 D55 VCC2
H H
VSS PICCLK D56 VSS
J J
VCC3 D2 PICD0 D58 D57 VCC2
K K
VSS D0 D59 VSS
L L
VCC3 PICD1 VCC3 D60 D61 VCC2
M M
VSS TCK D62 VSS
N N
VCC3 TDI TDO DP7 D63 VCC2
P P
VSS TMS# IERR# VSS
Q Q
VCC3 CPUTYP TRST# FERR# PM0BP0 VCC2
R R
VSS NC PM1BP1 VSS
S S
VCC3 NC NC BP3 BP2 VCC2
T T
VSS VCC3 MI/O# VSS
U U
VCC3 VSS VCC3 INV CACHE# VCC2
V V
VSS STPCLK# AHOLD VSS
W W
VCC3 NC NC KEN# EWBE# VCC2
X X
VSS BF1 BRDY# VSS
Y Y
VCC3 FRCMC# BF NA# BRDYC# VCC2
Z Z
VSS PEN# BOFF# VSS
AA AA
VCC3 IGNNE# INIT WB/WT# PHIT# VCC2
AB AB
VSS SMI# HOLD VSS
AC AC
VCC3 RS# NMI PRDY PHITM# VCC2
AD AD
VSS INTR PBGNT# VSS
AE AE
VCC3 D/P# A23 APCHK# PBREQ# VCC2
AF AF
VSS A21 PCHK# VSS
AG AG
VCC3 A24 A27 PCD SMIACT# VCC2
AH AH
A22 A26 KEY LOCK# VSS
AJ AJ
VSS A25 A31 VSS VCC3 VSS VSS NC VSS VCC3 VSS NC VSS VCC2 VSS VSS ADS# HLDA BREQ
AK AK
A28 A29 A5 A9 A13 A15 A17 A19 RESET CLK BE7# BE5# BE3# BE1# A20M# HIT# D/C# AP
AL AL
VSS A3 A7 A11 A12 A14 A16 A18 A20 NC SCYC BE6# BE4# BE2# BE0# BUSCHK# HITM# PWT VCC2DET
AM AM
A30 A4 A8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R# EADS# ADSC#
AN AN
VSS NC A6 A10 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 FLUSH# INC VCC5 VCC5
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
318720
40
INTEL CONFIDENTIAL
(until publication date)
E
B2.0. SOCKET 7 QUICK PIN REFERENCE
AP-579
Socket 7 has the same pin definition as Socket 5 with the exception of the following pins.
41
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
42
INTEL CONFIDENTIAL
(until publication date)
E AP-579
APPENDIX C
C1.0. LINEAR AND SWITCHING or accurate of all vendor solutions, but they are
REGULATOR SOLUTIONS intended as a voltage regulator reference lists for
known 2.8V/3.3V/VRE regulator solutions. Please
Appendix C contains a list of Linear/Switching contact your vendor for their latest product
Voltage Regulator solutions. These lists may not be all specifications.
inclusive
43
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
2.8V/3.3V/VRE Linear Regulator Solutions (Contd)
Electrical Availability
IOUT Power
Part VIN VOUT (Max) (Max) Remote
Vendor Number (V) (V) (A) (W) Sense Package Sample Product
LM2951 5 2.8 7 15.4 No SO-8 Now Now
National 5 3.3/VRE 7 11.9
LM3411 5 3.3/VRE 7 11.9 No SO-8/ Now Now
5-pin SOT
23
Raytheon RC5102 5 2.8 7 15.4 Yes 8-pin Now Now
(Dual) SOIC
5 3.3/VRE 7 11.9
EZ1083/A 5 2.8 7.5 16.5 No TO-220 or Now Now
5 3.3/VRE 7.5 12.75 TO-247
EZ1082 5 2.8 10 22.0 No TO-220 or Now Now
5 3.3/VRE 10 17 TO-247
Semtech EZ1584A 5 2.8 7 15.4 No TO-220 Now Now
5 3.3/VRE 7 11.9
EZ1900 5 2.8 7 15.4 No 8-pin Now Now
SOIC
(Dual) 5 3.3/VRE 7 11.9
EZ1580 5 2.8 7 15.4 Yes 5-pin Now Now
TO-220
5 3.3/VRE 7 11.9
EZ1585D 5 2.8 6 13.2 No TO-220 Now Now
5 3.3/VRE 6 10.2
Unisem US1080 5 2.8 8 17.6 No TO-220/ Q1’97 Q1’97
TO-263
5 3.3/VRE 8 13.6
44
INTEL CONFIDENTIAL
(until publication date)
E AP-579
45
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
2.8V/3.3V/VRE Switching Regulator Solutions (Cond)
Electrical Availability
IOUT Solution Number
Part VIN VOUT (Max) Efficency of
Vendor Number (V) (V) (A) (typical) MOSFETs Package Sample Product
National LM3578 & 5 3.3/VRE 10 88% 1 SO-8 or Now Now
LM3411 5-pin SOT23
RC5036 5 2.8 10 87% 2 16-pin SOIC Now Now
(Dual)
5 3.3/VRE 5 89%
Raytheon RC5031 5 2.8 10 87% 1 14-pin SOIC Now Now
5 3.3/VRE 5 89%
RC5035 5 2.8 10 87% 2 16-pin SOIC Now Now
(Dual)
5 3.3/VRE 5 89%
Si9140 5 2.8 6 90% 2 16-pin SOIC Now Now
Siliconix 5 3.3 6 90.5%
Si9145 5 2.8 6 82% 1 16-pin SOIC or Now Now
5 3.3/VRE 6 83% 16-pin TSSOP
UC3886 5 2.8 10 85% 1 16-pin SOIC or Now Now
5 3.3/VRE 10 85% 16-pin DIP
UCC3881 5 2.8 10 85% 1 16-pin SOIC or Now Q1‘97
Unitrode 5 3.3/VRE 10 85% 16-pin DIP
UCC3880 5 2.8 10 85% 1 20-pin SOIC or Now Now
5 3.3/VRE 10 85% 20-pin DIP
UC3874 5 2.8 10 90% 2 18-pin SOIC or Now Now
5 3.3/VRE 10 90% 18-pin DIP
Unisem US2050 5 2.8 10 85% 1 7-pin TO-220 Q1’97
5 3.3/VRE 10 85% or TO-263
46
INTEL CONFIDENTIAL
(until publication date)
E AP-579
APPENDIX D
47
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
Voltage Regulator Modules
Vendor North America Europe APAC Japan
Ambit Leonard Kao
Tel: (886) 35-7849575
Fax: (886) 35-782924
Socket 7
Vendor North America Europe APAC Japan
Amp Bob Branden Rob Rix H. Itoh
Tel: (910) 855-2247 Tel: (44) 753-67-6892 Tel: (81) 44-844-8086
Fax: (910) 855-2224 Fax: (44) 753-67-6808 Fax: (81) 44-812-3203
48
INTEL CONFIDENTIAL
(until publication date)
E AP-579
Header 7
Vendor North America Europe APAC Japan
Amp Larry Freeland Rob Rix H. Itoh
Tel: (717) 780-6045 Tel: (44) 753-67-6892 Tel: (81) 44-844-8086
Fax: (717) 780-7027 Fax: (44) 753-67-6808 Fax: (81) 44-812-3203
Decoupling Capacitors
Vendor Part No. Type North America APAC
AVX 1206YZ105KAT1A 1µF, X7S Dennis Lienemann Steve Chan (Singapore)
Tel: (803) 946-0616 Tel: (65) 258-2833
Fax: (65) 258-8221
Hong Kong
Tel: (852) 782-2618
Fax: (852) 782-1545
Korea
Tel: (82) 2-730-7605
Fax: (82) 2-739-5483
Taiwan
Tel: (886) 2-712-5090
Fax: (886) 2-712-3090
Hong Kong
Tel: (852) 736-2238
Fax: (852) 736-2108
49
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
Shorting Blocks
Vendor North America Europe APAC Japan
Amp Larry Freeland Rob Rix H. Itoh
Tel: (717) 780-6045 Tel: (44) 753-67-6892 Tel: (81) 44-844-8086
Fax: (717) 780-7027 Fax: (44) 753-67-6808 Fax: (81) 44-812-3203
Foxconn Julia Jang or Paul Fitting Wesley Lin or Ivan Liaw
Tel: (408) 749-1228 Tel: (886) 2-268-3466
Fax: (408) 749-1266 Fax: (886) 2-268-3225
Molex Micheal Gits (Molex) (Molex) (Molex)
Tel: (408) 946-4700 Tel: (49) 89-413092-0 Tel: (65) 268-6868 Tel: (81) 427-21-5539
Fax: (408) 946-5386 Fax: (49) 89-401527 Fax: (65) 265-6044 Fax: (81) 427-21-5562
Resistors
Vendor Size Type Accuracy/ Value Contact
Thin Film 1208 thin 0.1%, 100-250KΩ (507) 625-8445
Technology 0.5%, 10-250KΩ Region Sales Mgrs
0805 thin 0.1%, 100-100KΩ Patrick Lyons x14
0.5%, 10-1MΩ W. of Mississippi
(except TX & S. Cal)
0803 thin 0.1%, 100-33KΩ Mark Porisch x12
0.5%, 10-330KΩ Southern US, E. of
Mississippi (inc. TX)
0402 thin 0.5%, 10-100KΩ Tim Goertzen x13
Northern U.S., E. of
Mississippi & Canada
Mike Smith
(310) 768-8923
Southern California
Dale Electronics 0603 thin 0.5%, 10-100ΚΩ Gary Bruns
(402) 371-0080
thick 1%,2%, 10-1ΜΩ
805 thin 0.1%, 100-100ΚΩ
Koa Spear 805 thin 0.1%, 100-100ΚΩ T. Yogi
(814) 362-5536
thick 0.5-5%, 10-1ΜΩ
Beckman 0805 thin 0.1%, 10K-100ΚΩ Cathy Whittaker
Industrial (214) 392-7616
thick 1-5%, 10-1MW
0603 thick 1-5%, 10-1MW
50
INTEL CONFIDENTIAL
(until publication date)
E AP-579
51
INTEL CONFIDENTIAL
(until publication date)
AP-579 E
52
INTEL CONFIDENTIAL
(until publication date)
E AP-579
APPENDIX E
53
INTEL CONFIDENTIAL
(until publication date)
AP-579
Product Information
Document Title Notes ID/PDDC Document Number
Pentium® Processor Specification Update FMKIHU
200 MHz P54CS-cC0 Stepping Information, Rev. 1.0 EW3Q1T
P55C BIOS Compatibility CW1QGR
P55C External Design Specification (EDS), Rev. 3.1 SC-1294
P55C Platform Architecture Analysis, Rev. 3.0 SC-1263
E2.0. REFERENCES
Clyde F. Coombs, Jr., Printed Circuits Handbook, McGraw Hill Publishing Co., New York, 1988
54
INTEL CONFIDENTIAL
(until publication date)
UNITED STATES, Intel Corporation
2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119
Tel: +1 408 765-8080
Printed in USA/96/POD/PMG