Final Image Compression Based Fuzzy

Design and FPGA Implementation of Image Compression based Fuzzy Technique
CHAPTER 1
INTRODUCTION
The digital multimedia is popular because of their highly perceptual effects and
the advanced development its corresponding technology. However, it often requires a
large amount of data to store these multimedia contents due to the complex information
they may encounter. Besides, the requirement of resolution is much higher than before,
such that the data size of the image is surprisingly large.
In other words, a still image is a sensory signal that contains significant amount of
redundant information which exists in their canonical forms. Image data compression is
the technique of reducing the redundancies in image data required to maintain a given
quantity of information. The underlying basis of the reduction process is the removal of
redundant data. From a mathematical viewpoint, this is a process of transforming a 2-D
pixel array into a statistically uncorrelated data set .The transformation is applied prior to
storage or transmission of the image.
Currently image compression is recognized as an enabling technology. In
addition to the areas just mentioned, image compression is the natural technology for
handling the increased spatial resolution of todays imaging sensors and evolving
broadcast television standards. Furthermore image compression plays a major role in
many important and diverse applications, including tele-video-conferencing, remote
sensing (the use of satellite imagery for weather and other earth resource applications),
document and medical imaging facsimile transmission (FAX), and the control of remotely
piloted vehicles in military, space and hazardous waste management applications.
This project work explores the implementation of 2Dimentional DWT algorithm
on FPGA for image compression using fuzzy logic. Several architectures have been
proposed such as convolution based, lifting based and B-spline based. These architectures
are compared in terms of hardware complexity, critical path, and registers. As for the 2D
DWT the large amount of the memory access and the area required that becomes the most
critical issue so it also affects the total area and power. Finally, a flexible and efficient
proposed architecture has been selected for designing two-level 2D-DWT. The proposed
architecture has advantages over other architectures such as very less number of
multipliers, less area and less memory utilization.
DEPT ECE SJBIT BANGALORE
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Most of the applications require real-time DWT engines with large computing
potentiality for which a fast and dedicated very-large-scale integration (VLSI)
architecture appears to be the best possible solution. While it ensures high resource
utilization, that too in cost effective platforms like field programmable gate array
(FPGA), designing such architecture does offer some flexibilities like speeding up the
computation by adopting more pipelined structures and parallel processing, possibilities
of reduced memory consumptions through better task scheduling or low-power and
portability features.
Design and VLSI implementation of high speed, low power 2D wavelet
architecture is focused on image compression application. Flexible hardware architecture
is designed for performing 2D Discrete Wavelet Transform. The proposed architecture
uses fuzzy logic and fast convolution scheme which has the ability of performing
progressive computations by minimizing the buffering between the decomposition levels.
1.1 DIGITAL IMAGE PROCESSING

An image may be defined as a two-dimensional function f(x y) where x and y are
spatial (plane) co-ordinates and amplitude of f at any pair of co-ordinates (x, y) is called
the intensity or gray level of image at that point. Where x, y and amplitude values of f
are all finite, discrete quantities then it called digital image processing. The field of digital
image processing refers to processing digital images by means of a digital computer. Note
that a digital image is composed of a finite number of elements, each of which has a
particular location and value. These elements are referred to as picture elements, image
elements, pixels. Pixel is the term most widely used to denote the elements of a digital.
Figure 1.1: Digital image

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1.2 IMAGE COMPRESSION

Image compression is an application of data compaction that can reduce the
quantity of data. The block diagram of image coding system is shown in Figure 1.2.
Camera
C
R-G-B
coordinate
Transform to
Y-Cb-Cr
coordinate
Object
Downsample
Chrominance
Encoder
RateDstortion
Comparison
HDD
Upsample
Chrominance
Decoder
Monitor
C
R-G-B
coordinate
Transform to
R-G-B
coordinate
Figure 1.2: The block diagram of the general image storage system.
The camera captures the reflected light from the surface of the object, and the received
light will be converted into three primary color components R, G and B. These three
primary color components are processed by coding algorithms afterward.
Image compression addresses the problem of reducing the amount of data required to
represent a digital image. It is a process intended to yield a compact representation of an
image, thereby reducing the image storage/transmission requirements. Compression is
achieved by the removal of one or more of the following three basic data redundancies:
1.
Coding Redundancy
2.
Inter-pixel Redundancy
3.
Perceptual Redundancy
Coding redundancy occurs when the codes assigned to a set of events such as the pixel
values of an image have not been selected to take full advantage of the probabilities of the
events.
Inter-pixel redundancy usually results from correlations between the pixels. Due to the
high correlation between the pixels, any given pixel can be predicted from its neighboring
pixels.
Perceptual redundancy is due to data that is ignored by the human visual system. In other
words, all the neighboring pixels in the smooth region of a natural image have a high
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degree of similarity and this insignificant variation in the values of the neighboring pixels
is not noticeable to the human eye.
Image compression techniques reduce the number of bits required to represent an image
by taking advantage of these redundancies. An inverse process called decoding is applied
to the compressed data to get the reconstructed image. The objective of compression is to
reduce the resolution/intensity as much as possible, while keeping the number of bits and
the quality of the reconstructed image as close to the original image as possible.
Image compression systems are composed of two distinct structural blocks: an encoder
and a decoder, as shown in Figure 1.3.
f(x, y)
Mapper
quantizer
Symbol
coder
Compressed image
Symbol
decoder
Inverse
Mapper
f(x, y)
Figure 1.3: Image compression system

Image f(x, y) is fed into the encoder, which creates a set of symbols form the input data
and uses them to represent the image. If we let n1 and n2 denote the number of
information carrying units in the original and encoded images respectively, the
compression that is achieved can be quantified numerically via the compression ratio, C R
= n1/n2
As shown in above Figure, the encoder is responsible for reducing the coding, inter-pixel
and perceptual redundancies of input image. In first stage, the mapper transforms the
input image into a format designed to reduce inter-pixel redundancies. The second stage,
qunatizer block reduces the accuracy of mappers output in accordance with a predefined
criterion. In third and final stage, a symbol decoder creates a code for quantizer output
and maps the output in accordance with the code. These blocks perform, in reverse order,
the inverse operations of the encoders symbol coder and mapper block. As quantization
is irreversible, an inverse quantization is not included.
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The benefits of image compression can be listed as follows:
It provides a potential cost savings associated with sending less data over switched
telephone network where cost of call is really usually based upon its duration.
It not only reduces storage requirements but also overall execution time.
It reduces the transmission errors since fewer bits are transferred.
It also provides a level of security against illicit monitoring.
The image compression techniques are broadly classified into two categories depending
whether or not an exact replica of the original image could be reconstructed using the
compressed image. These are:
Lossy technique
Lossless technique
1.2.1 Lossy Compression Techniques

Lossy schemes provide much higher compression ratios than lossless schemes. Lossy
schemes are widely used since the quality of the reconstructed images is adequate for
most applications. By this scheme, the decompressed image is not identical to the original
image, but reasonably close to it.
Figure 1.4: Lossy image compression

As shown in Figure 1.4, this prediction transformation decomposition process is
completely reversible. The quantization process results in loss of information. The
entropy coding after the quantization step, however, is lossless. The decoding is a reverse
process. Firstly, entropy decoding is applied to compressed data to get the quantized data.
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Secondly, de-quantization is applied to it and finally the inverse transformation to get the
reconstructed image.
Major performance considerations of a lossy compression scheme include:
Compression ratio
Signal - to noise ratio
Speed of encoding and decoding.
Lossy compression techniques includes following schemes:
Transform Coding
Ector Quantization
Fractal Coding
Block Truncation Coding
Sub-band Coding
1.2.2 Lossless Compression Techniques

In lossless compression techniques, the original image can be perfectly recovered from
the compressed image. These are also called noiseless since they do not add noise to the
signal. It is also known as entropy coding since it use decomposition techniques to
minimize redundancy.
Following techniques are included in lossless compression:
Run length encoding
Huffman encoding
LZW coding
Area coding
1.3 FUZZY DOMAIN

Fuzzy set theory is thus useful in handling various uncertainties in computer vision and
image processing applications. Fuzzy image processing is a collection of different fuzzy
approaches to image processing that can understand, represent, and process the image. It
has three main stages, namely, image fuzzification, modification of membership function
values, and defuzzification. Fuzzy image enhancement is based on gray level mapping
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into membership function. The aim is to generate an image of higher contrast than the
original image by giving a larger weight to the gray levels that are closer to the mean gray
level of the image that are farther from the mean.
a. Fuzzy Set
In classical set theory, a set is defined as a collection of element having a certain property,
each of belongs to the set. So the characteristic function takes either the value of 0 or 1.
Let us consider a classical set, X, called the universe, whose elements are denoted as x,
that is, X= {x1, x2 ,.. xn}. Consider a subset A of the set X such that an element
x of X is a member of A if
( )
( )
So fuzzy set A is defined as:
*(
Where
( ))
( ) is a membership function for a fuzzy set. Examples of membership
functions (triangular, trapezoidal, Gaussian,) can be seen in figure below and described
with the following formulas:
Triangular Membership Function: Triangular membership function is defined as a
following equation:
0
if x a;
Triangular(x; a, b, c) =
if c x;
Trapezoidal Membership Function: Trapezoidal membership function is defined as a

following equation:
0
if x a;
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Trapezoidal(x; a, b, c, d) = 1 if b x a;
if d x;
Gaussian Membership Function: Gaussian Membership Function is defined as following

equation:
Gaussian(x, m, )
Where m = mean, and is the standard deviation.
Figure 1.5: Examples of Membership Function

b. Linguistic Variables
The concept of linguistic variables was introduced by Zadeh to provide a basis for
approximate reasoning. A linguistic variable was defined as a variable whose values are
words or sentences. For instance, Age can be linguistic variable if its values are linguistic
rather than numerical, i.e., young, middle age; old are represented by the membership
function.
0-10
40-50
10-20
50-60
20-30
60-70
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70 and above
Figure 1.6: Membership Function of the Term Set age.

c. Rule Based System
The theory of fuzzy IF-THEN rules was proposed by Zadeh. The general form of a rule is
as follows:
If x is A THEN y is B
Where A and B are linguistic values defined by fuzzy sets. x
is A
is
called
antecedent or premise, while y is B is called the consequence or

conclusion respectively.
Some of the if-then rule examples can be given below:
If the speed is low and the distance is small, then the force on brake should be
small.
If pixel is dark AND its neighborhood is also dark AND homogeneous THEN it
belongs to the background.
d. Fuzzy Reasoning
Fuzzy reasoning, approximate reasoning, is an inference procedure whose outcome is
conclusion for a set of fuzzy if-then rules. The steps of fuzzy reasoning can be given as
follows:
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Input variables are compared with the membership function on the premise part to
obtain the membership values of each linguistic label (fuzzification).
The membership values on the premise part are combined through specific fuzzy
set operations such as: min, max, or multiplication to get firing strength
(weight) of each rule.
The qualified consequent (either fuzzy or crisp) is generated depends on the firing
strength.
The qualified consequents are aggregated to produce crisp output according to

the defined methods such as: cancroids of area, bisector of area, mean of
maximum, smallest of maximum and largest of maximum ( defuzification ).
e. Rules of fuzzy reasoning:

Rules
If x is A1 and y is B1 Then z is C1
If x is A2 and y is B2 Then z is C2
Figure 1.7: Rules of Fuzzy Reasoning

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f. Fuzzy Inference System
Fuzzy systems are made of a knowledge base and reasoning mechanism called fuzzy
inference system. A fuzzy inference system (FIS) consists of four functional blocks as
shown in Figure 1.8.
Figure 1.8: Fuzzy Inference System
Figure 1.9: Membership Function Modification
Fuzzification: Transforms the crisp inputs into degrees of match with linguistic
values. Reverse process of defuzzification.
Knowledge Base: Consists of a rule base and a database. A rule base contains a
number of fuzzy if-then rules. A database defines the membership function of the
fuzzy sets used in the fuzzy rules.
Fuzzy Inference Engine: Fuzzy Inference engine performs the inference

operations on the rules.
Defuzzification: This conversion of fuzzy set to single crisp value is called

defuzzification.
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g. Fuzzy Image Processing
Fuzzy image processing is collection of all approaches that understand, represent and
process the images, their segments and features as fuzzy sets. The representation and
processing depend on the selected fuzzy technique and on the problem to be solved.
Expert knowledge
Input image
Membership
modification
Image
fuzzification
Image defuzzification
output
image
Fuzzy logic
Figure 1.10: Fuzzy Image Processing

The fuzzification and defuzzification steps are due to the fact that we do not possess
fuzzy hardware. Therefore, the coding of image data (fuzzification) and decoding of the
results (defuzzification) are steps that make possible to process images with fuzzy
techniques. The main power of fuzzy image processing is in the middle step (membership
modification).
Motivation behind Fuzzy Image Processing
There are many reasons to do this. The most important of them are follows:
Fuzzy is powerful tool to knowledge representation and process human

knowledge in form of fuzzy if then rules.
Fuzzy techniques can manage the ambiguity efficiently and vagueness (an image
can be represented as a fuzzy set).
General observations about the fuzzy techniques are:
Fuzzy logic is flexible. With any given system, it's easy to manage it or layer more
functionality on top of it without starting again from scratch.
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Fuzzy logic is conceptually easy to understand. The mathematical concepts behind

fuzzy reasoning are very simple.
Fuzzy logic is tolerant of imprecise data. Everything is imprecise if we look

closely enough, but more than that, most things are imprecise even on careful
inspection.
Fuzzy logic can be blended with conventional control techniques. Fuzzy systems
don't necessarily replace conventional control methods. In many cases fuzzy
systems augment them and simplify their implementation.
Fuzzy logic can model nonlinear functions of arbitrary complexity and it can be
built on top of the experience of experts.
1.4 OBJECTIVE
The main objective of the thesis work is implement an algorithm based on fuzzy rule for
image compression. In literature survey the existed methods are able to compression
images. But depending on application they designed the compression method is different
for different type of images.
The objective of the thesis work contains the following steps as described below:
To study the concept of compression and fuzzy logic set.
To study of various existed image compression techniques by using Verilog.
Study of existed fuzzy techniques for image compression.
To propose a Fuzzy algorithm to compression/reconstruction of image using

DWT-IDWT by reducing the intensity, power, noise, delay and area of image.
Implement this on FPGA and display the image in monitor.
1.5 METHODOLOGY
The step-by-step methodology to be followed for image compression using fuzzy theory:
Study and analyze various Fuzzy techniques and image compression techniques.
Based on above analysis algorithm is developed for image compression by using

Verilog.
Results achieved after the execution of program are compared with the earlier
outputs.
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1.6 ORGANIZATION OF THE REPORT

This report contains five chapters. Brief information of each chapter is presented below.
Chapter 1: This chapter describes about the background of this work, importance of
image compression, motivation.
Chapter 2: Literature survey reveals the details about the survey conducted before
obtaining the objectives for the project.
Chapter 3: This chapter describes the design and FPGA implementation of image
compression based fuzzy logic.
Chapter 4: This chapter gives the overview of results that are obtained. It also describes
bit file needed and dumped on FPGA to display the output.
Chapter 5: This chapter gives brief description of outcome of the project and future
enhancement that can be incorporated.
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CHAPTER 2
LITERATURE SURVEY
There is a lot work has been done in field of image compression . In this section, work
done in area of image compression and fuzzy logic is focus has been made on image
quality .
Yogitha S.K et al., 2013 has proposed the effects of quantization matrices on Discrete
cosine transform and Fuzzy logic using different resolution of an image and tells about
how different quantization matrices effects DCT and fuzzy intensification algorithm for
different resolution. The PSNR value of images in DCT varies for different quantization
matrices but when combine Fuzzy logic and DCT PSNR does not varies and get
enhanced, high quality and compressed image. Such an algorithm has been proven (by
experiments) to significantly increase the computational efficiency in image processing
algorithms applied to a JPEG image.
Mahesh Goparaju et al., 2013 implements transform using filter banks. For the design,
based on the constraints the area, power and timing performance were obtained. Based on
the application and the constraints imposed, the appropriate architecture can be chosen.
For the Daubechies 2, the poly-phase architecture, with modified DA technique was
implemented. The latency of the proposed architecture is 44 clock cycles and throughput
is 4 clock cycles, and hence is twice faster than the reference design. It is seen that, in
applications, which require low area, power consumption, and high throughput, e.g., realtime applications, the poly-phase with DA architecture is more suitable. The biorthogonal wavelets, with different number of coefficients in the low pass and high pass
filters, increase the number of operations and the complexity of the design, but they have
better SNR than the orthogonal filters.
V. Alarcon-Aquino et al., 2013 analyzed image was divided into little sub-images and
each one was decomposed in a vector following a Hilbert fractal curve. The wavelet
transform was applied to each vector and some of the high frequency components were
suppressed based on some threshold criteria. Different levels of wavelet decomposition
and wavelet mother functions were assessed. The Huffman coding algorithm was then
applied in order to reduce image weight. Simulation results have revealed that high
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compression ratios were obtained with the mean and the standard deviation thresholding
algorithms at different levels of wavelet decomposition.
G.Bheemeswara Rao et al., 2012 proposed a new technique called lifting DWT and is
implemented on Spartan 3e FPGA EDK. This uses less silicon area compared with
previous technique for the compression of 64X64 sized images. The silicon area used in
this new approach for the compression of 64X64 images is approximately same as that of
the silicon area used by the previous technique for the compression of 32X32 sized
images.
M. Mozammel Hoque Chowdhury et al., 2012 suggested a new image compression
scheme with pruning proposal based on discrete wavelet transformation (DWT). The
effectiveness of the algorithm has been justified over some real images, and the
performance of the algorithm has been compared with other common compression
standards. The algorithm has been implemented using Visual C++ and tested on a
Pentium Core 2 Duo 2.1 GHz PC with 1 GB RAM. Experimental results demonstrate that
the proposed technique provides sufficient high compression ratios compared to other
compression techniques.
Nagoor Gani et al., 2012 describe the fuzzy set theory has been applied in many fields
such as operation research, control theory and management sciences etc. The fuzzy
numbers and fuzzy values are widely used in engineering applications because of their
suitability for representing uncertain information. In standard fuzzy arithmetic operations
we have some problem in subtraction and division operations. A new operation on
Triangular Fuzzy Numbers is defined, where the method of subtraction and division has
been modified. These modified operators yield the exact inverse of the addition and
multiplication operators.
R. Lovassy et al., 2011 analyzed two types of neural networks, namely the traditional
tansig based neural networks and the multilayer perceptrons based on fuzzy flip-flops
(F3NN) trained by the Bacterial Memetic Algorithm with Modified Operator Execution
Order (BMAM) are tested and compared on their robustness to test functions outliers. The
robust design of the F3NN is presented, and the best suitable fuzzy neuron type is
emphasized. As our major motivation in these investigations was to construct a
technology for the creation of real hardware MLPs and for this reason the fuzzy flip-flop
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based F3NNs obviously offered much simpler and cheaper possibility for hardware
implementation compared to a relatively complicated tansig type neural network.
R.-E. Precup et al., 2011 analyzed that the capability of fuzzy logic based inference
systems to describe complex control strategies by means of linguistic rules, avoiding the
need for mathematical models and providing good results in terms of adaptability and
robustness, has motivated an increasing interest for the use of this technique to implement
intelligent control systems in applications related to industrial control, robotics, and
consumer electronics.
Sugreev Kaur et al., 2010 presented a high speed and area efficient DWT processor based
design for Image Compression applications. In this proposed design, pipelined partially
serial architecture has been used to enhance the speed along with optimal utilization and
resources available on target FPGA. The proposed model has been designed and
simulated using Simulink and System Generator blocks, synthesized with Xilinx
Synthesis tool (XST) and implemented on Spartan 2 and 3 based XC2S100-5tq144 and
XC3S500E-4fg320 target device. The results show that proposed design can operate at
maximum frequency 231 MHz in case of Spartan 3 by consuming power of 117mW at 28
degree/c junction temperature. The result comparison has shown an improvement of 15%
in speed.
Dr. S. Abdul Khader Jilani et al., 2009 describes the transport of images across
communication paths is an expensive process. The limitation in allocated bandwidth
leads to slower communication. To exchange the rate of transmission in the limited
bandwidth the Image data must be compressed before transmission. JPEG2000 image
compression system follows huffman coding for image compression. Embedded zero tree
wavelet (EZW) coding exploits the multi-resolution properties of the wavelet transform
when compared to existing wavelet transforms. Artificial Neural Network has been
applied to many problems in image processing and has demonstrated their superiority
over classical methods when dealing with noisy or incomplete data for image
compression applications. A fuzzy optimization design based on neural networks is
presented as a new method of image processing. The combination system adopts a new
fuzzy neuron network (FNN) which can appropriately adjust input and output values, and
increase robustness, stability and working speed of the network by achieving high
compression ratio.
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Thowhida Akther et al., 2009 analyzed a computer implementation to evaluate the
arithmetic operations on two fuzzy numbers with linear membership functions has been
developed. The fuzzy arithmetic approached by the interval arithmetic is used here. Using
these method four basic arithmetic operations between any two triangular fuzzy numbers
(TFNs) can be evaluated without complexity.
Shang Gao et al., 2009 concentrated on fuzzy number is simply an ordinary number
whose precise value is somewhat uncertain. Fuzzy numbers are used in statistics,
computer programming, engineering, and experimental science. The arithmetic operators
on fuzzy numbers are basic content in fuzzy mathematics. Operation of fuzzy number can
be generalized from that of crisp interval. The operations of interval are discussed.
Multiplication operation on fuzzy numbers is defined by the extension principle. Based
on extension principle, nonlinear programming method, analytical method, computer
drawing method and computer simulation method are used for solving multiplication
operation of two fuzzy numbers. The nonlinear programming method is a precise method
also, but it only gets a membership value as given number and it is a difficult problem for
solving nonlinear programming. The analytical method is most precise, but it is hard to cuts interval when the membership function is complicated. The computer drawing
method is simple, but it need calculate the -cuts interval. The computer simulation
method is the most simple, and it has wide applicability, but the membership function is
rough.
Nasri Sulaiman et al., 2009 implement real-time applications using FPGA, to make use of
FPGA technology features (small device size, high speed, low coast, and short time to
market). A control algorithm, when implemented in an FPGA, can have a very short
execution time due to the high degree of parallelism of its architecture. At the same time,
the constraints imposed by the power electronic components imply a sampling period that
is, for many applications, much higher than the execution time. The resulting wasted
time could be advantageously employed. Another perspective on FPGA design is to
propose a prototyping development system of a fully integrated controller from VLSI
technology and SOC design that can include digital control and its analog interface
(sensors, ADC, power drivers, etc.).
S. S-Solano et al., 2007 described a design strategy which eases the implementation of
embedded fuzzy controllers as systems on programmable chips (SOPC). The
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development of the controllers is carried out by means of a reconfigurable platform based
on field-programmable gate arrays (FPGAs). This platform combines specific hardware
to implement fuzzy inference modules with a general-purpose processor, thus allowing
the realization of hybrid hardware/software solutions. As happens to the components of
the processing system, the specific fuzzy elements are conceived as configurable
Intellectual Property (IP) modules in order to accelerate the controller design cycle.
Xixin Cao et al., 2006 have proposed an efficient and simple architecture for 9/7 Discrete
Wavelet Transform based on Distributed Arithmetic. To derive the proposed architecture,
they considered the periodicity and symmetry of DWT to optimize the performance and
reduced the computational redundancy. The inner product of coefficient matrix of DWT
was distributed over the input by careful analysis of input, output and coefficient word
lengths. In the coefficient matrix, linear maps were used to assign the necessary
computation to processing elements in space domain. Moreover, the proposed
architecture has regular data flow, and low control complexity. The result was low
hardware complexity DWT processors for 9/7 transforms, which allows two times faster
clock than the direct implementation. This design was very suitable for image
compression systems, e.g., JPEG2000 and MPEG4.
C. T. Huang et al., 2005 have presented a detailed analysis of very large scale integration
(VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete
wavelet transform (DWT) in many aspects, and three related architectures were proposed
as well. The 1-D DWT and inverse DWT (IDWT) architectures were classified into three
categories: convolution-based, lifting based, and B-spline-based. They were discussed in
terms of hardware complexity, critical path, and registers. As for the 2-D DWT, the large
amount of the frame memory access and the die area occupied by the embedded internal
buffer became the most critical issues. The 2-D DWT architectures were categorized and
analyzed by different external memory scan methods. The implementation issues of the
internal buffer were also discussed, and some real-life experiments were given to show
that the area and power for the internal buffer were highly related to memory technology
and working frequency, instead of the required memory size only. Besides the analysis,
the B-spline-based IDWT architecture and the overlapped stripe-based scan method were
also proposed. Last, they proposed a flexible and efficient architecture for a one-level 2-D
DWT that exploits many advantages of the presented analysis.
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K. Hirota et al., 2004 introduced a fuzzy relational equation (ICF) regards an original
image as a fuzzy relation by embedding the brightness level into [0, 1]. The
compression/reconstruction of ICF corresponds to the composition/solving inverse
problem formulated on fuzzy relational equations. Optimizations of ICF can be
consequently deduced based on fuzzy relational calculus, i.e., computation time
reduction/improvement of reconstructed image quality are correspond to a fast solving
method/finding an approximate solution of fuzzy relational equations, respectively.
Through the experiments using test images extracted from Standard Image Database
(SIDBA), the effectiveness of the ICF and its optimizations are shown.
R. Lovassy et a.,. presented a comparison of the performance of several type neural
networks based on fuzzy J-K and also fuzzy D flip-flops (the latter derived from the
former type). The behavior of algebraic, Yager, Dombi and Hamacher type fuzzy flipflop neural networks are presented. The best fitting t-norm and corresponding fuzzy flipflop type will be presented in terms of function approximation capability.
Thomas Hollstein et al., 1996 describe that the Fuzzy systems implemented in hardware
can be operated with much higher performance than software implementations on
standard microcontrollers. Three types of fuzzy systems and related hardware
architectures are discussed and presented two computer-aided design (CAD) packages for
automatic hardware synthesis of standard fuzzy controllers.
L. Huang., presented a new image compression algorithm called IWF, based on a wavelet
transform and fuzzy technique. The key idea is to use wavelet transform to decompose
the image, and apply Fuzzy Logic to optimize the calculation of wavelet coefficients. The
main advantage of the IWF algorithm is that it is computationally inexpensive as
compared to other algorithms when dealing with coefficients that do not reflect much
image information.
As per the above literature survey, the limitation in allocated bandwidth leads to slower
communication, Pixel error at edge of decompressed/reconstructed image, noises and
delay, so to overcome these limitations the Fuzzy algorithm has been proposed and
Implemented.
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2.1 MOTIVATION
The main motivation behind the approach is to produce immediate access to
object/feature of interest in a high quality decoded image which could be useful on smart
devices, for analysis purpose, as well as for multimedia content based description
standards. The recent improvement in FPGA technologies has led to important advances
in programmable logic devices, which allow the implementation of a complete systemon-a programmable chip (SOPC). In addition to the classical VHDL-based design flow,
FPGA manufactures have recently developed different design tools, such as System
Generator from Xilinx (XSG), to ease the implementation of digital signal processing
(DSP) algorithms on FPGAs. Hardware implementation of fuzzy image processing is
currently demanded by multimedia applications.
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CHAPTER 3
DESIGN AND IMPLEMENTATION

Among the methods for two-dimensional DWT, the indirect method based on rowcolumn decomposition is the best adapted to a hardware implementation. Fuzzy
Algorithm was proposed and has since used widely in VLSI implementations of DSP
architectures. Most of these applications are computation intensive with multiplication
and/or addition being the predominant operation. The main advantage of Fuzzy approach
is that it speeds up the multiply process by pre-computing all the possible medium values
and storing these values in a ROM. The input data can then be used to directly address the
memory and the result. It has been proposed an efficient 2D DWT architecture based on
Fuzzy Technique. This architecture uses both ROM and RAM in the proposed
architecture. Fuzzy and row-column decomposition reduce the hardware amount and
enhance the speed performance.
Figure 3.1: Proposed block diagram
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Figure 3.2: Flow of Design
3.1
IMAGE
An image (from Latin imago) is an artifact, for example a two-dimensional picture that
has a similar appearance to some subject usually a physical object or a person. Images may
be two-dimensional, such as a photograph, screen display, and as well as a three-dimensional,
such as a statue. They may be captured by optical devicessuch as cameras, mirrors, lenses,
telescopes, microscopes, etc. and natural objects and phenomena, such as the human eye or
water surfaces.
Image file sizeexpressed as the number of bytesincreases with the number of

pixels composing an image, and the color depth of the pixels. Greater the number of rows
and columns, greater the image resolution, and larger the file size. Also, each pixel of an
image increases in size when its color depth increasesan 8-bit pixel (1 byte) stores 256
colors, a 24-bit pixel (3 bytes) stores 16 million colors, the latter known as true color.
From the multimedia file block reads image and imports them into a MATLAB. Image
consists of pixels that are arranged in two dimensional matrixes, each pixel represents the
digital equivalent of image intensity.
Page 23
Figure 3.3: Resize the image (100x100).

Many of the toolbox functions are MATLAB M-files, a series of MATLAB statements
that implement specialized image processing algorithms. It can view the MATLAB code
for these functions using the statement, type function_name. It can extend the
capabilities of Image Processing Toolbox by writing your own M-files, or by using the
toolbox in combination with other toolboxes, such as Signal Processing Toolbox and
Wavelet Toolbox.
Read and Display an Image
First, clear the MATLAB workspace of any variables and close open figure windows.
Close all to read an image, use the imread command. The example reads one of the
sample images included with Image Processing Toolbox, lena.jpg, and stores it in an
array named I. I = imread (' penguins.jpg '); Now display the image. The toolbox
includes two image display functions: imshow and imtool. Imshow is the toolbox's
fundamental image display function. Imtool starts the Image Tool which presents an
integrated environment for displaying images and performing some common image
processing tasks. The Image Tool provides all the image display capabilities of imshow
but also provides access to several other tools for navigating and exploring images, such
as scroll bars, the Pixel Region tool, Image Information tool, and the Contrast Adjustment
tool.
Image Appearance in the Workspace
To see how the imread function stores the image data in the workspace, check the
Workspace browser in the MATLAB desktop. The Workspace browser displays
information about all the variables you create during a MATLAB session. The imread
function returned the image data in the variable I, which is a 100-by-100 element array of
uint8 data. MATLAB can store images as uint8, uint16, or double arrays.
Page 24

Conversion of the image into file .COE using MATLAB.
a. Read the image and resize to 100x100.
b. Convert decimal to 24-bit hexadecimal.
3.2
XILINX CORE GENERATOR
The Xilinx CORE Generator System provides you with a catalog of ready-made functions
ranging in complexity from simple arithmetic operators such as adders, accumulators and
multipliers, to system level building blocks including filters, transforms and memories.
The CORE Generator System can customize a generic functional building block such as a
FIR filter or a multiplier to meet the needs of your application and simultaneously deliver
high levels of performance and area efficiency.
Block Memory Generator
Block Memory Generator core is an advanced memory constructor that generates area
and performance-optimized memories using embedded block RAM resources in Xilinx
FPGAs. Available through the CORE Generator software, users can quickly create
optimized memories to leverage the performance and features of block RAMs in Xilinx
FPGAs.
The Block Memory Generator core uses embedded Block Memory primitives in Xilinx
FPGAs to extend the functionality and capability of a single primitive to memories of
arbitrary widths and depths. Sophisticated algorithms within the Block Memory
Generator core produce optimized solutions to provide convenient access to memories for
a wide range of configurations. The Block Memory Generator has two fully independent
ports that access a shared memory space. Both A and B ports have a write and a read
interface.
In Virtex-6, Virtex-5 and Virtex-4 FPGA architectures, all four interfaces can be uniquely
configured, each with a different data width. When not using all four interfaces, the user
can select a simplified memory configuration (for example, a Single-Port Memory or
Simple Dual-Port Memory), allowing the core to more efficiently use available resources.
Page 25
Memory Types
The Block Memory Generator core uses embedded block RAM to generate five types of
memories:
I.
II.
Single-port RAM
Simple Dual-port RAM
III.
True Dual-port RAM
IV.
Single-port ROM
V.
Dual-port ROM
For dual-port memories, each port operates independently. Operating mode, clock
frequency, optional output registers, and optional pins are selectable per port. For Simple
Dual-port RAM, the operating modes are not selectable; they are fixed as READ_FIRST.
Configurable Width and Depth
The Block Memory Generator can generate memory structures from 1 to 1152 bits wide,
and at least two locations deep. The maximum depth of the memory is limited only by the
number of block RAM primitives in the target device.
Selectable Operating Mode per Port
The Block Memory Generator supports the following block RAM primitive operating
modes: WRITE FIRST, READ FIRST, and NO CHANGE. Each port may be assigned an
operating mode.
Memory Initialization
The memory contents can be optionally initialized using a memory coefficient (COE) file
or by using the default data option. A COE file can define the initial contents of each
individual memory location, while the default data option defines the initial content of all
locations.
Simulation Models
The Block Memory Generator core provides behavioral and structural simulation models
in VHDL and Verilog for both simple and precise modeling of memory behaviors, for
example, debugging, probing the contents of the memory, and collision detection.
Page 26
Functional Description
The Block Memory Generator is used to build custom memory modules from block RAM
primitives in Xilinx FPGAs. The core implements an optimal memory by arranging block
RAM primitives based on user selections, automating the process of primitive
instantiation and concatenation. Using the CORE Generator Graphical User Interface
(GUI), users can configure the core and rapidly generate a highly optimized custom
memory solution.
Intellectual Property (IP) RAM:
Load the converted input pixel values into RAM.
Figure 3.4: Snapshot of type of memory select
3.3
FUZZY INTENSIFICATION OPERATOR
Fuzzification operation raises the membership grade of those elements within the 0.5
points and reduces the membership grade of those elements outside the crossover (0.5)
point. Hence, intensification amplifies the signal within the bandwidth while reducing the
`noise'.
If TALL=-.125/5+0.5/6+0.875/6.5+1/7+1/7.5+1/8 then
INT(TALL) = 0.031/5+0.5/6+0.969/6.5+1/7+1/7.5+1/8.
Page 27
Figure 3.5: Intensification set operator

Steps are explained as below
1. First read the input image, here images of resolution (100x100) is used for image
Processing.
2. Fuzzification is described by
()
The value of a is calculated by

*(
) (
)+
The values of the second parameter b are obtained from B (

a.Ithd+b=0.5
): B (
)=0.5
b=0.5-a.Ithd
Im=0, IM=255, Ithd=128 this value is considered by seeing below figure 3.6.
Figure 3.6: Fuzzy intensification operator

Page 28

3. Defuzzification is given by B(l)
()
3.4
( ( ))
* (
DISCRETE WAVELET TRANSFORM (DWT)
Fuzzified data output is given to DWT for compression purposes.

The Wavelet Series is just a sampled version of continuous wavelet transform and its
computation may consume significant amount of time and resources, depending on the
resolution required. The Discrete Wavelet Transform (DWT), which is based on sub-band
coding, is found to yield a fast computation of Wavelet Transform. It is easy to
implement and reduces the computation time and resources required.
In the case of DWT, a time-scale representation of the digital signal is obtained using
digital filtering techniques. The signal to be analyzed is passed through filters with
different cutoff frequencies at different scales.
DWT processor transforms the spatial domain pixels into frequency domain information
that are represented in multiple sub-bands, representing different time scale and frequency
points. Human visual system is very much sensitive to low frequency and hence, the
decomposed data available in the lower sub-band region and is selected and transmitted,
information in the higher sub-bands regions are rejected depending upon required
information content. In order to extract the low frequency and high frequency sub -bands
DWT architecture shown in figure below is used. As shown in the figure, input image
consisting rows and columns are transformed using high pass and low pass filters. A low
pass filter and a high pass filter are chosen, such that they exactly halve the frequency
range between themselves. The filter pass is called the analysis filter pair. First the low
pass filter is applied for each row of data, thereby getting the low frequency components
of the row. But since the low pass filter is a half band filter, the output data contains
frequencies only in the first half of the original frequency range. So they can be sub
sampled by two, so that the output data now contains only half the original number of
samples. Now the high pass filter is applied for the same row of data, and similarly the
high pass components are separated and placed by the side of the low pass components.
This procedure is done for all rows. Next, the filtering is done for each column of the
intermediate data. The resulting two dimensional arrays of coefficients contain four bands
Page 29

of data, each labeled as LL (low- Low), HL (high-low), LH (Low-High) and HH (HighHigh). The LL band can be decomposed once again in the same manner, thereby
producing even more sub bands. This can be done up to any level, thereby resulting in a
pyramidal decomposition as shown. The LL band at the highest level can be classified as
most important and the other detail bands can be classified as of lesser importance, with
the degree of importance decreasing from the top of the pyramid to the bands at the
bottom.
Figure 3.7: Image coding
Figure 3.8: DWT Architecture
Page 30
Figure 3.9: Dividing even and odd pixels
Multirate DSP systems are commonly used in many practical signal processing
applications that require different sampling rates. Downsampling and Upsampling are
common techniques used for sampling rate conversion in analysis and synthesis filters.
The input is filtered and downsampled by a factor of two at every stage of the DWT
algorithm. Downsampling, also known as decimation, can be easily implemented as
shown in Figure 3.11 where H(z) is the filter transfer function, x(n) is the input signal,
y(n) is the filtered output and y(n) is the signal decimated output signal. The input clock
frequency is F Hz and the output clock frequency is F/2 Hz. Figure 3.12 illustrates a
sample waveform for the output sequence after filtering y (n) and the output sequence
after decimation y(n).
Figure 3.10: Filtering and downsampling
Page 31
Figure 3.11: Example of decimation by 2
Figure 3.12: 2-level of Decomposition
3.5
INVERSE DWT
Just as a forward transform is used to separate the image data into various classes of
importance a reverse transform is used to reassemble the various classes of data into a
reconstructed image. A pair of high pass and low pass filters is used here also. Then filter
pair is called the synthesis filter pair. The filtering procedure is just the opposite. We start
from the topmost level, apply the filters column wise first and then row wise and proceed
to the next level, till we reach the first level. In this section the theoretical background and
algorithm development is discussed. The first recorded mention of what is now called a
Page 32

"wavelet" seems to be in 1909, in a thesis by Alfred Haar. An image is represented as a
two dimensional (2D) array of coefficients, each coefficient representing the brightness
level in that point. When looking from a higher perspective, it is not possible to
differentiate between coefficients as more important ones, and lesser important ones. But
thinking more intuitively, it is possible. Most natural images have smooth color
variations, with the fine details being represented as sharp edges in between the smooth
variations. Technically, the smooth variations in color can be termed as low frequency
components and the sharp variations as high frequency components. The low frequency
components (smooth variations) constitute the base of an image, and the high frequency
components (the edges which give the detail) add upon them to refine the image, thereby
giving a detailed image. Hence the averages/smooth variations are demanding more
importance than the details. In wavelet analysis, a signal can be separated into
approximations or averages and detail or coefficients. Averages are the high-scale, low
frequency components of the signal. The details are the low scale, high frequency
components. If we perform forward transform on a real digital signal, we wind up with
twice as much data as we started with. Thats why after filtering down sampling has to be
done. The inverse process is how those components can be assembled back into the
original signal without loss of information. This process is called reconstruction or
synthesis. The mathematical manipulation that affects synthesis is called the inverse
discrete wavelet transform. The original signal is reconstructed from the wavelet
coefficients. Where wavelet analysis involves filtering and down sampling, the wavelet
reconstruction process consists of up sampling and filtering. DWT outputs are computed
every clock cycle. In the computation process fuzzy arithmetic operators and fuzzy neuro
D-flip-flop has been used in order to increase the computation speed which is very
essential in compression.
Figure 3.13: Fuzzy D-flip flop

Page 33
The input signal x(n) is filtered by the analysis process using the low pass and the high
pass filters. The symbols 2 and 2 are up sampling and down sampling by a factor of
two for decimating the filter results. The inverse of the analysis process is synthesis
process. In digital signal processing there was decimation and filtering in the synthesis
process.
Figure 3.14: Block diagram of 2 dimensional Inverse DWT

The reconstruction of the original fine scale coefficients can be made from the
combination of the scaling and the wavelet coefficients at a (lower) coarser scale it is
illustrated in Figure 3.15. In 2D, the images are considered to be matrices with N rows
and M columns. Any decomposition of an image into wavelets involves a pair of
waveforms
One to represent the high frequency corresponding to the detailed part of the
image (wavelet function).
One for low frequency or smooth parts of an image (scaling function).
At every level of decomposition the horizontal data is filtered, and then the
approximation and details produced from this are filtered on columns. At every
level, four sub-images are obtained; the approximation, the vertical detail, the
horizontal detail and the diagonal detail.
Page 34
Wavelet function for 2-D DWT can be obtained by multiplying wavelet functions
((x, y)) and scaling function ((x, y)). After first level decomposition we get
four details of image those are,
Approximate details (x, y) = (x) (y)
Horizontal details (x, y) = (x) (y)
Vertical details (x, y) = (x) (y)
Diagonal details (x, y) = (x) (y)
The approximation details can then be put through a filter bank, and this is repeated until
the required level of decomposition has been reached. The filtering step is followed by a
sub-sampling operation that decreases the resolution from one transformation level to the
other. After applying the 2-D filler bank at a given level n, the detail coefficients are
output, while the whole filter bank is applied again upon the approximation image until
the desired maximum resolution is achieved. Figure 3.16(b) shows wavelet filter
decomposition. The sub-bands are labeled by using the following notations.
LLn represents the approximation image nth level of decomposition, resulting

from low-pass filtering in the vertical and horizontal both directions.
LHn represents the horizontal details at nth level of decomposition and obtained
from horizontal low-pass filtering and vertical high-pass filtering.
HLn represents the extracted vertical details/edges, at nth level of decomposition

and obtained from vertical low-pass filtering and horizontal high-pass filtering.
HHn represents the diagonal details at nth level of decomposition and obtained
from high-pass filtering in both directions.
Page 35
Figure 3.15: Illustration of 2 dimensional DWT for an image Lena
3.6
VIRTEX 2 PRO
IDWT output is De-fuzzified and load into IP RAM, Finally dumping the Verilog code
into FPGA board (virtex 2pro) and to display output in monitor.
The XUP Virtex-II Pro Development System provides an advanced hardware
platform that consists of a high performance Virtex-II Pro Platform FPGA surrounded by
a comprehensive collection of peripheral components that can be used to create a
complex system and to demonstrate the capability of the Virtex-II Pro Platform FPGA.
Page 36
Figure 3.16: XC2VP3O virtex 2 pro module

The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families are focused
on system-on-chip (SoC) designers because they include up to two embedded IBM
PowerPC cores.There are no PowerPC blocks in any Xilinx devices other than Virtex-II
Pro.Xilinx FPGAs can run a regular embedded OS (such as Linux ) and can implement
processor peripherals in programmable logic.
Xilinx's IP cores include IP for simple functions (BCD encoders, counters, etc.),
for domain specific cores (digital signal processing, FFT and FIR cores) to complex
systems (multi-gigabit networking cores, MicroBlaze soft microprocessor, and the
compact Picoblaze microcontroller). Xilinx also creates custom cores for a fee.
The ISE Design Suite is the central electronic design automation (EDA) product
family sold by Xilinx. The ISE Design Suite features include design entry and synthesis
Page 37

supporting Verilog or VHDL, place-and-route (PAR), completed verification and debug
using ChipScope Pro tools, and creation of the bit files that are used to configure the chip.
Xilinx's Embedded Developer's Kit (EDK) supports the embedded PowerPC 405 and 440
cores (in Virtex-II Pro and some Virtex-4 and -5 chips) and the Microblaze core. Xilinx's
System Generator for DSP implements DSP designs on Xilinx FPGAs. A freeware
version of its EDA software called ISE WebPACK is used with some of its non-highperformance chips. Xilinx is the only (as of 2007) FPGA vendor to distribute a native
Linux freeware synthesis tool chain.
The pixel clock needs to be at 40 MHz (which you will generate from the system clock
of 100 MHz) and the resolution will be at 100 Columns x 100 Rows. It can use the Digital
Clock Management modules (DCM) provided with the Virtex II Pro FPGA to accurate
signals. Colors can be represented using a triplet consisting of the intensities of each
fundamental color (Red, Green, Blue). The monitor expects these values to be analog, and
thus a DAC (Digital to Analog Converter) is used. Depending on the type of monitor and
video card that computer uses 16, 24, or 32 bits to encode this color information. In this
project will be using 8 bits per color component of each pixel, hence the pixel will be
total of 24 bits (8 for Red, 8 for Blue, and 8 for Green). An important fact to realize is that
the VGA monitor does not have memory and thus will not store the pixel information
being written to it. Instead, the pixels must be continuously sent to the display to achieve
a stable image. The VGA controller needs to be receiving from the memory pixels and
will be responsible for constantly sending out the pixel information. There are two signals
that are used to maintain synchronization with the monitor: horizontal and vertical sync.
These signals are active low (activated when the signal is logic 0). The timing for these
signals is defined by the standards for VGA monitors. During a horizontal sync cycle, the
pixel information is sent for all row pixels followed by the lowering of the horizontal
sync signal. The signal is used to coordinate the start of new lines. A vertical sync is
achieved by lowering the vertical sync signal. The vertical sync instructs the monitor to
return to the top of the screen (0, 0). The horizontal sync cycle that follows becomes the
first row on the screen. The controller must take the pixels and the system clock as inputs
from the FPGA, and generate the VGA output signals to drive a common VGA interface.
Page 38
Start
Start
Read the image and

resize to 100x 100
Read compressed image

pixel value
Conversion of image into

file .COE by Matlab
De-fuzzification
Load the converted .COE

file into ROM
Read the Pixel Value and

Calculate Co-efficient h (n)
using fuzzification
Convolution based
DWT
Applying
IDWT
Load the decompressed

pixels value into RAM
Dump the Program into

FPGA virtex 2 pro kit
Y (n) = x (n) * h (n)

Displays both original
image and reconstructed
image
Compressed image
Figure 3.17: Flow of compression and decompression process
Page 39
CHAPTER 4
RESULT AND DISSCUSSION

ISIM is the tool that integrates with Xilinx ISE to provide simulation and testing
for the data processed by Matlab in this project. Two kinds of simulation are used for
testing a design they are functional simulation and timing simulation. Functional
simulation is used to make sure that the logic of a design is correct. Timing simulation
also takes into account the timing properties of the logic and the FPGA, so we can see
how long signals take to propagate and make sure that our design will behave as
expected when it is downloaded onto the FPGA.
Figure 4.1: Simulate in ISIM

Comparison of different FPGAs
When examining the specifications of an FPGA chip, they are often divided into
configurable logic blocks like slices or logic cells, fixed function logic such as
multipliers, and memory resources like embedded block RAM. There are many other
FPGA chip components, but these are typically the most important when selecting and
comparing FPGAs for a particular application.
Page 40

Table 4.1: FPGA Resource Specifications for Various Families
Virtex-II
Virtex-II
Spartan-3
Spartan-3
Virtex-5
Virtex-5
Virtex-5
Virtex-5
1000
3000
1000
2000
LX30
LX50
LX85
LX110
Gates
1 million
3 million
1 million
2 million
-----
-----
-----
-----
Flip-Flops
10,240
28,672
15,360
40,960
19,200
28,800
51,840
69,120
LUTs
10,240
28,672
15,360
40,960
19,200
28,800
51,840
69,120
Multipliers
40
96
24
40
32
48
48
64
Block RAM
(kb)
720
1,728
432
720
1,152
1,728
3,456
4,608
Table 4.1 shows resource specifications used to compare FPGA chips within
various Xilinx families. The number of gates has traditionally been a way to compare the
size of FPGA chips to ASIC technology, but it does not truly describe the number of
individual components inside an FPGA.
Synthesis
Xilinx ISE Foundation Software takes the input of the circuit in the schematic
editor, simulate the timing behavior of the circuit, compile it for a Virtex-2 FPGA, and
test the design on a prototyping board. The ISE software includes Xilinx Synthesis
Technology (XST), which synthesizes VHDL, Verilog, or mixed language designs to
create Xilinx-specific Netlist files known as NGC files
.
Figure 4.2: Synthesizing blocks
Page 41
Configure target device:

Target Device Properties
The following properties are available for the Configure Target Device process for
a CPLD or FPGA device.

iMPACT Project File
The iMPACT Project File (IPF) contains information from a previous session of
iMPACT. If you specify an IPF file in this property and run the Configure Target Device
process, the target device will be configured according to the settings in the specified IPF
file. If Default is specified here, the target device will be configured according to the
settings in the default IPF file, <ISE_image_inte>.ipf.
Port to be used (Advanced): Here we use USB, specifies the port you would like
to use for configuration. Auto-default causes the software to search every port for a
connection, automatically detect an available cable, and connect to it. Run Generate
Target PROM/ACE File If selected, the Configure Target Device process will
automatically run the Generate Target PROM/ACE File process to generate a PROM or
ACE file before configuring the target device. The file will be generated using the
information from the .ipf file specified in the iMPACT Project File property. When
Automatically Generate Target PROM/ACE File is set to True (checkbox is checked), the
PROM or ACE file is generated in the background before the target device is configured.
This is useful for quick PROM or System ACE file regeneration when a bitstream has
changed.
Figure 4.3: ISE synthesis for prototype implementation

Page 42
Design summary
Design entry is the first step in the ISE design flow. During design entry, you create your
source files based on your design objectives. You can create your top-level design file
using a Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or
using a schematic. You specify your top-level module type when you create your project
as described in Creating a Project.
You can use multiple formats for the lower-level source files in your design. Different
source types are available, depending on your project properties (top-level module type,
device type, synthesis tool, and language). You can create these source files in Project
Navigator, as described in Creating a Source File. Some source types launch additional
tools to help you create the file, as described in Source File Types.
Table 4.3.1: Design summary of proposed method
Page 43
Timing constraints
The ISE software allows you to enter timing constraints that describe the timing
performance requirements of the design. Providing a concise set of constraints achieves
the following:
Allows the software to create a design that meets your requirements.
Allows you to compare the constraints to the performance of the resulting design,
using the timing reports output by the ISE software.
By analyzing the timing reports, you can identify the paths in the design that may require
coding modifications, placement directives, or additional constraints to achieve timing
closure. Increases the performance of ISE software by reducing the memory and runtime
requirement.
Table 4.3.2: Timing Constraint of proposed design
Page 44
Clock report
This report contains information on the resource utilization of each clock region and lists
any clock conflicts between global clock buffers in a clock region.
Table 4.3.3: Clock Report of implemented design
Data in X-power analyzer

Table 4.3.4: X-power Analyzer
Page 45
4.1 RTL SCHEMATIC

The synthesized design can be viewed as a schematic in the register transfer level
(RTL) viewer. This view displays gates and elements independently of the targeted Xilinx
device. The schematic shows a representation of the pre-optimized design in terms of
generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, which
are independent of the targeted Xilinx device. Viewing this schematic may help you
discover design issues early in the design process.
Figure 4.4: RTL Schematic of fuzzification and de-fuzzification
Figure 4.5: RTL Schematic of DWT

Page 46
Figure 4.6: RTL Schematic of IDWT
Figure 4.7: RTL Schematic of DWT and IDWT
Page 47
4.2 DISPLAY OUTPUT
Figure 4.8: Original image and reconstructed image

In any of the image compression technique, the quality of decompressed or
reconstructed image will be less because of pixel error at edges and noise in the
decompressed image. To overcome this problem, the fuzzy algorithm has been proposed
and combined with image compression based DWT-IDWT technique. In 2-level 8 subband decomposition of image, one of the sub-band's intensity will be low, that is selected
or chosen, de-fuzzified and applying IDWT to get improved quality of decompressed
image in-terms of reduced pixel error at edges and noise. The original image and
reconstructed image are compared with respect to contrast and brightness. This have been
discussed briefly in this thesis and implemented. Results achieved was according to the
main aim reduction in the pixel errors, which indent to reduce in size without any change
in the appearance of the original image from resulted image that human eye cannot easily
recognizable.
Page 48
CONCLUSION AND FUTURE SCOPE

The developed algorithm is found very efficient for full color image compression.
During the analysis it is found that, developed algorithm provides higher compression
ratio as compare to normal discrete wavelet transform. In addition to this fuzzyfied
discrete wavelet transform based developed technique is also able to keep error between
input image and reconstructed image in allowable range, though it is generating slightly
higher error but at the same time the compression ratio is much higher than available
Normal DWT technique. The advantage of the developed algorithm is, Fuzzyfication
performed before using DWT because normal DWT cannot able to handle imperfections
presented in the input images. An image compression algorithm was simulated using
Verilog to comprehend the process of image compression. The relative area and speed
efficiencies of Fuzzy turn out to be good on hardware implementation on FPGA. An
implementation process included fuzzy arithmetic operators which make the computation
quite faster and fuzzy helps to enhance the image better way in the presence of noise. The
reconstructed image has got better edges in this design compared to the previous work. In
the implementation results it is clear that Fuzzy logic based architectures have an area,
speed and simplicity advantage over any other method based on implementations.
In future modification of the algorithm can produce the better result for the image.
Neruo-fuzzy techniques can be used to enhance the output image. The need for better
compression will be increased.
Page 49
REFERENCES
[1]. Yogitha S.K and Savitri Raju, DCT and Fuzzy based Analysis of Quantization
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Final Image Compression Based Fuzzy

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Design and FPGA Implementation of Image Compression based Fuzzy Technique

Design and FPGA Implementation of Image Compression based Fuzzy Technique

1.1 DIGITAL IMAGE PROCESSING

Figure 1.1: Digital image

Design and FPGA Implementation of Image Compression based Fuzzy Technique

1.2 IMAGE COMPRESSION

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Figure 1.3: Image compression system

Design and FPGA Implementation of Image Compression based Fuzzy Technique

It reduces the transmission errors since fewer bits are transferred.

It also provides a level of security against illicit monitoring.

1.2.1 Lossy Compression Techniques

Figure 1.4: Lossy image compression

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Signal - to noise ratio

Speed of encoding and decoding.

Lossy compression techniques includes following schemes:

Block Truncation Coding

1.2.2 Lossless Compression Techniques

Run length encoding

1.3 FUZZY DOMAIN

Design and FPGA Implementation of Image Compression based Fuzzy Technique

( ) is a membership function for a fuzzy set. Examples of membership

Trapezoidal Membership Function: Trapezoidal membership function is defined as a

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Gaussian Membership Function: Gaussian Membership Function is defined as following

Where m = mean, and is the standard deviation.

Figure 1.5: Examples of Membership Function

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Figure 1.6: Membership Function of the Term Set age.

Where A and B are linguistic values defined by fuzzy sets. x

antecedent or premise, while y is B is called the consequence or

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique

The qualified consequents are aggregated to produce crisp output according to

e. Rules of fuzzy reasoning:

Figure 1.7: Rules of Fuzzy Reasoning

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Figure 1.8: Fuzzy Inference System

Figure 1.9: Membership Function Modification

Fuzzy Inference Engine: Fuzzy Inference engine performs the inference

Defuzzification: This conversion of fuzzy set to single crisp value is called

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Figure 1.10: Fuzzy Image Processing

Fuzzy is powerful tool to knowledge representation and process human

General observations about the fuzzy techniques are:

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique

Fuzzy logic is conceptually easy to understand. The mathematical concepts behind

Fuzzy logic is tolerant of imprecise data. Everything is imprecise if we look

To study the concept of compression and fuzzy logic set.

To study of various existed image compression techniques by using Verilog.

Study of existed fuzzy techniques for image compression.

To propose a Fuzzy algorithm to compression/reconstruction of image using

Based on above analysis algorithm is developed for image compression by using

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique

1.6 ORGANIZATION OF THE REPORT

DEPT ECE SJBIT BANGALORE

Design and FPGA Implementation of Image Compression based Fuzzy Technique