MITSUBISHI ELECTRIC CORPORATION

Application Note

Prep.
Apr.

Wang, M.Sakai, S.Kou, F.Tametani

M.Fukunaga

Rev.

03-1/24

DIP-IPM

Ver.3

APPLICATION NOTE
MITSUBISHI ELECTRIC CORPORATION
POWER SEMICONDUCTOR
DEVICE DIVISION

DIP-IPM

DPH2588eB
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MITSUBISHI ELECTRIC CORPORATION

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Table of Contents
Chapter 1 DIP-IPM Product Outlines.........4
1.1 Product Line-up........4
1.2 Applications..........4
1.3 Functions and Features.............4
1.3.1 Function Outlines.............4
1.3.2 Product Features..........5

Chapter 2 Electrical Characteristics..........6

2.1 Maximum Ratings...........6
2.2 Electric Characteristics..........7
2.2.1 Thermal Resistance........7
2.2.2 Static and Switching Characteristics............7
2.2.3 Control (Protection) Characteristics.........9
2.3 Recommended Operation Conditions.........9

Chapter 3 Package Outline.....10

3.1 Package Outline Drawing of DIP-IPM....10
3.2 Package Outline Drawing of Mini DIP-IPM...11
3.3 Isolation......12
3.4 Laser Marking ......12
3.5 Input / Output Terminals Description.........13
3.5.1 Terminal Arrangement..........13
3.5.2 Detailed Input / Output Terminal Description.....15
3.5.3 Description of Protective Functions........16
3.5.4 Operation Sequence ........16
3.5.5 Installation Guidelines (Flatness / Mounting Strength / Screw Type /Grease) ...16

Chapter 4 Application System ......18

4.1 System Connection Diagram...18
4.2 Input circuit.......19
4.2.1 Structure of Control Input Terminals and Application Examples.......19
4.2.2 Input Signal Voltage Rating.........19
4.2.3 Minimum Rating of Control Input Pulse Width......20
4.3 Single Supply Drive Scheme...........20
4.3.1 Initial Charging...........20
4.3.2 Charging and Discharging of the Bootstrap Capacitor During Inverter Operation...21
4.3.3 Control Circuit Current-Frequency Characteristics...24
4.4 Interface Circuit Examples and Guidelines...26
4.4.1 Example of Direct Input Interface.......26
4.4.2 Example of Interface Circuit with Fast Opto-Coupler.. ...27
4.4.3 Snubber Circuit......28
4.4.4 Parallel Connection..........28
4.4.5 Input Signal Connection.......29
4.4.6 Recommended Wiring of Shunt Resistor......29
4.5 Short Circuit Protective Function........30
4.5.1 Timing Charts of Short Circuit Protection......30
4.5.2 Selecting Current Sensing Shunt Resistance....31

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4.5.3 Filter Circuit Setting (RC Time Constant) for Short-circuit Protection Operation....32
4.5.4 SOA of the DIP-IPM (short-circuit operation and switching operation).34
4.5.5 Repetition of Short Circuit Protection.....35
4.6 Fault output Circuit.......36
4.7 Guidelines for Control Supply.........37
4.7.1 Timing Charts of Under-Voltage Protection....37
4.7.2 Other Guidelines........38
4.8 Power Loss and Thermal Dissipation Design......39
4.8.1 Power Loss Calculation (Example) ........39
4.8.2 Temperature Rise Considerations and Calculation Example......41
4.9 Noise Withstand Capability ............42
4.9.1 Evaluation Circuits.........42
4.9.2 Countermeasures and Precautions .....42
4.9.3 Surge Withstand Capability....43

Chapter 5 Additional Guidelines....44

5.1 Packaging Specification......44
5.2 Attention for Handling..........45

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CHAPTER 1

DIP-IPM PRODUCT OUTLINES

1.1 Product Line-up

Type Name
PS21562
PS21563
PS21564
PS21865(-A)
PS21867(-A)
PS21869(-A)

Table 1. DIP-IPM Ver.3 Product Line-up

IGBT Rating (IC /VCES)
Motor Rating
Isolation
5A / 600V
0.2 kW / 220 VAC
10A / 600V
0.4 kW / 220VAC
15A / 600V
0.75 kW / 220 VAC
Viso = 2500Vrms
20A / 600V
1.5 kW / 220 VAC
(Sinusoidal, 1min)
30A / 600V
2.2 kW / 220 VAC
50A / 600V
3.7 kW / 220 VAC

Package
Mini DIP-IPM

DIP-IPM

Note: (1) The motor ratings show general motor capacity of general-purpose inverter for industrial application.
The available motor rating according to application conditions may be different from the above one.
(2) Type name suffixed by (-A) of DIP-IPM(PS21865/867/869) indicates the long terminal with 16mm-length.

1.2 Applications
Motor drive for household electric appliances, such as air conditioners, washing machines, refrigerators, and low
power industrial applications as well.

1.3 Functions and Features

1.2.1 Function outlines
Figure 1(a) and (b) show the photograph and the internal structure block diagram of DIP-IPM and mini DIP-IPM
respectively. The DIP-IPM is the ultra-compact intelligent power module, which integrates power parts, driver and
protection circuit for AC100-220V class low power motor inverter control into a dual-in-line transfer molded package.
DIP-IPM over 20A class has built-in heat sink to reduce the thermal resistance, as shown in Fig. 1(b).

IGBT/FWDi

Control IC
(HVIC,LVIC)

DIP-IPM
Lead frame

Heat sink
mold resin

IGBT/FWDi

Control IC
(HVIC,LVIC)

miniDIP-IPM
Figure1(a) Photograph

DIP-IPM

Figure1(b) Internal structure

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VUFS

VUFS

VUFB

VUFB
P

VP1
UP

+VCC
Input
Signal
Condition

Level
Shift

P
VP1

Gate
Drive
& UV
lock
out

UP

HVIC

VVFS

VP

+VCC
Input
Signal
Condition

Level
Shift

VP1

Gate
Drive
& UV
lock
out

VP

VPC

HVIC

+VCC
Input
Signal
Condition

Level
Shift

HVIC

Level
Shift

Gate
Drive
& UV
lock
out

VP1
WP

+VCC
Input
Signal
Condition

Level
Shift

VN1

+VCC
Gate
Drive

VN

+VCC
Input Signal
Conditioning

Gate
Drive

WN

FO

FO
Fault Logic &
UV lock out

Protection
Circuit

CFO

CIN
VNC

UN
Input Signal
Conditioning

WN

CFO

Gate
Drive
& UV
lock
out

HVIC

UN
VN

VWFB
V

+VCC
Input
Signal
Condition

HVIC
VN1

Gate
Drive
& UV
lock
out

HVIC

VWFS

VWFB

WP

Gate
Drive
& UV
lock
out

VVFB

VWFS

VP1

Level
Shift

VVFS

VVFB
VP1

+VCC
Input
Signal
Condition

Fault Logic &

UV lock out

Protection
Circuit

CIN

LV-ASIC

VNC

LV-ASIC

VNO

DIP-IPM

miniDIP-IPM
Figure1(c) Internal function block diagram of DIP-IPM

1.3.2 Product Features

Integrated IGBT inverter circuit for three-phase AC output, Loss reduction by employing the 5th generation
planar IGBT and CSTBT (Carrier Stored Trench-gate Bipolar Transistor).
the 5th generation planar IGBT for 5A-30A DIP-IPM.
the CSTBT for 50A DIP-IPM
Single-power-supply drive topology by introducing bootstrap circuit scheme.
Built-in control and protection functions
P-side Control circuit Under-Voltage (UV) protection (without fault signal output).
N-side UV and Short-Circuit (SC) protection by means of external shunt resistor (with fault signal output).
By virtue of integrating high voltage IC (HVIC) inside, direct coupling to CPU without any opto-coupler or
transformer isolation is possible.
By virtue of applying high-active drive logic, the sequence restraint between control supply and control input in
turn on and turn off operation has been able to eliminated, which makes the devices to be fail-safe, and
furthermore, a direct connection without signal level shift to a 3V MCU or DSP becomes possible.

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CHAPTER 2

ELECTRICAL CHARACTERISTICS

2.1 Maximum Ratings

Table 2 shows the Maximum Ratings of PS21865

(*).

Table 2. Maximum Ratings of PS21865

Vccthe maximum P-N voltage in

state of no switching. A brake is
necessary if P-N voltage exceeds
this specification.
Vcc(surge): the maximum P-N surge
voltage in state of no switching. A
snubber circuit is necessary if P-N
voltage exceeds Vcc(surge).
VCES: the sustained collector-emitter
voltage of built-in IGBT.

IC: the allowable DC

current continuously flowing
at collect electrode (Tf=25)

Tj:power cycles will be no less than

10 million on the condition of
Tf=100 and Tj 125 . Although
chip will not be damaged right now
at Tj=150,its power cycles come
to be decreased

Vcc(prot): the Maximum supply

voltage for IGBT turning off safely in
case of SC or OC. The power chip
might be damaged if supply voltage
exceeds this specification.

Viso: united to 2500Vrms in Ver.3

(*): Unless otherwise noted, the data used in this chapter are all of PS21865 (20A/600V) as a demonstration example. For other products of
DIP-IPM ver.3 series, please refer to their individual datasheets.

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2.2. Electric Characteristics

2.2.1 Thermal Resistance
Table 3 shows the thermal resistance of PS21865.
Table 3. Thermal resistance of PS21865

The steady thermal

resistance corresponding
to the unite 1 in figure 2.
Example:
The transient thermal
resistance in 0.1sec of
PS21865 is 1.900.5=0.95
/W.

Table 3 shows the steady thermal resistance between Junction and Fin. The thermal resistance goes into saturation in
about 10 seconds. Figure 2 shows the transient resistance Zth(j-f) curve within 10 seconds.

1
j-f(stardard value)

Zth(j-f)(standard value)

0.1

0.01
0.001

0.01

0.1
tsec

0.1

0.01
0.001

10

0.01

0.1
sec

(a) DIP-IPM Zth(j-f) characteristic

(b) Mini DIP-IPM Zth(j-f) characteristic
Figure 2. DIP-IPM Zth(j-f) characteristic curve(IGBT/FWDi)

2.2.2 Static Characteristics and Switching Characteristics

(1) Static Characteristics
Table 4 shows the typical static characteristics and switching characteristics of PS21865.
Table 4. Static characteristics and switching characteristic of PS21865

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(2) Switching Characteristics

trr
VCE
Irr

P-Side IGBT

Ic

VP1

90%

90%

VB
L

VCIN(P)

IN
COM

OUT
VS

P-Side Input Signal

10%

10%

10%

VCC

10%

tc(off)

tc(on)

VD
VCIN(N)

VCIN
td(on)
tr
( ton=td(on)+tr )

td(off)
tf
( toff=td(off)+tr )

VN1
OUT
IN
VNC

VNO
CIN

N-Side IGBT

N-Side Input Signal

(a) Switching time definition

(b) Evaluation circuit (inductive load)

Figure 3. Half-bridge evaluation circuit diagram

Conditions : VCC=300V, VD=VDB=15V, Tj=125, Ic=20A, Inductive load half-bridge circuit
Turn on

Turn off

Figure 4. Typical switching waveform (PS21865 N-side)

Conditions : VCC=300V, VD=VDB=15V, Tj=125, Ic=10A, Inductive load half-bridge circuit
Turn on

Turn off

Figure 5. Typical switching waveform (PS21563 N-side)

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2.2.3 Control (Protection) Characteristics

Table 5. Control (Protection) characteristics of PS21865

2.3. Recommended Operation Conditions

Table 6 Recommended operating conditions of PS21865.

Note: Although DIP-IPM is able to operate at high frequency upto 20kHz, the allowable r.m.s current will vary according to the temperature
condition,control method (PWM scheme). PWM control signal should be determined on the basis of power loss and thermal evaluation.
The above values are only for reference.

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CHAPTER 3 PACKAGE OUTLINE

3.1 Package Outline Drawing of DIP-IPM

Figure 6. Package outline drawing of DIP-IPM

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3.2 Package Outline Drawing of mini DIP-IPM

Figure 7 Package Outline Drawing of mini DIP-IPM

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3.3 Isolation
Table 7. Isolation distance of DIP-IPM
Clearance (mm)
1.6
DIPIPM
Between Power terminals
6.6
Between Control terminals
3.55
Between Terminals and Fin
3.6

Standard
UL 508
34.7 Table34.1-B
Rating voltage: 51~300V
Below 2HP
Less than 1440VA

Standard
UL 508
34.8 Table34.1-B
Rating voltage: 51~300V
Below 2HP
Less than 1440VA

Creepage distance (mm)

3.2
DIPIPM
Between Power terminals
Between Control terminals
Between Terminals and Fin

6.6
3.55
3.6

Table 8. Isolation distance of mini DIP-IPM

Clearance (mm)
Creepage distance (mm)
1.6
3.2
mini DIPIPM
mini DIPIPM
Between Power terminals
4.0
Between Power terminals
Between Control terminals
1.8
Between Control terminals
Between Terminals and Fin
2.0
Between Terminals and Fin

4.0
4.0
4.0

Both the clearance and the creepage distance of DIP-IPM and/or mini DIP-IPM satisfy the isolation standard of UL
508.

3.4 Laser Marking

The laser marking range of DIP-IPM is described in Figure 8. Mitsubishi Corporation mark, Type name (Part A), and Lot
number(Part B), are marked in the upper side of module .
Marking area
Marking area

PS2186O-O

Brand area
QR code: used for product
line management;
There is possibility of product
without this QR mark.

Figure 8 Laser Marking

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3.5 Input / Output Terminals Description

3.5.1 Terminal Arrangement

Terminal
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

Table 9. (a) DIP-IPM terminal Arrangement

DIP-IPM
Terminal
Description
Name
UP
U-phase P-side control input terminal
VP1
U-phase P-side control supply positive terminal
VUFB
U-phase P-side drive supply positive terminal
VUFS
U-phase P-side drive supply GND terminal
VP
V-phase P-side control input terminal
VP1
V-phase P-side control supply positive terminal
VVFB
V-phase P-side drive supply positive terminal
VVFS
V-phase P-side drive supply GND terminal
WP
W-phase P-side control input terminal
VP1
W-phase P-side control supply positive terminal
VPC
P-side control supply GND terminal
VWFB
W-phase P-side drive supply positive terminal
VWFS
W-phase P-side drive supply GND terminal
VN1
N-side control supply positive terminal
VNC
N-side control supply GND terminal
CIN
SC current trip voltage detecting terminal
CFO
Fault pulse output width setting terminal
FO
Fault signal output terminal
UN
U-phase N-side control input terminal
VN
V-phase N-side control input terminal
WN
W-phase N-side control input terminal
P
Inverter DC-link positive terminal
U
U-phase output terminal
V
V-phase output terminal
W
W-phase output terminal
N
Inverter DC-link negative terminal
VPC
Dummy-pin
(Note 1)
UPG
Dummy-pin
P
Dummy-pin
VPC
Dummy-pin
VPG
Dummy-pin
U
Dummy-pin
WPG
Dummy-pin
V
Dummy-pin
UNG
Dummy-pin
VNC
Dummy-pin
VNO
Dummy-pin
WNG
Dummy-pin
VNG
Dummy-pin
W
Dummy-pin
P
Dummy-pin

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Terminal
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

Table 9. (b) Mini DIP-IPM terminal Arrangement

Mini DIP-IPM
Terminal
Description
Name
VUFS
U-phase P-side drive supply GND terminal
UPG
Dummy-pin
VUFB
U-phase P-side drive supply positive terminal
VP1
U-phase P-side control supply positive terminal
COM
Dummy-pin
UP
U-phase P-side control input terminal
VVFS
V-phase P-side drive supply GND terminal
VPG
Dummy-pin
VVFB
V-phase P-side drive supply positive terminal
VP1
V-phase P-side control supply positive terminal
COM
Dummy-pin
VP
V-phase P-side control input terminal
VWFS
W-phase P-side drive supply GND terminal
WPG
Dummy-pin
VWFB
W-phase P-side drive supply positive terminal
VP1
W-phase P-side control supply positive terminal
COM
Dummy-pin
WP
W-phase P-side control input terminal
UNG
Dummy-pin
VNO
(Note 2
UN
U-phase N-side control input terminal
VN
V-phase N-side control input terminal
WN
W-phase N-side control input terminal
FO
Fault signal output terminal
CFO
Fault pulse output width setting terminal
CIN
SC current trip voltage detecting terminal
VNC
N-side control supply GND terminal
VN1
N-side control supply positive terminal
VNG
Dummy-pin
WNG
Dummy-pin
P
Inverter DC-link positive terminal
U
U-phase output terminal
V
V-phase output terminal
W
W-phase output terminal
N
Inverter DC-link negative terminal

Note:
1)
2)

Dont connect dummy-pins to any other terminals or PCB pattern.

VNO terminal treatment way:
Connect it with N terminal for PS21562(5A/600V) or PS21563(10A/600V);
Leave it open for PS21564(15A/600V).

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3.5.2 Detailed Description of Input / Output Terminals

Table 10. Detailed description of input and output terminals
Item
Symbol
Description
Drive supply terminals for the P-side IGBTs.
By virtue of applying the bootstrap circuit scheme, individual isolated power
P-side drive
supplies are not needed for the DIP-IPM P-side IGBT drives. Each bootstrap
supply positive
capacitor is charged by the N-side VD supply during ON-state of the
corresponding N-side IGBT in the loop.
terminal
U(VUFB)VUFS
Abnormal operation might happen if the VD supply is not aptly stabilized or has
V(VVFB)VVFS
insufficient current capability. In order to prevent malfunction caused by such
W(V
WFB)VWFS
P-side drive
unstability as well as noise and ripple in supply voltage, a smoothing capacitor
with favorable frequency and temperature characteristics should be mounted
supply GND
very closely to each pair of these terminals.
terminal
Inserting a Zener diode (24V/1W) between each pair of control supply terminals
is helpful to prevent surge destruction.
Control supply terminals for the built-in HVIC and LVIC.
P-side control
In order to prevent malfunction caused by noise and ripple in the supply voltage,
a smoothing capacitor with favorable frequency characteristics should be
supply terminal
VP1
mounted very closely to these terminals.
Carefully design the supply so that the voltage ripple caused by noise or by
VN1
N-side control
system operation is within the specified minimum limitation.
It is recommended to insert a Zener diode (24V/1W) between each pair of control
supply terminal
supply terminals to prevent surge destruction.
Control ground terminal for the built-in HVIC and LVIC.
N-side control
Ensure that line current of the power circuit does not flow through this terminal
VNC
GND terminal
in order to avoid noise influences.
Control signal input terminals.
Voltage input type. These terminals are internally connected to Schmitt trigger
UP,VP,WP
Control input
circuit composed by 5V-class CMOS.
terminal
The wiring of each input should be as short as possible (less than 2 cm) to
UN,VN,WN
protect the DIP-IPM from noise interference.
To prevent signal oscillations, an RC coupling is reccomended.
Current sensing resistor should be connected between this terminal and VNC to
Short-circuit trip
detect short-circuit accidents (short-circuit voltage trip level). Input impedance
voltage detecting
CIN
for CIN terminal is approximately 600k.
terminal
CR filter should be connected for noise immunity.
Fault signal output terminal.
Fault signal
This output is open collector type. FO signal line should be pulled up to a 5V
FO
output terminal
logic supply with approximately 10k resistor.
The terminal is for setting the fault pulse output width.
Fault pulse
An external capacitor should be connected between this terminal and VNC to set
CFO
output width
the fault pulse width.
The capacitor of 22nF is recommended (corresponding to 1.8ms typical value of
setting terminal
fault pulse output time).
DC-link positive power supply terminal.
Internally connected to the collectors of all P-side IGBTs.
Inverter DC-link
P
To suppress surge voltage caused by DC-link wiring or PCB pattern inductance,
positive terminal
smoothing capacitor should be inserted verry closely to the P and N terminal. It
is also effective to add small film capacitor with good frequency characteristics.
Inverter DC-link
DC-link negative power supply terminal (power ground) of the inverter.
N
This terminal is connected internally to the emitters of all N-side IGBTs.
negative terminal
Inverter output terminals for connection to inverter load (e.g. AC motor).
Inverter power
U, V, W
Each terminal is internally connected to the intermidiate point of the
output terminal
corresponding IGBT half bridge arm.

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3.5.3 Description of Protective Functions

Table 11. Description of protective functions
Function
Symbol
Description
high-active drive logic.
Normal drive
A low-level input signal (VCIN < Vth(off) ) drives IGBT off, and a high-level input

signal (VCIN > Vth(on) ) drives IGBT on.

The external shunt resistor detects bus current of the DC-link. A short circuit is
regarded when the current exceeds the specified SC trip level, and the N-side
IGBTs are turned off immediately.
Short circuit
A fault pulse signal is output from Fo terminal when an SC current flows through
protection
SC
the external shunt resistor. The pulse duration is determined by the capacitance of
the capacitor connected between CFO and VNC. The reset operation is
performed at the first on-lever signal input soon after Fo pulse duration .
An internal logic monitors the N-side control supply voltage. If the voltage falls
below the UVD trip level for a given period of time, input signals to the N-side
IGBTs are locked.
The state of control circuit under-voltage protection continuous until the voltage
UVD
exceeds the UVDr reset level.
Control supply
The fault resetting takes place at the next input signal if control supply voltage
under voltage
rises over the reset level.
protection
An internal logic monitors the P-side floating supply voltage. If the voltage level
(UV)
drops below the UVDB trip level for a given period of time, input signal for the
corresponding P-side IGBT will not be accepted.
UVDB
The state of control circuit under-voltage protection continuous until the voltage
exceeds the UVDBr reset level.
Fault signal is not output for the P-side UV failure.
3.5.4 Operation Sequence
DIP IPM Ver.3 is designed with high-active input logic, which is different from that of Ver.2.

Control input signal

IGBT gate signal
IGBT gate current

Figure 9. Operation sequence

3.5.5 Installation Guidelines (Flatness / Mounting Strength / Screw Type / Grease)

When installing a module to a heat sink, excessive uneven fastening way might apply stress to inside chips, which
will lead to a broken or degradation of the device. An example of recommended fastening order is shown in Figure
10.

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Temporary fastening

Permanent fastening

Figure 10. Recommended fastening order

Note Generally, the temporary fastening torque is set to 2030% of the maximum torque rating.

Item
Mounting torque
Case surface flatness
Heat sink flatness

Table 12. Mounting torque and heat sink flatness specifications

Condition
Min.
Typ.
Max.
Recommended 1.18Nm
0.98
1.18
1.47
DIP IPM
Mounting screw : M4
Recommended 0.78Nm
mini DIP-IPM
0.59
0.78
0.98
Mounting screw : M3
See Fig. 11(a)
50

+100
See Fig. 11(b)
50

+100
Surface applied grease

Unit
Nm
Nm
um
um

DIP-IPM

DIP-IPM
Measurement point

3mm

Base-plate edge
Place to contact a
heat sink

Heat sink

Heat sink flatness range

Heat sink

(a)

(b)

Figure 11. Measurement point of heat sink flatness

Note: The measurement point of mini DIP-IPM is 3mm away from the screw, toward the power terminals.

In order to get most effective heat dissipation, it is necessary to enlarge the contact area as much as possible to
minimize the contact thermal resistance. Regarding the heat sink flatness (warp/concavity and convexity) on the
module installation surface (refer to Fig.11), the surface finishing-treatment should be within Ra12.5.
Tightening torque test
Figure 12 shows the test method: Inserting a 100um-thickness gauge
between DIP-IPM and heat sink, then increase fastening torque step by
step to verify whether there is a package broken or characteristics
degradation.
**: It has been confirmed that the bearing capability of tightening torque is
larger than 0.98Nm (10kgcm) even in the worst condition.

Planar
DIP-IPM
gauge

Heat-sink

Figure 12 Tightening torque test

Evenly apply thermally-conductive grease with 100um200um over
the contact surface between a module and a heat sink, which is also useful for preventing the contact surface
from corrosion. Furthermore, ensure the grease to be with stable quality and long endurance within wide
operating temperature range. Use a torque wrench to fasten up to the specified torque rating. Exceeding the
maximum torque limitation might cause a module to be damaged or degraded. Also, pay attention not to have
any desert remaining on the contact surface between the module and the heat sink.

DIP-IPM

DPH2588eB
(17/46)

Application Note

MITSUBISHI ELECTRIC CORPORATION

Application Note Prep.

Rev.

Apr.

CHAPTER 4

APPLICATION SYSTEM

4.1 System Connection Diagram

CBW+

CBV+

CBW-

CBU+

High-side input (PWM)

(5V line)
Note 1,2)

CBV-

CBU-

C3: Tight tolerance, temp-compensated electrolytic type

(Note: The capacitance depends on the PWM control scheme used in
the applied system.)
C4: 0.22 2uF R-category ceramic capacitor for noise filtering

C4
Input signal Input signal
conditioning conditioning
Level shifter
Protection
circuit (UV)

C3

Input signal
conditioning

Level shifter Level shifter

Protection
circuit (UV)

Note 6)

Protection
circuit (UV)

DIP-IPM
Drive circuit Drive circuit

Inrush current
limiter circuit

Drive circuit

AC input

H-side IGBTs

U
Note 4)

V
W

Fig.3

AC line output

N1

VNC

Z: Surge absorber.
C: AC filter (Ceramic capacitor 2.2 ~ 6.5nF)
(Protection against common-mode noise)

L-side IGBTs

CIN
Drive circuit

Input signal conditioning

Low-side input (PWM)

(5V line)
Note 1,2)

Fo logic

Fo

SC protection

Control supply
under-voltage
protection
Note 7)

CFO

Fo output (5V line)

Note 3,5)

VNC

VD
(15V line)

Figure 13. System block diagram of DIP-IPM

Note 1) To prevent input signals oscillation, an RC coupling at each input terminal is recommended.
Note 2) By virtue of integrating HVIC inside the module, direct coupling to CPU terminals without any
opto-coupler or transformer isolation is possible.
Note 3) Fo output is open collector type. This signal line should be pulled up to the positive side of a 5V supply
with an approximate 10k resistor.
Note 4) The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to
protect DIP-IPM against catastrophic high surge voltage. For extra precaution, a small film type snubber
capacitor (0.10.22uF, high voltage type) is recommended to mount closely to the P and N1 terminals.
Note 5) Fo output pulse width (tFO) should be determined by connecting external capacitor between CFO and VNC
terminals. (Example CFO = 22nF tFO = 1.8ms (Typ.)).
Note 6) High voltage diodes (600V or more) should be used for the bootstrap circuit.
Note 7) To prevent HVIC from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between
each control supply terminals.

DIP-IPM

DPH2588eB
(18/46)

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MITSUBISHI ELECTRIC CORPORATION

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4.2 Input circuit

4.2.1 Structure of Control Input Terminals and Application Examples
DIP-IPM Ver.3 series employ High-Active input logic
which released the sequence restriction between the
control supply and the input signal in start-up or
shut-down operation, therefore, makes the system
UPVPW P
fail-safe.
In addition, an about 2.5k pull-down resistor is
built-in each input circuit of the DIP-IPM as shown in
Fig. 14, hence, external pull-down resistor is not
needed.
UNVNW N
Furthermore, by lowering the turn on and turn off
threshold value of input signal as shown in Table 13, a
direct connection to 3V-class microcomputer or DSP
becomes possible.

DIP-IPM
1k

Gate
Driver

Level shift
circuit

2.5(min.)

1k

Gate
Driver

2.5(min.)

Figure 14. Internal structure of control input terminals

Table 13. Input threshold voltage ratingsVD=15V, Tj25
Item
1.Turn-on threshold voltage
2.Turn-off threshold voltage

Symbol
Vth(on)
Vth(off)

Condition
UPVPWP-VNC terminals
UNVNWN-VNC terminals

Min.
2.1
0.8

Typ.
2.3
1.4

Max.
2.6
2.1

Unit
V
V

4.2.2 Input Signal Voltage Rating

The input signal and the fault signal input/output is applicable not only for 35V class interface but also for 15V class
interface. The maximum ratings for input signal and FO output voltages are shown in Table 14. Since FO is an open
collector type terminal, it should be pulled up to the positive side of a 5V (or 15V) supply.
Table 14. Maximum ratings of input voltage and fault output voltage (Tj25)
Item

Symbol

Input voltage

VCIN

Fault output voltage

VFO

Condition
Applied
between
UP,VP,WP-VNC,
UN,VN,WN-VNC
Applied between Fo-VNC

Rating

Unit

-0.5VD+0.5

-0.5VD+0.5

4.2.3 Minimum Rating of Control Input Pulse Width

Table 15. Minimum rating of control input pulse width
Condition
PWIN(on)

Allowable
minimum
pulse width of
control input

PWIN(off)

200VCC350V,
13.5VD16.5V,
13.0VDB18.5V,
-20Tf100,
N-line inductance less
than 10nH

Below rated
current

Between rated
current and 1.7
times of rated
current

PS21562
PS21563
PS21564
PS21865
PS21867
PS21869
PS21562
PS21563
PS21564
PS21865
PS21867
PS21869

min
0.3
0.5
0.5
0.5
1.4
1.5
3.0
0.5
0.5
2.0
2.5
3.0
5.0

typ

max

Unit

usec

Note: DIP-IPM might make no response to an input on signal with pulse width less than PWIN(on);
DIP-IPM might make no response or not work if the input off signal pulse width is less than PWIN(off).

DIP-IPM

DPH2588eB
(19/46)

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MITSUBISHI ELECTRIC CORPORATION

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4.3 Single Supply Drive Scheme

4.3.1 Initial Charging
Initial charge loop

P(VCC)

Bootstrap Condenser

P-side IGBT
HVIC

VDB
U,V,W
High Voltage & High Speed
Recovery Type Diode

N-side IGBT
VD

LVIC

VCIN(N)
N(GND)
Bootstrap Circuitry

VCC

PWM Start
0V

VD
0V

VDB
0V

VCIN(N)
off

Bootstrap Charging Timing Chart

Figure 15. Charging current loop and timing chart of bootstrap circuit
Charging:
In order to start the DIP-IPM, initial bootstrap charging is necessary. By turning on the N-side IGBT, as
shown in Figure 16, the bootstrap capacitor will be charged. The pulse width or pulse number should be large
enough for a full charge of the bootstrap capacitor.

4.3.2 Charging and Discharging of the Bootstrap Capacitor During Inverter Operation

DIP-IPM

DPH2588eB
(20/46)

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VB

High-side IC

P
C1

R1
D1

R1

VCC

ID

IGBT1

FWDi1

VS

M1

IGBT2

Q1

FWDi2

Figure 16. Inverter circuit diagram

1 Charging operation Timing Chart of Bootstrap Capacitor (C1)
Sequence (1-1) : IGBT2 ON (Figure 17)
When IGBT2 is in the ON state, charging voltage on C1 (VC(1)) is calculated by
VC(1) = VCCVF1Vsat2IDR1
(Transient state)
VC(1) = VCC
(Steady state)
VCC is the charging supply voltage, VF1 the forward voltage drop of diode D1, Vsat2 the saturation voltage of
IGBT2, ID the charging current, and R1 the inrush current limitation resistance.
Then, IGBT2 is turned off. Motor current will flow through the free-wheel path of FWD1. Once the electric
potential of VS rises near to that of P, the charging to C1 is stopped.
When IGBT1 is in ON state, the voltage of C1 gradually declines from the potential VC(1) due to the current
consumed by the drive circuit.
ON
IGBT1
OFF
ON
IGBT2

Spontaneous discharge of C1
OFF
Declining due to current
consumed by drive circuit
VC1

Potential of C1

VC(1)

VS

Figure 17. Timing chart of sequence (1-1)

DIP-IPM

DPH2588eB
(21/46)

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Sequence (1-2): IGBT2 OFF and FWD2 ON (Figure 18)

When IGBT2 is OFF and FWD2 is ON, the voltage on C1 (VC(2)) is calculated by:
VC(2)=VCCVF1VEC2
where VEC2 denotes the forward voltage drop of FWD2. When both IGBT2 and IGBT1 are OFF, the
regenerative current flows continuously through the free-wheel path of FWD2. Therefore the potential of VS
drops to -VEC2, then C1 is recharged to restore the declined potential. When IGBT1 is turned ON, the potential
of VS rises to that of P, the charge to C1 stops and the voltage on C1 gradually declines from the potential V
C(2) due to the current consumed by the drive circuit.
ON
IGBT1
OFF
ON
IGBT2
OFF
VC1
Potential of C1

VC(2)

Declining due to current

consumed
by
drive
circuit

VS

Figure 18. Timing chart of sequence (1-2)

2 Guidelines of Selecting the Bootstrap Capacitor (C1) and Resistance (R1)
The capacitance of bootstrap capacitor can be calculated by:
C1=IBST1/V
where T1 is the maximum ON pulse width of IGBT1 and IBS is the drive current of the IC (depends on
temperature and frequency characteristics), and V is the allowable discharge voltage. A certain margin
should be added to the calculated capacitance.
Resistance R1 should be basically selected such that the time constant C1R1 will enable the discharged
voltage (V) to be fully charged again within the minimum ON pulse width (T2) of IGBT2.
However, if only IGBT1 has an ONOFFON control mode (Figure 19), the time constant should be set so
that the consumed energy during the ON period can be charged during the OFF period.
ON
IGBT1
OFF
ON
IGBT2
OFF
Declining due to current
consum ed by drive circuit
Vc1
Charging area

Potential of C1

VS

Figure 19. Timing Chart of ONOFFON Control Mode

DIP-IPM

DPH2588eB
(22/46)

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MITSUBISHI ELECTRIC CORPORATION

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Designing example of Bootstrap circuit

Selecting bootstrap capacitor
Condition: VDB(discharged voltage)=1V, The maximum ON pulse width T1 of Upper-side IGBT is 5ms, IDB is
0.35mA(Max. rating).
C=IDBT1/VDB=1.7510-6
The calculated bootstrap capacitance is 1.75 F. By taking consideration of dispersion and reliability, the
capacitance is generally selected to be 23 times of the calculated one.
Selecting bootstrap resistor
Condition: The value of bootstrap capacitor is 5F, VD=15V, VDB=14V. If the minimum ON pulse width t0 of
lower-side IGBT or the minimum OFF pulse width t0 of upper-side IGBT is 20 s, bootstrap capacitor needs to be
charged VDB=1V during this period, therefore,
R={(VDVDB)t0}/(CVDB)=4
The bootstrap resistor should be 4.
In the case of the control for DCBLM or 2-phase modulation for IM (Induction Motor), there will be a long ON time
period on the high-side IGBT, please pay attention to the bootstrap supply voltage drop.
Note:
The above result is only a calculation example. It is recommended that you design a system by taking consideration of the actual
control pattern and lifetime of components.

Selecting bootstrap diode

The bootstrap diode with withstand-voltage more than 600V is recommended. In DIP-IPM, the maximum rating of
power supply is 450V. The actual voltage applied on the diode is 500V including a surge voltage of about 50V.
Furthermore, if considering 100V for the margin, 600V class diode is necessary. The diode is also highly
recommended to be with fast recovery characteristics (recovery time is less than 100ns).
Reference:
Recommended bootstrap diode: 10DF06 made by Inter Co., Japan.
Noise filter for control supply
It is recommended to insert a film type or ceramic type noise filter with 0.222F to the control supply
terminals(VP1-VPC, VN1-VNC, VUFB-VUFS, VVFB-VVFS, VWFB-VWFS). The smaller the supply parasitic impedance is , the
smaller a feasible noise filter capacitance can be . The supply circuit should be such designed that the noise
fluctuation is less than 1V/s, and the ripple voltage is less than 2V.
Reference:
There are tow kinds of control supply in general use. The first one is DC-DC converter (3-terminal regulator), of
which input DC supply comes from AC-transformer. The other is DC-DC converter (switching regulator), of which
input DC supply comes from DC-link supply directly.
Note:
After bootstrap voltage have been fully charged, please input one pulse as the reset pulse of P-side input signal before starting
PWM.

DIP-IPM

DPH2588eB
(23/46)

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MITSUBISHI ELECTRIC CORPORATION

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4.3.3 Current Characteristics

Figure 2022 show the current characteristics of P-side bootstrap supply versus carrier frequency under different
temperature, respectively. (Typical for PS21865)
Conditions: VD=VDB=15V, Tj=-20, 25, 125deg., Duty=10, 30, 50, 70, 90%, fc=3, 7, 15, 20kHz

Circuit currient (A)

400
350

10%

300

30%
50%

250

70%
90%

200
150
100
1

10

100

Carrier frequency (kHz)

Figure 20. Current characteristics at Tj=-20deg.

Circuit current (A)

400
350
300

10%
30%

250

50%
70%

200

90%

150
100
1

10

100

Carrier frequency (kHz)

Figure 21. Current characteristics at Tj=25deg.

Circuit current (A)

400
350

10%

300

30%
50%

250

70%

200

90%

150
100
1

10

Carrier frequency (kHz)

100

Figure 22. Current characteristics at Tj=125deg.

DIP-IPM

DPH2588eB
(24/46)

Application Note

MITSUBISHI ELECTRIC CORPORATION

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Apr.

Table 16. Typical value of circuit current for PS21865

(unit: uA)
Tj
(deg.)

-20

25

125

DIP-IPM

PWM Frequency
fc(kHz)
3
5
7
10
15
20
3
5
7
10
15
20
3
5
7
10
15
20

10
210
227
242
262
295
329
230
247
260
281
313
342
255
272
284
303
333
362

30
191
208
225
250
290
329
211
226
243
266
309
341
236
253
268
294
332
363

DPH2588eB
(25/46)

Duty (%)
50
173
189
205
231
273
315
192
208
224
249
290
328
217
235
249
274
315
351

70
153
170
186
212
255
297
172
188
204
230
272
310
198
215
230
256
294
332

90
135
151
169
194
236
278
154
170
186
210
254
290
179
196
211
235
274
312

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4.4 Interface Circuit Examples and Guidelines

4.4.1 Example of Direct Input Interface
Figure 23 shows a typical application circuit of interface schematic, where control signals are transfered directly from a
microcomputer.
C1:Tight tolerance temp-compensated electrolytic type
C2,C3: 0.10.22F R-category ceramic capacitor for noise filtering.
(Note: The capacitance value depends on the PWM control used in the applied system.)
C2

DIP-IPM

VUFB
VUFS
VP1
C3

HVIC1

C1

UP

VCC
IN

VB
HO
U

COM

C2

VS

VVFB
VVFS

HVIC2

C1
VP1
C3

VP

VCC
IN

VB
HO
V

COM

C2

VS

VWFB
VWFS

CPU

C1
C3

HVIC3
VP1
WP

VCC
IN

VB
HO

UNIT

W
COM

VS

LVIC
UOUT
VN1
5V line

VCC

C3

VOUT
UN
VN
WN
Fo

UN
VN
WN
Fo

VNO
E

CIN
VNC

GND

If this wiring is too long,

short circuit might be caused.

Note 10

W OUT

VNO

CFO
CFO

This connection is necessary

only for PS21562/PS21563.

CIN

C4(CFO)

15V line
C5

R1

Shunt
Resistance

A
N1

The long wiring of GND might generate

noise on input and cause IGBT to
be malfunction.

If this wiring is too long, the SC level

fluctuation might be larger and cause
SC malfunction.

Figure 23. A example of interface circuit without opto-coupler

Note:
(1) To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm)
(2) By virtue of integrating HVIC inside the module, direct coupling to CPU output without any opto-coupler or transformer isolation is
possible.
(3) Fo output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply by a resistor of
about 10k.
(4) Fo output pulse width can be determined by connecting an external capacitor between CFO and Vnc terminals (CFO). (Example
CFO=22nFtFO=1.8ms(Typ.))

DIP-IPM

DPH2588eB
(26/46)

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(5) Input signal is High-Active type. There is a 2.5k (Min.) resistor inside IC to pull down each input signal line to GND. When
employing RC coupling circuits at each input, set up such RC couple that input signal agree with turn-off /turn-on threshold voltage.
(6) To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
(7) The time constant R1C4 of the protection circuit should be selected in the range of 1.52s. SC interrupting time might vary with
the wiring pattern.
(8) All capacitors should be mounted as close to the terminals of the DIP-IPM as possible.
(9) To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible.
Generally a 0.10.22F snubber between the P&N1 terminals is recommended.
(10) Please connect VNO to N terminal outside the DIP-IPM of PS21562 and PS21563, as shown as part D, and leave VNO terminal
open in the case of PS21564/865869 because the VNO is connected with N inside as shown as part E.

4.4.2 Example of Interface with Fast Opto-Coupler

Figure 24 shows a typical application circuit interface schematic by using fast Opto-Coupler (Except Fo).
VUFB

DIP-IPM

VUFS
C1 C2

VP1
C3

DC 5V

UP

HVIC1
VCC

VB

IN

HO

COM

VS

DC 5V

VVFB

VVFS
Control Unit

C1 C2
C3

VP1
VP

VWFB

HVIC2
VCC

VB

IN

HO

COM

VS

VWFS
C1 C2
C3

VP1
WP

HVIC3
VCC

VB

IN

HO

R
E
L
L
O
R
T
N
O
C

COM

VS

LVIC
UOUT

VN1
VCC

C3

VOUT

UN
VN
WN
FO

UN
VN

WOUT

WN

N
VNO

FO

CIN

VNC

GND

VNO

CFO

CFO

CIN

DC 15V

R1

C4
C5

Shunt Resistor
N1

Figure 24. An example of interface circuit with fast opto-Coupler

Note:
(1) Fast type opto-coupler is recommended for electric isolation. Slow type opto-coupler leads to much longer time in signal
rising and falling edge therefore is not recommended.
(2) Because Fo output current is 1mA(max) which cannot drive directly an opto-coupler, a buffer circuit should be added in
the primary side of the opto-coupler.

DIP-IPM

DPH2588eB
(27/46)

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4.4.3 Snubber Circuit

There are two positions (or) to mount a snubber capacitor to the DIP-IPM as shown in Figure 25. Snubber capacitor
should be installed in the position so as to suppress surge voltage effectively. However, the charging and discharging
currents generated by the wiring inductance and the snubber capacity will flow on the shunt resistor, which might cause
an error protection if this current is large enough to reach the SC trip level on the shunt resistor.
In order to suppress the surge voltage maximally, the wiring at part-A should be as short as possible when mounting a
snubber capacitor outside the shunt resistor as shown in position . An effective wiring example is shown in location
.
SIP-IPM
Wiring Inductance
P

N
A

Figure 25. Instruction for snubber circuit location

4.4.4 Parallel Connection
Figure 26 shows the circuitry of parallel connection of two DIP-IPMs.
Route and indicate the gate charging path of low-side IGBT in DIP-IPM No.2. If the route is too long, gate voltage
might drop due to large voltage drop on the wiring, which will result a bad effect to the second IPM operation. (Charging
of bootstrap capacitor for high-side is similar, too.).
In addition, noise might easily impose to the wiring impedance. If there are many DIP-IPM parallel connected, GND
pattern becomes long and the influence to other circuit (power supply, protection circuit etc.) by the fluctuation of GND
potential is conceivable, therefore parallel connection is not recommended.
SIP-IPM No.1
VN1

DC15V

U,V,W

M
AC100/200V

VNC

Shunt resistor

SIP-IPM No.2
VN1

U,V,W

Shunt resistor
VNC

Figure 26. Parallel Connection

DIP-IPM

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(28/46)

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4.4.5 Input Signal Connection

Because input logic of DIP-IPM Ver.3 is High-Active, and there is pull-down resistor built-in each input circuit
external pull-up or pull-down resistor is no longer needed.
DIP-IPM has limitation for the allowable input pulse width, especially the off pulse width. DIP-IPM might make no
response or not work properly if the pulse width is less than the specified one. Please refer to Fig.28 for the
countermeasure against possible small pulse width input.
Fo output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply by
a resistor of approximate 10k.
R

5V line

DIP-IPM
Input

MCU
Di
10k

DIP-IPM
(1) Referenced filter with resistor and diode

UP,VP,W P,VN,VN,W N
CPU
Fo

DIP-IPM

MCU

2.5k(min)

Input
C

C
VNC(Logic)

(2) Referenced filter with general logic (inverter)

Figure 27. Input signal connection

Figure 28. Example of Filter for narrow off pulse.

Note: RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the
application and the wiring impedance of the applications printed circuit board.
The DIP-IPM input signal section integrates a 2.5k (min) pull-down resistor. Therefore, when using an external
filtering resistor, please pay attention to the signal voltage drop at input terminal.

4.4.6 Recommended Wiring of Shunt Resistor

External current sensing resistor is applied to detect short-circuit accidents. A longer pattern between the shunt resistor
and DIP-IPM will cause so large surge that might damage built-in IC. To decrease the pattern inductance, the wiring
between the shunt and DIP-IPM should be as short as possible.

This wiring is necessary only for PS21562/PS21563.

Dont connect this wiring for PS21564.

DIP-IPM

Wiring Inductance should be less than 10nH.

width=3mm, thickness=100m, length=17mm
in copper pattern (rough standard)
VNO
Shunt resistor
VNC

N
Please make the connection point
as close as possible to the terminal
of shunt resistor

Figure 29. Recommendation for wiring of shunt resistor

DIP-IPM

DPH2588eB
(29/46)

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4.5 Short Circuit Protective Function

4.5.1 Timing Chart of Short Circuit (SC) Protection (Figure 30)
SC protection (Lower-arms only) : Activated by external shunt resistor and CR time constant circuit
a1.Normal operation: IGBT ON and carrying current
a2.SC current detection (SC trigger). The optimum setting for CR circuit time constant is 1.52.0 us.
a3.Hard interruption of IGBT gate
a4.IGBT turns OFF
a5. Fo timer operation starts. The pulse width of the Fo signal is set by the external capacitor CFO.
a6.Input L= IGBT OFF state
a7.Input H= IGBT ON state
a8.IGBT OFF state
N-side control input

a6

Protection circuit state

a7

SET

Internal IGBT gate

RESET

a3
a2
SC

a4

a1
Output current Ic(A)

a8
SC reference voltage

Sense voltage of the

Shunt resistance
CR circuit time constant delay

Error output Fo

a5

Figure 30. Timing chart of SC operation

Note:
The reset of SC protection will not activated unless the Fo level changes from low to high. IGBT will turn ON just at the next
Low-to-High input signal.

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4.5.2 Selecting Current Sensing Shunt Resistor

(1) Short-Circuit Protection
Figure 31 shows an example of external SC protection circuit. The line current on N-side DC-link is detected and
the protective operation starts through the RC filter. If the current exceeds the SC reference level, all the gates of
the N-side three-phase IGBTs are interrupted and the fault signal is asserted. As shortcircuit protection is
non-repetitive, IGBT operation should be stopped immediately as soon as the fault output.
DIP-IPM

Drive circuit

H-side IGBTs

U
V
W
L-side IGBTs
SC Protection External Parts

N1

External shunt resistor A

Note1)

Collect current

Ic (A)

SC protection level

N
VNC

Collector current
waveform

Drive circuit

CIN
B
C

Note2)

2
SC protection

Input pulse width tw (us)

Figure 31. Example of external protection circuit

External protection circuit triggers off an SC protection by comparing the external shunt voltage to the reference SC
trip voltage in HVIC. Then, HVIC interrupt IGBT gate to stop IGBT operation.
(2) Selecting Shunt Resistance
The value of current sensing resistance is calculated by the following expression :
R= VSC(ref)SC
where VSC(ref) is the SC reference voltage (trip level) of the control IC.
The maximum value of SC trip level should be set less than the minimum value of IGBT saturation current which is
1.7 times as large as the rating current. For example, the maximum value of SC trip level of PS218645 is 1.7 x
20=34A.
Table 17. Specification for VSC(ref) (Unit:[V])
Min
Typ
Max
Specification at

-20Tj125

0.43

0.48

0.53

Similarly, by considering the dispersed property of shunt resistance, SC trip level is calculated as:
SC(max)= VSC(ref)max./min. shunt resistance value .(1)
SC(typ) = VSC(ref)typ./ typ. shunt resistance value
SC(min)= VSC(ref)min./ max. shunt resistance value
If shunt resistance dispersion is 5%, then the operative SC level has a variation as shown in Table 18.
Table 18. Operative SC level (unit: A)

(Shunt resistance min.15.6mtyp.16.4mmax.17.2m)

min.
typ.
max.
Operative SC level at -20Tj125
25
29.2
34
It is possible that the actual SC protective level is less than a calculated one, due to the resonant signals caused
mainly by parasitic inductance and parasitic capacity. The final shunt resistance is recommended to determine by
prototype experiment.

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4.5.3 Filter Circuit Setting (RC Time Constant) for Short-circuit Protection Operation
(1) RC Time Constant Setting
It is necessary to set an RC filter in order to prevent malfunction of SC protection in case of noise interference. The RC
time constant is determined depending on the applying time of noise interference and the withstand voltage capability of
the IGBT.
When the voltage drop on external shunt resistor exceeds the SC protective level, the voltage is applied to CIN terminal
via the RC filter. The time (t1) that the CIN terminal voltage rises to the referenced SC protective level can be calculated
by the following expression:

V=RI(1--t1/ )
t1=-ln(1-(V/RI) (2)
VSC reference voltage VSC(ref),
RShunt resistance,
IPeak current,
RC time constant,
The typical time delay of IC is shown in Table 19, ever since the IGBT gate starts to be interrupted by SC trip voltage
detected at CIN terminal.
Table 19. Internal time delay of IC
Item
min
typ
max
Unit
IC transfer delay time
0.3
0.5
1.0
s
Therefore, the total time from an SC trip current is detected to the IGBT gate is interrupted becomes:
tTOTAL=t1+t2
Example)
In the case of PS21865, if the maximum value of SC trip level (peak current) is set to 1.7times of the rated current (34A),
and the shunt resistor is 15.6m , RC time constant is 2us, VSC(ref) is 0.53V, then, the characteristics of the maximum
current versus interrupting time can be obtained as shown in Figure 32.
250

50

VD=18.5V
VD=16.5V

200

Ic(peak) (A)

Collector Peak Current (A)

60

40
30
20

VD=15.0V
150
Maximum
saturation current
(VD=16.5V)

100
50

10

IGBT SC operation
area

0
0

10
15
20
IGBT shutdown Time (us)

25

Figure 32 PS21865 Shutdown time characteristics

Input pulse width (us)

Figure 33 PS21865 short circuit SOA

Figure 33 shows the typical safe operation area (SOA) of the 5th gen. IGBT used in PS21865 under a short circuit failure
status with the following condition. The graph illustrates that if the input ON pulse width is less than 4.5us, IGBT has the
ability to turn off safely. In this case IGBT can shutdown an SC current of about 190A under a recommended control
supply voltage of 16.5V.
Vcc=400V, Tj=125deg., Vth(on)=min. non-repetitive, VCES600, Vcc(surge)=500V, 2m-long inductive load

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(2) Guidelines of Wiring for Protection Circuit

Drive circuit

DIP-IPM
P

H-side IGBTs

U
V
W

SC protection External Parts

DC-bus current route

L-side IGBTs

A
C

Drive circuit

R2

CIN
C1

Shunt resistance

SC protection
VNC

D
N1

Figure 34. External protection circuit

A. Influence of the part-A wiring pattern
The ground of Low-side IGBT gate is VNC. If part-A wiring pattern in Figure 34 is too long, voltage fluctuation occurs
due to the wiring inductance, which results the potential of IGBT emitter variation during switching operation. Please
install shunt resistor as close to the N terminal as possible.
B. Influence of the part-B wiring pattern
The part-B wiring affects SC protection level. SC protection works by judging the voltage over the CIN-VNC(typ.0.48V)
terminals. If part-B wiring is too long, surge voltage occurs easily due to the wiring inductance, therefore leads to
deterioration of SC protection level. It is necessary to connect CIN and VNC directly to the two ends of shunt resistor
and avoid the part-B wiring area.
C. Influence of the part-C wiring pattern
C1R2 filter is added to remove noise influence occurring on shunt resistor. Filter effect will become small and noise is
easy to impose on the wiring if part-C wiring is too long. Please install a C1R2 filter near CIN, VNC terminal as close as
possible.
D. Influence of the part-D wiring pattern
Part-D wiring pattern gives influence to all the items described in above item AC, therefore, GND wiring should be as
short as possible.

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4.5.4 SOA of DIP-IPM

The following describes the SOA (Safety Operating Area) of the DIP-IPM.
Maximum rating of IGBT collector-emitter voltage
VCES :
VCC :
Supply voltage applied on P-N terminals
VCC(surge): The add of VCC and the surge voltage generated by the wiring inductance and the DC-link capacitor.
VCC(PROT) : DC-link voltage that DIP-IPM can protect itself.

Collector current Ic

VCES
VCES

VCC(PROT)

VCE=0IC=0

VCC(PROT)

Short-circuit current

VCE=0IC=0
2s

Figure 35. SOA for Switching and Short-circuit

In Case of switching
VCES represents the maximum voltage rating (600V) of the IGBT . By subtracting the surge voltage (100V or less)
generated by internal wiring inductance from VCES is VCC(surge), that is 500V. Furthermore, by subtracting from VCC(surge)
the surge voltage (50V or less) generated by the wiring inductor between DIP-IPM and DC-link capacitor is VCC, that is
450V.
In Case of Short-circuit
VCES represents the maximum voltage rating (600V) of the IGBT . By Subtracting the surge voltage (100V or less)
generated by internal wiring inductor from VCES is VCC(surge), that is, 500V. Furthermore, by subtracting from VCC(surge the
surge voltage (100V or less) generated by the wiring inductor between the DIP-IPM and the electrolytic capacitor is
VCC, that is, 400V.

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4.5.5 Repetition of Short Circuit Protection

A repetition of SC protection behaving as protectionrestartprotectionrestart will result a repeated temperature
change of IGBT (Tj), therefore shorten the device life-cycle expectancy. Figure 36 shows typical power cycles of
DIP-IPM. Short circuit protection function only protects DIP-IPM itself from non-repeated short-circuit. Therefore, it is
necessary to stop IGBT when there is Fo output.
1.0E+07

1%
10%
0.1%

Power cycle

1.0E+06

1.0E+05

1.0E+04

1.0E+03
10

100

1000

Junction temperature variation Tj()

Figure 36. Power cycle

The graph is drawn based on the data at 3 points of Tj=46, 88, 98. It illustrates each failure rate of 0.1, 1, 10% in
respective regression line.

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4.6 Fault Output Circuit

Item
Fault output supply voltage
Fault output current

Item
Fault output voltage

Table 20. Maximum Ratings

Condition
Applied between Fo-VNC
Sink current of Fo terminal

Symbol
VFO
IFO

Symbol
VFOH
VFOL

Ratings
-0.5VD+0.5
1

Table 21. Electric Characteristics

Condition
Min.
VSC=0VFo=10k,5V pulled-up
4.9
VSC=1VFo=1mA

Typ.

Unit
V
mA

Max.

0.95

Unit
V
V

Because Fo terminal is an open collector type, it should be pulled up to 5V or 15V level via a pull-up resistor. The
resistor has to satisfy the above specifications.

5V

0.3
0.25

Ro

VFo(V)

0.2

Fo

0.15

MCU

DIP-IPM

0.1
0.05

GND

VNC

0
0

0.2

0.4

0.6

0.8

IFO(mA)

Figure 37. Voltage-current characteristics of Fo terminal

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Figure 38 Fo terminal wiring

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4.7 Guidelines for Control Supply

4.7.1 Timing Charts of Under-Voltage Protection (Figure 39, 40)
(1)Under-Voltage Protection (N-side, VD)
a1. Control supply start up . IGBT begin operation after VD rises to VDr
a2. Normal operation : IGBT ON and carrying current
a3. Under-voltage trip (UVDt)
a4. IGBT turns OFF inspite of control input condition.
a5. Fo timer operation starts.
a6. Under-voltage reset (UVDr)
a7. Normal operation : IGBT ON and carrying current
Control input

Protection circuit state

RESET

Control supply voltage VD

a1

SET

RESET

UVD r
a6

UVD t

a3

a2

a4

a7

Output current Ic(A)

Keeping high-level output
a5

Error output Fo

Figure 39. Timing Chart for N-side UV Operation

Note: All three-phase N-side IGBTs will be interrupted concurrently if N-side UV happened.

Under-Voltage Protection (P-sideVDB)

a1. Control supply start up. IGBT begin operation after VDB rises to VDBr.
a2. Normal operation : IGBT ON and carrying current
a3. Under-voltage trip (UVDBt)
a4. IGBT OFF inspite of control input condition, but there is no Fo signal output.
a5. Under-voltage reset (UVDBr)
a6. Normal operation : IGBT ON and carrying current
Control input

Protection circuit state

SET

RESET

RESET

UVDB r
Control supply voltage VDB

a1

UVDB t

a2

a5
a3
a4

a6

Output current Ic(A)

Keeping high-level output (No Fo output)
Error output Fo

Figure 40. Timing Chart for P-side UV Operation

Note: Only the IGBT of the phase with P-side UV failure will be interrupted; other IGBTs will not be stopped.

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4.7.2 Other Guidelines

Table 22 describes DIP-IPM state corresponding to various control supply. The ripple included control voltage should
meet the specification.
Table 22. DIP-IPM state corresponding to control supply voltage
Range of control supply
voltageVDVDB

State

04.0

It is almost the same as no power supply.

External noise may cause DIP-IPM malfunction (turns ON).
Supply under-voltage protection will not operate and no Fo signal
will be asserted.

4.012.5

Even if control input signals are applied, IGBT does not work
Supply under-voltage protection starts operation and outputs Fo
signals.

12.513.5

Switching operation works. However, this value is below the

recommended one, VCE(sat) and switching time will be out of the
specified values, it may increase collector dissipation and junction
temperature.

13.516.5

(for VD)

13.518.5

(for VDB)

16.520

(for VD)

18.520

(for VDB)

20.0

Recommended values.

Switching operation works. This range, however, is over the

recommended value, thus, too fast switching speed might cause the
The control circuit will be destroyed.

Note: UV fault signals are asserted only for VD supply.

(1) Specifications for Ripple Noise

If high frequency noise is imposed on the control IC supply line, it may cause IC a malfunction and assert an error
fault signal. To avoid such malfunction, the supply circuit should be designed such that the noise fluctuation is
limited within 1V/s, and the ripple voltage is less than 2V.
Specification dV/dt1V/s, Vripple2Vp-p

(2) UV filter
When control supply voltage falls down, IGBT will turn OFF ignoring the input signal. It will take about 10sec to
keep on interrupting the gate after receiving an set signal because there is a built-in 10sec filter (standard).

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4.8 Power Loss and Thermal Dissipation Design

4.8.1 Power Loss Calculation (Example)
Simple expressions for calculating average power loss
Scope
In preparation for applying the DIP-IPM in VVVF inverter, it is possible to calculate overall loss in normal
operation in order to select (or compare) power modules. This calculation, however, cannot be applied
to thermal design under extreme conditions.
Assumptions
Sine waveform current output PWM control VVVF inverter
PWM signals generated by the comparison of sine waveform and triangular waveform.
Duty amplitude of PWM signals varies within the range:

1 D 1+ D

(%/100)
2
2

Output current is given by Icpsinx and it does not have ripple.

Load power factor for output current is cos, while ideal inductive load is assumed for switching.
IGBT saturation voltage VCE(sat) is in proportion to the collector current Ic.
Forward voltage drop of free-wheeling diode VEC is in proportion to the forward current IEC.
Switching losses PSW(on) and PSW(off) are in proportion to the collector current.
Reverse current of free-wheeling diode is constant regardless of the forward current IEC.
Expressions
Static loss of IGBT

1 D
Icp Vce( sat )(@ Icp) ( +
cos )
8 3
Dynamic loss of IGBT

( Psw(on) + Psw(off )) fc

Static loss of free-wheeling diode

1 D
Iecp Vec(@ Ifp = Icp) (
cos )
8 3
Dynamic loss of free-wheeling diode

1
( Irr Vcc trr fc)
8
Expressions Derivation
For the time t, duty ratio of PWM signals is represented by

1 + D sin t
. This corresponds to the
2

change of output voltage. Thus, with the power factor cos i ndicating the relationship between output
current and voltage, the expressions to calculate output current and PWM duty will be derived as follows:

Outputcurrent = Icp sin x

1 + D sin(t + )
PWMDuty =
2

Thus, VCE(sat) and VEC at the phase x for linear approximation is calculated by:

Vce( sat ) = Vce( sat )(@ Icp) sin x

Vec = Vec(@ Iecp = Icp)(1) sin x

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Thus, the static loss of transistor is calculated by:

1 + D sin( x + )
dx
2
1
1 + D sin( x + )
= Icp Vce( sat )(@ Icp)
dx
( Icp sin 2 x)

2 0
2
1 D
= Icp Vce( sat )(@ Icp) +
cos
8 3

1
2

( Icp sin x) Vce( sat )(@ Icp)

Similarly, the static loss of free-wheeling diode is calculated by:

1
2

((1) Icp sin x) ((1) Vec(@ Icp) sin x)

1 + D sin( x + )
dx
2

1 D
cos )
= Icp Vec(@ Icp) (
8 3
On the other hand, the dynamic loss of transistor, which does not depend on PWM duty, is calculated by:

1
2

( Psw(on)(@ Icp) + Psw(off )(@ Icp)) sin x fcdx

= ( Psw(on)(@ Icp) + Psw(off )(@ Icp)) fc

If dynamic loss of free-wheeling diode is idealized as shown in Figure 41, it is calculated by:
trr
Iec
Vec
time

Irr
Vcc

Figure 41. FWDi Dynamic Loss

Psw =

Irr Vcc trr

(const.)
4

Recovery occurs in the middle of output current period. Thus, the dynamic loss is calculated by:

Irr Vcc trr

1
fc
4
2
1
( Irr Vcc trr fc )
8

Guidelines for applying the power loss expressions in inverter designs

Divide the output current period into fine-steps and calculate the losses at each step based on the
actual values of : PWM duty; output current; the values of VCE(sat), VEC, Psw corresponding to the output
current.
PWM duty depends on the way of generating signals.
The relationship between output current waveform or output current and PWM duty changes depending
on the way of generating signals, load, and other various factors. Thus, calculation should be
performed based on actual waveforms.
VCE(sat) and Psw(on, off) should be the value at Tj=125.

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4.8.2 Temperature Rise Considerations and Calculation Example

The result of loss calculation using the typical characteristics is shown in Figure 42 as Effective current versus carrier
frequency characteristics.
Conditions: VCC=300V, VD=VDB=15V, VCE(sat)=Typ., Switching loss=Typ., Tj=125, Tf=100,Rth(j-f)=Max., P.F=0.8, 3-phase
PWM modulation, 60Hz sine waveform output

PS21869
PS21867
PS21865

10
Io[Arms]

Allowable effective current Io (Arms)

100

PS21564
PS21563
PS21562

1
1

10

100

Carrier frequency
f [KH ] fc(kHz)

Figure 42. Effective currentcarrier frequency characteristics

Note:
The above characteristics may vary in the different control schemes and motor drive types.

Figure 43 indicates an example of an inverter operated under the condition of Tf=100. It indicates the effective
current Io which can be outputted when the junction temperature Tj rises to the average junction temperature of
125 (up to which the DIP-IPM operates safely).

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4.9 Noise Withstand Capability

4.9.1 Evaluation Circuit
In noise test of DIP-IPM, 2.0kV or much high withstand capability has been confirmed under the conditions given in
Figure 43. However, noise withstand capability greatly depends on the test conditions, the wiring patterns of control
substrate, parts layout, and other factors; therefore a confirmation on prototype is necessary.

Heat sink
C1

R
Breaker
3-phase 200V

U
V
W

DIP-IPM
T

FO

Voltage slider
I/F

Control supply
(15V single power-source)
Isolation
transformer

Inverter

Noise simulator

DC supply
AC100V

Figure 43. Noise test circuit

Note:
C1 AC line common-mode filter 4700pF
PWM signals are inputted from microcomputer both directly and through opto-coupler
15V single power-source drive
Test is performed for both IM and DCBLM motors
Test conditions
VCC=300V, VD=15V, Ta=25, no load
Scheme to apply noise : From AC line (R, S, T), Period T=16ms, Pulse width tw=0.051s, input in
random.

4.9.2 Countermeasures and Precautions

DIP-IPM improves noise withstand capabilities by means of reducing parts quantity, lowering inductance by the
internal wiring optimization, and reducing leakage current by the isolation structure optimization.
Noise countermeasures implemented outside the DIP-IPM:
For malfunction caused by external noise over-current
Improving power supply filtering (close to DIP-IPM terminals)
Lowering impedance of input parts (reducing pull-up resistance)
Connecting filter between input parts and GND (bypassing noise)

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4.9.3.Surge Withstand Capability

LVIC

R=0

C=200pF

V
UN
VN
WN

Figure 44. Surge Test circuit(Vterminal)

HVIC

R=0
VP1

C=200pF

UP

VP

VUFB
VG

VUFS

Figure 45. Surge Test circuit(VPterminal)

For surge test of DIP-IPM, 1.0kV or more withstand capability has been confirmed under the conditions given in
Figure 44,45.

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CHAPTER 5

ADDITIONAL GUIDELINES

5.1 Packaging Specification

(44)
(22)

Plastic tube

Per tube
DIP-IPM

(520)

6 pieces of DIP-IPM per tube

5 columns
of tube

10 pieces of Mini DIP-IPM per tube

Per package box (Max.)

6 rows
of tube

Partition

(250)

DIP-IPM
Total number of tubes is 20.
(5 columns4 rows)
Total number of DIP-IPMs is 120.
(20 tubes6 pieces)
Mini DIP-IPM
Total number of tubes is 32.
(4 columns8 rows)
Total number of DIP-IPMs is 320.
(32 tubes10 pieces)

Weight
DIP-IPM
Approximately 65g Per DIP-IPM
Approximately 490gPer tube
(180)

Approximately 11kg

Per package

Mini DIP-IPM
Approximately 20gPer MiniDIP-IPM
Approximately 310g Per tube

Spacer

Per package

The above weights are ones when the

maximum number of DIP-IPMs are
packaged.

(600)

Package box

Approximately 12kg

Figure 46. DIP-IPM Packaging Specification

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5.2 Attention for Handling

Transportation

Put package boxes in the correct direction. Putting them upside down, leaning them or
giving them uneven stress might cause electrode terminals to be deformed or resin case
to be damaged.
Throwing or dropping the packaging boxes might cause the devices to be damaged.
Wetting the packaging boxes might cause the breakdown of devices when operating.
Pay attention not to wet them when transporting on a rainy or a snowy day.

Storage

We recommend room temperature and humidity in the ranges 535 and 4575,
respectively, for the storage of modules. The quality or reliability of the modules might
decline if the storage conditions are much different from the above.

Long storage

When storing modules for a long time (more than one year), keep them dry. Also, when
using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on
their exterior.

Surroundings

Keep modules away from places where water or organic solvent may attach to them
directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They
might cause serious problems.

Disposal

The epoxy resin and the case materials are made of approved products in the UL
standard 94-V0, still they are incombustible.

Static electricity

Exclusive ICs of MOS gate structure are used for the DIP-IPM power modules. Please
keep the following notices to prevent modules from being damaged by static electricity.
1Notice of breakdown by static electricity
Excessively high voltage (over the Max. rated input terminal voltage) resulting from the
static electricity of human bodies and packaging materials, might cause the modules to
be damaged if applied on the control terminals. For countermeasures against static
breakdown, it is important to control the static electricity as much as possible and when
it exists, discharge it as soon as possible.
Do not use containers which are easy to be electro-statically charged during
transportation.
Be sure to short the control terminals with carbon cloth, etc. just before using the
module. Also, do not touch between the terminals with bare hands.
During assembly (after removing the carbon cloth, etc.), earth machines used and
human bodies. We suggest putting a conductive mat on the surface of the operating
table and the surrounding floor.
When the terminals on the printed circuit board with mounted modules are open, the
modules might be damaged by static electricity on the printed circuit board.
When using a soldering iron, earth its tip.
2Notice when the control terminals are open
When the control terminals are open, do not apply voltage between the collector and
emitter.
Short the terminals before taking a module off.

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Notice for Safe Designs

We are making every effort to improve the quality and reliability of our products. However, there are
possibilities that semiconductor products be damaged or malfunctioned. Pay much attention to take
safety into consideration and to adopt redundant, fireproof and malfunction-proof designs, so that the
breakdown or malfunction of these products would not cause accidents including human life, fire, and
social damages.

Notes When Using This Specification

This specification is intended as reference materials when customers use semiconductor products of
Mitsubishi Electric. Thus, we disclaim any warranty for exercise or use of our intellectual property rights
and other proprietary rights regarding the product information described in this specification.

We assume absolutely no liability in the event of any damage and any infringement of third partys
rights arising from the use of product data, diagrams, tables, and application circuit examples
described in this specification.

All data including product data, diagrams, and tables described in this specification are correct as of
the day it was issued, and they are subject to change without notice. Always verify the latest
information of these products with Mitsubishi Electric and its agents before purchase.

The products listed in this specification are not designed to be used with devices or systems, which
would directly endanger human life. Should you intend to use these products for special purposes such
as transportation equipment, medical instruments, aerospace machinery, nuclear-reactor controllers,
fuel controllers, or submarine repeaters, please contact Mitsubishi Electric and its agents.

Regarding transmission or reproduction of this specification, prior written approval of Mitsubishi Electric
is required.

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DIP-IPM

DPH2588eB
(46/46)

Application Note