Lecture 5, Transistor matching and good

layout techniques

18-Mar-08

Transistor mismatch & Layout techniques

1. Transistor mismatch its causes
and how to estimate its magnitude
2. Layout techniques for good
matching
3. Layout techniques to minimize
parasitic effects

Part 1: Device Matching

(especially transistor matching)

Neuromorphic Engineering 2
Spring 08
Delbruck/Indiveri/Liu

Transistor matching data

From Brad Minch, formerly Cornell, now at Olin Tech
Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Inst. of Microelectronics, Sevilla, Spain

Statistical rule for matching

(aka Pelgroms rule)
Zero order rule:
(X is some quantity like VT)

(X ) =

AX
WL

1. The variance goes as 1/area, i.e., goes as

1/dimension
2. Only applies for local, identically-drawn neighbors.
3. There are many refinements to account for spatial
locality, large scale effects (tilt), etc.
4. Statistical transistor models try to model individual
parameter variations, e.g. VT, , , W/L

Small transistors Big mismatch

1. All devices follow
area rule

(Inter-die)

2. Caps match 1-2

decades better
than FETs
3. pfets match worse
than nfets (usually)
Notes: Gradient and
border effects are
removed here. I0
exp(-VT) and VT
has normal
distribution

JSSC, 39:1, 2004 p157-168 Gyvez, Tuinhout,

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch

Lecture 5, Transistor matching and good

layout techniques

Dominant cause of FET mismatch is random

dopant fluctuation

18-Mar-08

Magnitude of VT mismatch
(VT ) =

AVT
WL

, what is AVT ?

AVT is reported to be ~1 mV*um per nm

oxide thickness (JSSC, 39:1, 2004 p157-

Cheng, Roy, Asenov ESSCIRC 2003

Weak inversion mismatch

168)
Example: 0.35um process with Tox=7nm,
AVT=7mV*um.
FET with W=L=2um
(With =0.2um, this is 10/10 ),
(VT)=7mV*um/sqrt(2um*2um)=3.5mV
Minch measured value is 2.4mV

Mismatch is almost constant in weak inversion

(VT )

0.35u process

(log I ds )

To zero order, weak inversion mismatch goes as

( I ds )
I ds

(VT )
= (log I ds ) = exp

UT

It is reported that weak inversion (sometimes) has

additional mismatch not accounted for by (VT)
Ids
Serrano-Gotarredeno, Linares-Barranco 2000

Ids

Mismatch process scaling

Reducing mismatch by design

Objectives:
Good event-threshold uniformity
Fast response under wide illumination range

I0

I0

A
1. From 1.2u to 0.35u, FETs with same dim have same
mismatch. (not true for deeper submicron, gets worse).
2. Cap matching depends on absolute size.

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch

random variation

logI

Lecture 5, Transistor matching and good

layout techniques

18-Mar-08

Use unit devices: e.g. for capacitor matching

Part 2: Layout for good device

matching

e.g. 3:1 capacitor

ratio

Not
very
precise

Much better
(if you can
afford it)

Put devices as nearby as possible

E.g. Matching resistors

Use same orientation: e.g.

diff pair/current mirror

Use common-centroid to cancel

gradients: e.g. diff pair with common
centroid transistors

better
Even better:
1. Use dummy devices on ends
2. Use common centroid

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch

Lecture 5, Transistor matching and good

layout techniques

Surroundings affect matching

18-Mar-08

Use dummy devices to create identical

local surroundings

Relative
capacitance

Minch et al. ISCAS 1996

Checklist of Matching Techniques

1. Same dimensions
2. Same structure (do not match nFETs with
pFETs)
3. As large as possible
4. Close to one another
5. Same orientation
6. Laid out in a common-centroid arrangement
7. Surrounding circuits should be similar
8. Same temperature

Layout Techniques for Good Performance

Part 2: General layout techniques

Latchup: avoid it by using lots of substrate

and well contacts

Every node has a parasitic capacitance and

resistance
Layout of mixed analog and digital circuits
should be carefully planned to minimize parasitic
effects and undesirable coupling
Digital circuits should have their own power
supply lines.
Digital ground should not be connected to
the substrate!

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch

Lecture 5, Transistor matching and good

layout techniques

18-Mar-08

Shielding from substrate noise

Never connect digital ground to the substrate

V=LdI/dt noise on digital ground yanks around local
substrate. This can move backgate on analog FETs,
severely affecting them.

Digital circuit
Analog circuit

Lab exercise LVS

Layout vs. Schematic

Shielding from minority carriers

Steps for LVS exercise

1.
2.
3.
4.
5.
6.

Draw schematic/simulate
Draw layout
Extract schematic and layout to SPICE netlist
Run LVS tool to compare netlists
Interpret output to spot differences
Fix layout (or maybe schematic) iterate to 3.

Note: LVS has many options, e.g. check transistor

geometry, check R & C values, collapse
stacked logic you need to make sure you are
using reasonable options

Papers about transistor mismatch

1.
2.
3.
4.
5.

6.
7.

8.

9.

Lecture 5, Transistor matching and good

layout techniques, http://avlsi.ini.uzh.ch

Lakshmikumar, K.R. Hadaway, R.A. Copeland, M.A. Characterisation and modeling of mismatch in MOS
transistors for precision analog design, IEEE J. Solid-State Circuits 1986, 21:6, p 1057-1066
M. J. M. Pelgrom, A. C. J. Duinmaiger, and A. P. G. Welbers, Matching properties of MOS transistors for
precision analog design, IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
Aleksandra Pavasovi, Andreas G. Andreou and Charles R. Westgate, Characterization of subthreshold MOS
mismatch in transistors for VLSI systems, Analog Int. Circuits and Signal Processing, 1994, 6:1, p 75-85
Forti, F. Wright, M.E. Measurement of MOS current mismatch in the weak inversion region, IEEE J. SolidState Circuits 1994, 29:2, p 138-142
T. Mizuno, J. Okamura, A. Toriumi, "Experimental Study of Threshold Voltage Fluctuation due to statistical
variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. ED-41, pp. 2216-2221,
1994.
Teresa Serrano-Gotarredona and Bernab Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch
Model," IEEE Electron Device Letters, vol. 21, No. 1, pp. 37-39. January 2000. (PDF 144K, 3 pages)
Teresa Serrano-Gotarredona and Bernab Linares-Barranco, "Systematic Width-and-Length Dependent CMOS
Transistor Mismatch Characterization and Simulation," Analog Integrated Circuits and Signal Processing,
Kluwer Academic Publishers, December 1999. (PDF 1.4M, 26 pages)
T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for Short Channel MOS
Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp. 440-443,
1999. (PDF 266K, 4 pages)
The matching of small capacitors for analog VLSI, Minch et. Al. ISCAS 1996 p 239-241