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FSBB20CH60
TM
General Description
Applications
AC 100V ~ 253V three-phase inverter drive for small power
ac motor drives
Home appliances applications like air conditioner and washing machine.
Top View
Bottom View
44mm
26.8mm
Figure 1.
FSBB20CH60 Rev. C
www.fairchildsemi.com
April 2005
Pin Configuration
Top View
13.7
(1) VCC(L)
(2) COM
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) VFO
(7) CFOD
(8) CSC
(21) NU
(22) NV
19.2
(23) NW
(9) IN(UH)
(10) VCC(UH)
(11) VB(U)
(12) VS(U)
(13) IN(VH)
(14) VCC(VH)
(15) VB(V)
(16) VS(V)
(17) IN(WH)
(18) VCC(WH)
(19) VB(W)
(24) U
(25) V
(26) W
DBC Substrate
(27) P
(20) VS(W)
Figure 2.
FSBB20CH60 Rev. C
www.fairchildsemi.com
Pin Descriptions
Pin Number
Pin Name
Pin Description
VCC(L)
COM
IN(UL)
IN(VL)
IN(WL)
VFO
CFOD
CSC
Fault Output
IN(UH)
10
VCC(UH)
11
VB(U)
12
VS(U)
13
IN(VH)
14
VCC(VH)
15
VB(V)
16
VS(V)
17
IN(WH)
18
VCC(WH)
19
VB(W)
20
VS(W)
21
NU
22
NV
23
NW
24
25
26
27
FSBB20CH60 Rev. C
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(19) V B(W )
(18) V CC(W H )
(17) IN (W H)
(20) V S(W )
(15) V B(V)
(14) V CC(VH)
(13) IN (VH)
(16) V S(V)
(11) V B(U)
(10) V CC(UH)
(9) IN (UH)
(12) V S(U)
(8) C SC
(7) C FO D
(6) V FO
(5) IN (W L)
(4) IN (VL)
(3) IN (UL)
(2) CO M
(1) V CC(L)
P (27)
VB
VCC
COM
IN
OU T
VS
W (26)
VB
VCC
COM
IN
OU T
VS
V (25)
VB
VCC
OU T
COM
IN
C(SC)
VS
U (24)
OUT(W L)
C(FOD)
N W (23)
VFO
IN(W L) OUT(VL)
IN(VL)
N V (22)
IN(UL)
COM
VCC
OUT(UL)
VSL
N U (21)
Note:
1. Inverter low-side is composed of three IGBTs, freewheeling diodes for each IGBT and one control IC. It has gate drive and protection functions.
2. Inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals.
3. Inverter high-side is composed of three IGBTs, freewheeling diodes and three drive ICs for each IGBT.
Figure 3.
FSBB20CH60 Rev. C
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Inverter Part
Symbol
VPN
VPN(Surge)
VCES
Parameter
Conditions
Rating
Units
Supply Voltage
450
500
600
20
Collector-emitter Voltage
IC
TC = 25C
ICP
40
PC
Collector Dissipation
61
TJ
(Note 1)
-20 ~ 125
Note:
1. The maximum junction temperature rating of the power chips integrated within the SPM is 150 C(@TC 100C). However, to insure safe operation of the SPM, the average
junction temperature should be limited to TJ(ave) 125C (@TC 100C)
Control Part
Symbol
Parameter
Conditions
Rating
Units
VCC
20
VBS
20
VIN
-0.3~17
VFO
IFO
VSC
-0.3~VCC+0.3
mA
-0.3~VCC+0.3
Total System
Symbol
VPN(PROT)
TC
Parameter
Conditions
TSTG
Storage Temperature
VISO
Isolation Voltage
Rating
Units
400
-20 ~ 100
-40 ~ 125
2500
Vrms
Thermal Resistance
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Junction to Case Thermal
Resistance
Condition
Min.
1.63
C/W
2.55
C/W
Note:
2. For the measurement point of case temperature(TC), please refer to Figure 2.
FSBB20CH60 Rev. C
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Inverter Part
Symbol
VCE(SAT)
VF
HS
Parameter
IC =20A, TJ = 25C
VIN = 0V
IC = 20A, TJ = 25C
Switching Times
Collector-Emitter
Saturation Voltage
Min.
Typ.
Max.
Units
2.3
2.1
0.48
0.30
0.93
tC(OFF)
0.52
trr
0.10
tON
tC(ON)
tOFF
LS
Conditions
tON
tC(ON)
tOFF
tC(OFF)
trr
ICES
Collector-Emitter
Leakage Current
VCE = VCES
0.63
0.30
1.01
0.51
0.10
250
Note:
3. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally.
For the detailed information, please see Figure 4.
100% IC 100% I C
trr
V CE
IC
IC
V CE
V IN
V IN
t ON
t OFF
t C(ON)
V IN(ON)
V IN(OFF)
tC(OFF)
10% V CE
10% I C
(b) turn-off
(a) turn-on
FSBB20CH60 Rev. C
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Control Part
Symbol
IQCCL
Parameter
Quiescent VCC Supply
Current
IQCCH
IQBS
VFOH
VFOL
Conditions
Min.
Typ.
Max. Units
VCC = 15V
IN(UL, VL, WL) = 0V
VCC(L) - COM
23
mA
VCC = 15V
IN(UH, VH, WH) = 0V
100
VBS = 15V
IN(UH, VH, WH) = 0V
500
4.5
0.8
VSC(ref)
0.45
0.5
0.55
UVCCD
Detection Level
10.7
11.9
13.0
Reset Level
11.2
12.4
13.2
Detection Level
10.1
11.3
12.5
UVCCR
UVBSD
UVBSR
Reset Level
10.5
11.7
12.9
tFOD
1.0
1.8
ms
VIN(ON)
ON Threshold Voltage
3.0
VIN(OFF)
0.8
Note:
Parameter
Conditions
Value
Min.
Typ.
Max.
Units
VPN
Supply Voltage
300
400
VCC
13.5
15
16.5
VBS
13.0
15
18.5
-1
V/s
2.5
20
kHz
fPWM
VSEN
-4
FSBB20CH60 Rev. C
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Parameter
Mounting Torque
Device Flatness
Limits
Conditions
Mounting Screw: - M3
Typ.
0.51
0.62
0.72
Nm
+120
15.00
Recommended 0.62Nm
Note Figure 5
Weight
Max.
Units
Min.
(+)
(+)
FSBB20CH60 Rev. C
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Input Signal
Protection
Circuit State
RESET
SET
RESET
UVCCR
a1
Control
Supply Voltage
a6
UVCCD
a3
a2
a7
a4
Output Current
a5
a1 : Control supply voltage rises: After the voltage rises UVCCR, the circuits start to operate when next input is applied.
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under voltage detection (UVCCD).
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts.
a6 : Under voltage reset (UVCCR).
a7 : Normal operation: IGBT ON and carrying current.
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVBSR
Control
Supply Voltage
b1
UVBSD
b5
b3
b6
b2
b4
Output Current
High-level (no fault output)
FSBB20CH60 Rev. C
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c6
Protection
circuit state
SET
Internal IGBT
Gate-Emitter Voltage
c3
Lower arms
control input
c7
RESET
c4
c2
SC
c1
c8
Output Current
SC Reference Voltage
Sensing Voltage
of the shunt
resistance
Fault Output Signal
c5
CR circuit time
constant delay
FSBB20CH60 Rev. C
10
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5V-Line
R PF =
SPM
4.7k
CPU
IN (UL) , IN (VL) , IN (W L)
100
1nF
VFO
C PF =
1nF
COM
Note:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the applications
printed circuit board. The SPM input signal section integrates 3.3k(typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
2. The logic input is compatible with standard CMOS or LSTTL outputs.
15V-Line
R E(H)
R BS
D BS
P
22uF
0.1uF
Vcc
VB
IN
HO
COM VS
Inverter
Output
Vcc
1000uF
1uF
IN
OUT
COM VSL
Note:
1. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
2. The bootstrap resistor (RBS) should be 3 times greater than RE(H). The recommended value of RE(H) is 5.6, but it can be increased up to 20 (maximum) for a slower dv/dt of
high-side.
3. The ceramic capacitor placed between VCC-COM should be over 1F and mounted as close to the pins of the SPM as possible.
FSBB20CH60 Rev. C
11
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RE(VH)
15V line
RE(UH)
RBS
DBS
(19) VB(W)
(18) VCC(WH)
CBS
Gating WH
CBSC
(17) IN(WH)
(20) VS(W)
RBS
DBS
(15) VB(V)
(14) VCC(VH)
CBS
Gating VH
C
P
U
CBSC
(13) IN(VH)
(16) VS(V)
RBS
DBS
(11) VB(U)
(10) VCC(UH)
CBS
Gating UH
(9) IN(UH)
(12) VS(U)
5V line
Fault
CBSC
RS
VCC
OUT
COM
IN
W (26)
VS
VB
VCC
OUT
COM
IN
VS
V (25)
VB
VCC
CDCS
OUT
COM
IN
Vdc
U (24)
VS
RF
(8) CSC
CSC
RPF
(7) CFOD
CFOD
(6) VFO
(5) IN(WL)
Gating WL
(4) IN(VL)
Gating VL
(3) IN(UL)
Gating UL
CBPF
P (27)
VB
(2) COM
CPF
(1) VCC(L)
CSP15
C(SC) OUT(WL)
C(FOD)
NW (23)
RSW
VFO
IN(WL) OUT(VL)
IN(VL)
NV (22)
RSV
IN(UL)
COM
OUT(UL)
VCC
VSL
NU (21)
RSU
CSPC15
RFW
W-Phase Current
V-Phase Current
U-Phase Current
RFV
RFU
CFW
CFV
CFU
Note:
1. To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm)
2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible.
3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7k resistance. Please refer to Figure 9.
4. CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended.
5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin7) and COM(pin2). (Example : if CFOD = 33 nF, then tFO = 1.8ms
(typ.)) Please refer to the note 5 for calculation method.
6. Input signal is High-Active type. There is a 3.3k resistor inside the IC to pull down each input signal line to GND. When employing RC coupling circuits, set up such RC couple
that input signal agree with turn-off/turn-on threshold voltage.
7. To prevent errors of the protection function, the wiring around RF and CSC should be as short as possible.
8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 1.5~2 s.
9. Each capacitor should be mounted as close to the pins of the SPM as possible.
10. To prevent surge destruction, the wiring between the smoothing capacitor and the P&GND pins should be as short as possible. The use of a high frequency non-inductive
capacitor of around 0.1~0.22 F between the P&GND pins is recommended.
11. Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays.
12. CSPC15 should be over 1uF and mounted as close to the pins of the SPM as possible.
FSBB20CH60 Rev. C
12
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RE(WH)
FSBB20CH60 Rev. C
13
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FSBB20CH60 Rev. C
14
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FSBB20CH60 Rev. C
15
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
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Product Status
Definition
Advance Information
Formative or In
Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I15
16
FSBB20CH60 Rev. C
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