Microelectronics Packaging 1

The Electronics and

Semiconductor Industry in the
Philippines

Engr. Enrico Claro R. Delmoro, PECE

26 July 2009

Evolution and Challenges in Electronics/Semiconductor Industry

Microelectronics
Packaging and
Assembly

- Electronics and Semiconductor Industry in the Philippines

- Microelectronics Revolution
- Semiconductor Devices
Trends in Microelectronics Packaging
- Primary Functions
- Considerations in Package Selection
- Assembly and Test Processes

At the heart of the communication,

information technology, consumer
electronics,
medical
and
transportation
technologies
is
microelectronics
technology.
Microelectronics Packaging is an
integral building block of it.

Medical
Telecom

Computer
Aerospace
USA

Consumer
Software, Applications

Agenda

ic
pt ies
r O lo g
be no
s
cs
F i ech
ie
ni
T
lay log
tro s
isp no
lec ie
D ech
oe log
T
icr hno
M ec
T

Transportation

Ba
tte
ry
Te
ch
M
no
Pa
a
lo
S
t o gne
T e c ka
gi
r
es
a ti
ch gi
no ng ge T c/O
lo
ec pti c
gi
hn al
es
ol
og
ie
s

MPA

Inside A Cell Phone

Electronics and Semiconductor Industry in the Philippines

(Export Value in Billion Dollars as of 2007)

Nokia Cellular Phone

31

35

29.6
27.3
27.07
26.64
25.34
24.17
23.76
21.6
19.87

30
25
20

14.98
15

10.61
10

7.55
4.89
5 2.97 3.78
0
1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

Sources: National Statistics Office

Bureau of Export Trade Promotion, DTI

Inside a Cell Phone

Electronics and Semiconductor Industry in the Philippines

(Distribution of Employment as of 2007)

Other Electrical
Equipment
3%
Computer and
Peripherals
Equipment
7%

Plastic Products
3%
Mens and Boys
Garment
3%

Women, Girl and

Babies Garments
7%

Semiconductor and
Electronics
12%

Other Industries
65%

Apple iPhone
Source: http://news.cnet.com/2300-1041_3-6244920-1.html?tag=mncol
Sources: National Statistics Office
Bureau of Export Trade Promotion, DTI

Electronics and Semiconductor Industry in the Philippines

Electronics and Semiconductor Industry in the Philippines

(Total Employment as of 2007)

460

500

438

450

402
376

400
350

315 307

335 346

280

300

Chip Equipment SME

Fab P rocess Development

Materials SME

Sort Test Development

Software SME

Package and Assembly Development

Instrumentation SME

Final Test Development

Systems Development

250
250

Our activities in the value chain

Chip Design

Source : The Bitter Pill Building a New Philippine

Semiconductor and Electronics Industry Through Technical
Competencies Enhancement by Lito Zulaybar

Software Development

220

200

160

150

Fab Manufacturing

120

90
100 74 80

Sort Manufacturing

Assembly Manufacturing

50

Test Manufacturing

0
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
Sources: Philippine Board of Investments (BOI) &
Philippine Economic Zone Authority (PEZA)

Electronics and Semiconductor Industry in the Philippines

COMPONENTS AND DEVICES

ELECTRONIC SUB-ASSEMBLIES

Core 2 Duo, DSPs, ASIC, DRAM, SRAM ,Flash

Transistors, Diodes, Resistors, Coils,
Capacitors, Transformers, Lead Frames

Hard Disk Drives, Floppy Disks

DVD/CD ROM, Motherboards, LCD Panels
PSU, UPS, Solar Panels

CONSUMER ELECTRONICS

TELECOMMUNICATIONS

TV Sets, Electronic Games, Radio Cassette

Players, Karaoke Machines,
VCD/DVD Players

Telephones, Pagers, VHF,UHF Radios,

Cellular Phones, Scanners,
Satellite Receivers

PC/OFFICE EQUIPMENT

COMMUNICATIONS AND RADAR

Personal Computers, Photocopy Machines and Parts,

Electronic Calculators

Pagers, CCTV, Radar Detectors,

Marine and Land Mobile Radios,
CB Transceivers

CONTROL & INSTRUMENTATION

MEDICAL AND INDUSTRIAL

Stepper Motor Drivers, PCB Assembly for

Instrumentation Equipment

Spiro Analyzers, Heart Implants,

Hearing Aids

Systems Manufacturing

Electronics and Semiconductor Industry in the Philippines

Too much reliance on Foreign Direct Investment

Malaysia Others
2%
8%
Singapore 2%

Taiwan
4%

Electronic Brake Systems, Car Radios

Engine Control Unit, Wiring Harness

Philippines
28%

Europe
7%

NUMBER OF FIRMS

860 FIRMS
NATIONALITY:

US
9%
Korea
10%

AUTOMOTIVE ELECTRONICS

2004

Japan
30%

72% Foreign
28% Filipino
Sources: Philippine Board of Investments (BOI) &
Philippine Economic Zone Authority (PEZA)

Source: Master Plan for Philippine Electronics Industry 1998

Electronics and Semiconductor Industry in the Philippines

Among developing nations, China has been the largest

recipient of foreign investment, averaging about $40
billion per year during the late 1990s. Membership in the
World Trade Organization will result in even higher levels.

U.S.
companies
are
shifting
manufacturing
from
Malaysia,
Philippines, Thailand, Indonesia, and
even Mexico to China. Toshiba Corp. (TOSBF
) is making its TVs on the mainland, and Sony Corp. (SNE
) is manufacturing its PlayStations there. Taiwan's
companies produce half of all their informationtechnology products in the country.
China's advantages are numerous. Its wage rates are a third
of Mexico's and Hungary's, and 5% of those in the U.S. or
Japan. China's investments in education and training are
attracting research facilities from companies such as IBM
(IBM ), Motorola (MOT ), and Microsoft (MSFT ). The
critical mass of factories, subcontractors, and specialized
vendors has created a manufacturing environment with
which few can compete. China is not just an export
platform, either; its large and expanding domestic market
is another attraction.

The Microelectronics Revolution

Microelectronics is the cornerstone of:

The problem with the industries too
much reliance on Foreign Direct
Investment (FDI) is that growth is
dependent on how much these
Multinational
Companies
(MNCs)
infuse investments into the country.

- The Consumer electronics revolution

- The Computer Revolution
- The Communication Revolution
- Internet

Competition for FDI comes not only

from China, Malaysia, Thailand and
India; but Vietnam is emerging as well.

When Everything Is Made in China, Jeffrey E. Garten,

BusinessWeek, June 17, 2002

History of the Integrated Circuit

The Microelectronics
Revolution

In 1945, Bell Labs established a group to

develop a semiconductor replacement for
the vacuum tube. The group led by William
Shockley, included, John Bardeen, Walter
Brattain and others. In 1947 Bardeen and
Brattain succeeded in creating an amplifying
circuit utilizing a point-contact "transfer
resistance" device that later became known
as a point contact transistor.
Bardeen and Brattain applied two closelyspaced gold contacts held in place by a
plastic wedge to the surface of a small slab
of high-purity germanium. The voltage on
one contact modulated the current flowing
through the other, amplifying the input signal
up to 100 times.
Source:http://www.computerhistory.org/semiconductor/timeline/1947-invention.html

History of the Integrated Circuit

History of the Integrated Circuit

In 1948, William Shockley developed the

concepts for junction transistor a more practical
form of the transistor, the point contact
transistor was difficult to produce. By 1951,
Gordon Teal grows large single crystals of
germanium and works with Morgan Sparks to
fabricate the first grown n-p-n junction transistor

History of the Integrated Circuit

On May 10, 1954, TI announced the first commercial

availability of grown-junction silicon transistors. These
first silicon transistors were constructed by cutting a
rectangular bar from a silicon crystal that was grown
from a melt containing impurities. The impurities were
chosen to produce the desired current-carrying
characteristics in the resulting transistor.
The ability to produce low cost transistors
that tolerated higher heat levels was an
important factor in the transition of
computers and other electronic equipment
from bulky vacuum-tube systems to more
compact, reliable solid-state systems.

At the Dsseldorf Radio Fair in 1953,

the German firm Intermetall unveiled
what was probably the world's first
transistor radio, more than a year
before Texas Instruments claimed
that milestone. The radio's amplifier
circuit was built around four pointcontact
transistors
made
by
Intermetall, which Herbert Matar and
businessman Jakob Michael had
founded in 1952.

History of the Integrated Circuit

The first commercial transistor radio, the Regency

TR-1, was announced on October 18 ,1954 by the
Regency Division of Industrial Development
Engineering Associates of Indianapolis, Indiana
and put on sale in November of 1954. It cost
$49.95 (the equivalent of roughly $364 in year2005 dollars) and sold about 150,000 units.
Raytheon and Zenith Electronics transistor radios
soon followed.

Source: http://en.wikipedia.org/wiki/Transistor_radio
Source: http://www.ti.com/corp/docs/company/history/tihistory.shtml

History of the Integrated Circuit

Jack Kilby designed the first Integrated Circuit

over the summer of 1958 at Texas Instruments
while most of the company was on vacation,
and it was first demonstrated on September
12, and unveiled to the public the following
spring.

History of the Integrated Circuit

In 1959 M. M. (John) Atalla and Dawon Kahng at Bell Labs achieved the first
successful insulated-gate field-effect transistor (FET).
By overcoming the surface states that
blocked electric fields from penetrating into
the semiconductor material. Investigating
thermally grown silicon-dioxide layers, they
found these states could be markedly
reduced at the interface between the
silicon and its oxide in a sandwich
comprising a layer of metal (M - the gate),
a layer of oxide (O - the insulation), and a
layer of silicon (S semiconductor). As
their prototype transistor was slow and
addressed no pressing needs of the
telephone system, it was not pursued
further at Bell Labs

Kilby succeeded in integrating electronic

components, including a transistor and other
components, onto a sliver of germanium,
which made possible low-cost high volume
manufacturing of electronic circuits.

Source: http://www.ti.com/corp/docs/company/history/tihistory.shtml

History of the Integrated Circuit

Kilby's invention had a serious drawback, the individual

circuit elements were connected together with gold wires
making the circuit difficult to scale up to any complexity.
By late 1958 Swiss-born physicist - Jean Hoerni at
Fairchild had developed a structure with N and P junctions
formed in silicon. Over the junctions a thin layer of silicon
dioxide was used as an insulator and holes were etched
open in the silicon dioxide to connect to the junctions.
Czech-born physicist - Kurt Lehovec of Sprague Electric
developed the technique of using PN junctions to
electrically isolate components.
In 1959, Robert Noyce also of Fairchild had the idea to create an integrated
circuit by combing Hoerni's and Lehovec's processes and evaporating a thin
metal layer over the circuits. The metal layer connected down to the junctions
through the holes in the silicon dioxide and was then etched into a pattern to
interconnect the circuit. The Planar Technology set the stage for complex
integrated circuits and is the process used today.

History of the Integrated Circuit

In 1960 Karl Zaininger and Charles

Meuller fabricated an insulated-gate
FET at RCA and C.T. Sah of Fairchild
built a surface-potential controlled
tetrode. Today both would be called
MOS transistors. In an MOS transistor,
the conducting region is either p-type
(making it a p-channel device) or ntype (n-channel device) material. The
latter devices are faster than p-channel
ones but more difficult to manufacture.
MOS transistors hit the commercial
market in 1964.

History of the Integrated Circuit

Moores Law

Semiconductor devices are enclosed in protective ceramic, metal or plastic

packages to prevent damage to the chip and its fragile connecting wires. Despite
this important function, packaging is one of the most neglected aspects of
semiconductor design. Many programs were delayed because the chip was too
large or consumed too much power for the designated package.
In 1965 Don Forbes, Rex Rice, and
Bryant ("Buck") Rogers at Fairchild
devised a 14-lead ceramic Dual-inLine Package (DIP) with two rows of
pins 100 mils apart that revolutionized
computer
manufacturing
by
simplifying layout and allowing
automated insertion into printed
circuit boards. Low-cost, plasticmolded DIPs dominated production
volumes by the early 1970s.

History of the Integrated Circuit

Measuring trends in semiconductor manufacturing technology

generation

In 1965, Gordon Moore director of research and development at Fairchild

Semiconductor wrote a paper for Electronics entitled cramming more
components onto integrated circuits. In the paper Moore observed that the
complexity for minimum component cost has increased at a rate of roughly a
factor of two per year. This observation became known as the Moores Law

Gate Insulator
Gate
Source

Drain

Channel Length is good measure of the development in

the semiconductor manufacturing technology
Source: http://www.computerhistory.org/semiconductor/timeline/1965-Moore.html

The number of transistors per given area of silicon will double every
2 years

The number of transistors per given area of silicon will double every
2 years (Moores Law)

This 8088 16-bit processor could

manage 1 MB of memory using an
external 20-bit address bus . The
clock frequency chosen by IBM (4.77
MHz) was fairly low, though the
processor was running at 10 MHz by
the end of its career. The 8088 was
packaged in a 40 leads Ceramic DIP
Flash Memory Semiconductor Technology scaling. A tremendous
improvement of 1/476 from 1986 to 2004.

The number of transistors per given area of silicon will double every
2 years (Moores Law)

Intel 4004:
Nov 1971
10 micron technology
2,300 transistors
108 KHz clock

The number of transistors per given area of silicon will double every
2 years (Moores Law)

The Pentium 32-bit processor

contained 3.3 Million transistors . It
has a clock frequency of 66 200
MHz and was packaged in a 320
pins Staggered Pin Grid Array
(SPGA)

The number of transistors per given area of silicon will double every
2 years

Computers become Ubiquitous

Intel Pentium 4:
June 2002
0.13 micron technology
55 Million transistors
2.40 GHz clock

The Pentium 4 was packaged in

478 pins Flip Chip-Pin Grid Array

The number of transistors per given area of silicon will double every
2 years

Intel Core 2 Duo (Conroe):

June 2006
65 nm technology
~291 Million transistors
3.00 GHz clock
Flip Clip Land Grid Array 775 pins

The Intel Codre 2 Duo processor has more

than 10,000 times as many transistors as the
Intel 8088 CPU

Reference: Ray Kurzweil, The Age of Spiritual Machines, 1999

http://en.wikipedia.org/wiki/Image:PPTExponentialGrowthof_Computing.jpg

Acceleration of Communication

Benefits of Continuous Integration

Results into the exponential improvements in:

- System performance
- Cost per function
- Power per function
- System reliability
- Size reduction

Internet: Pierre Teilhard de Chardins Noosphere?

Packaging Technology: Needs to Keep up with Moores Law

Reference: Cyberspace and the Dream of Teilhard de Chardin by John R. Mabry

Teilhard imagined a stage of evolution

characterized by a complex membrane
of information enveloping the globe and
fueled by human consciousness. It
sounds a little off-the-wall, until you think
about the Internet, that vast electronic
web encircling the Earth, running point to
point through a nerve-like constellation
of wires. We live in an intertwined world
of telephone lines, wireless satellitebased transmissions, and dedicated
computer circuits that allow us to travel
electronically from Des Moines to Delhi
in the blink of an eye.
Excerpt from : A Globe, Clothing Itself with a Brain by
Jennifer Cobb Kreisberg
These striking images are 3D hyperbolic graphs of Internet topology. They are created using the Walrus Visualization
tool developed by Young Hyun at the Cooperative Association for Internet Data Analysis (CAIDA).

The evolution of electronic assembly has reached the 3-D era. (Source: SiliconPipe)
Reference: An Alternative Approach to Circuit Design and Assembly for High Speed
Interconnections
Source: http://soccentral.com/results.asp?EntryID=10778

Packaging Technology: Transition in Semiconductor Package Types

Keys to Microelectronics Revolution

Because of their smaller size and lower

power consumption than bipolar devices,
over 99.9 percent of the microchips
produced today use MOS transistors

Keys to Microelectronics Revolution

Cheap and abundant

Amazing mechanical, chemical and
electronic properties
Probably, the materials best known to
humankind

Keys to Microelectronics Revolution

Polymers are the most interesting and versatile substances in the world of
material science offering an incredibly wide range of physical and chemical
properties.
Polymers can be viscous liquids, like silicones, or steel-like solids with high
temperature performance.
Although there are natural polymers, such as rubber, most of the thousands
of commercial products are synthesized. Our ability to design polymers with
specific properties is what makes them so useful.
Polymers are now the most critical ingredients for electronic circuitry and
packaging.

Reference: Thermoplastic Die Attach Adhesive for Today's Packaging Challenges by K.

Gilleo, T. Cinque, S. Corbett, M. Corey, C. Lee & R. Miculich

Integrated Circuit Packaging: Electrical Functions

Power Distribution
Power Supply
Ground

Microelectronics Packaging

Signal Distribution
Data ( Transmit and/or Receive)
Address
Clock
Control

Integrated Circuit Packaging: Primary Functions

Traffic Cop, which routes power, ground and signals going into and/or coming
from the die. Interconnects the die to the rest of the system as quickly and with
as little added distortion as possible.
Firefighter, which draw performance-sapping and reliability limiting heat away
from the die to be absorbed by the surrounding environment; and.
Soldier, which protects the die from mechanical stresses and other
environmental effects (moisture, contamination, etc), while creating no
stresses of its own.
Reference: Silicon Contends with Stuffed and Shrinking Packages by Brian
Dipert. June 13, 2002, Electronics Design, Strategy News

Semiconductor Packaging: Introduction

Most ICs are bonded to small IC packages.

Although it is possible to attach chips directly to boards (The method
used extensively in low-cost consumer electronics.) Placing chips in
packages enables independent testing of packaged parts, and eases
requirements on board pitch and pick and place equipment.
IC Packaging Materials
Metal
Ceramic
Plastic
Laminates (Fiberglass, Epoxy Resin)

Hermetically Sealed Semiconductor Packages.

Metal Can

Hermetically Sealed Semiconductor Package.

Ceramic
Characteristics of Ceramic packaging material
Consist of several layers of conductors separated by layers of ceramic
(Al2O3 Alumina)
Chip is placed in a cavity and bonded to the conductors

Cap

Metal lid soldered on the package

Hermetically sealed against the environment
Base
Metal Stud
Glass

Ground layers and direct bypass capacitors possible within a ceramic

package
High permittivity of alumina (r = 10)
Expensive

Hermetically Sealed Semiconductor Package.

Ceramic

Cost of Ceramic Packages Versus Plastic Packages

Plastic Packages cost

lower compared to
Ceramic Packages on
similar
package
configuration
and
number of pins

Lidded Ceramic Package

Hermetically Sealed Semiconductor Packages.

Ceramic

Hermetically Sealed Semiconductor Packages.

Ceramic

Cap
IC
Wire (Au-Al)

Lead
Frame

Devitrifying
Glass
Base

Un-lidded Ceramic Package

Ceramic Package with Quartz Bull's-eye

Hermetically Sealed Semiconductor Packages.

Ceramic Lidded Chip Carrier (LCC); Hybrid Package

Plastic Molded Semiconductor Packages.

PLCC

PDIP
Wire
Ceramic Lidded Chip Carrier

Die

Lead
Frame

Hybrid Packages

TSOP
Mold Compound

Die Pad

Plastic Molded Semiconductor Packages.

Plastic Molded Semiconductor Packages.

Characteristics of Plastic packaging material

Die-bonding and wire bonding the chip to a metal lead frame
Encapsulation in injection-molded plastic
Inexpensive but high thermal resistance
Plastic molds are hygroscopic
Absorbs moisture. Storage in low-humidity environment
Observation of factory floor-life
Stored moisture can vaporize during rapid heating. Can lead
to hydrostatic pressure during reflow process. Consequences
can be: Delamination within the package, package cracking.
Early device failure.

Die Stacked Chip Scale Packaging

Flexible Stacked (Folded Stacked)

Plastic Molded Semiconductor Packages with Organic Laminate

Substrate.

Interconnect Technology
Ball Grid Array (BGA)

Advanced IC package
for high density low
profile applications
Chip scale
(CSP)

package

Low lead inductance

Package Interconnect

Semiconductor Packaging: Second Level Interconnect Technology

Pin-Through-Hole (PTH)
The package serves as a space
transformer
from
the
chip
interconnection
to
the
board
interconnection.

First Level Interconnect connects the silicon die to the package. This maybe a
wirebond or a flip chip type interconnect
Second Level Interconnect is the connection between the package and the
system board. This may be in the form of leads, pins or balls arrays.

Semiconductor Packaging: First Level Interconnect Technology

Wirebond
The pads on the IC chip and the adjoining I/O
signal, power and ground terminals are
connected one by one with Gold (Au) or
Aluminum (Al) wires

Flip Chip
The invention of the flip chip technology
allowed a breakthrough in increasing the
number of internal signal interconnect to
external package pins.

Pins are inserted into through-holes in the circuit board and soldered in
place from the opposite side of the board
Socket available
Manual pick and place possible

Surface Mount Technology (SMT)

SMT packages have leads that are soldered directly to corresponding
exposed metal lands on the surface of the circuit board
Elimination of holes
Ease of manufacturing (high-speed P&P)
Components on both sides of the PCB
Smaller dimensions
Improved package parasitic components
Increased circuit-board wiring density

Semiconductor Packaging: Second Level Interconnect Technology

Packaging Trends

Electrical performance requirements

continue to drive increases in pin
count and interconnect performance.
These requirements include, but are
not limited to, increases in bus speed,
alternative signaling technologies,
feature integration, and low-voltage,
high-current power delivery.

Trends and Challenges

Reference:
Pentium 4 Processor High-Volume Land-Grid-Array Technology: Challenges and Future
Trends Intel Technology Journal, Volume 09Issue 04 November 9, 2005

Packaging Trends

Packaging Trends

The pad pitch on the IC chip is

typically 0.006 inch (6 mils or
152m). This spacing is already
much larger than the 2 to 8
microns (0.08 to 0.31 mils) pitch of
the wiring (metallization) on the IC
chip. But PCB wiring requires an
even larger pitch, usually between
40 and 100 mils.

Microelectronics Packaging: Interconnect Challenges

Rents Rule

E.F. Rent of IBM published two

internal memoranda in 1960 that
contained the log plots of "number
of pins" versus "number of circuits'
in a logic design. These data tend to
form a straight line in a log-log plot
and yield the relationship:

The biggest limitation of a modern digital IC: Large reduction in signal count
between on chip wires and package pins. Typical IC has:

104 wiring tracks on each of the 4-5

metal layers
103 signals can leave the chip (for
cheaper packages: 40200)

N P K P N G

Chips are often pad limited.

Peripheral-bonded chips. Chip area
increases as the square of the
number of pads.

Microelectronics Packaging: Interconnect Challenges

Peripheral-bonded chips.

Reference: Wire-Loop Shaping in Multi-Tier Packages

URL: http://www.semiconductor.net/article/CA630278.html

Where:
NP is the number of pins
NG is the number of logic blocks
is Rents constant
KP is a proportionality constant

Rents Rule

Packaging Trends

Packaging Trends

Ball Pitch

To avoid substantial increases in

package size with this increase in pin
count, interconnect pitch reduction is
required. Pitch reduction imposes
package routing, motherboard routing,
and socket design constraints that
require significant integration to
address. From socket design and
assembly standpoints, surface-mount
capability continues to be desired,
imposing
additional
design
considerations. Yield and reliability of
large-pin-count and reduced-pitch
components are a design challenge
due to component warpage and
thermal
expansion
differences
between materials.

This passive silicon carrier

contains a regular grid of
through-silicon vias (TSVs). It is
designed to serve as a costoptimized
interposer
for
standard circuit
ICs,
with
matching coefficient of thermal
expansion to the chip and
carrier.

Packaging Trends

Source: http://nepp.nasa.gov/index_nasa.cfm/779/

The rapid progress in chip-level

interconnect scaling that is
expected between now and 2015
(from 60-20 m peripheral
pitches), relative to the density of
interconnects on PCBs (800-500
m solder ball pitch) is the focus
of next-generation flip-chip and
substrate technology . With ball
grid array (BGA) and micro-BGA
approaches, package reliability is
dominated by underfill reliability.
Smaller diameter bumps put
more strain on thinner layers and
higher stresses on smaller areas.

Reference: http://www.semiconductor.net/article/CA6492524.html

Assembly and Test Processes

Semiconductor Assembly and Test Process: Introduction

Plastic Package Assembly: Die Preparation

Wafer Mount

Wafer Inventory

To FOL

Assembly and test are the processes involved in transforming the

fabricated wafers into packaged and functional components.

Semiconductor Assembly and Test Process: Wirebond

Wafer Saw

Wafer Thinning

Assembly: Front of Line

Die Attach

Wirebond

Plasma Clean

To EOL
Plasma Clean

Optical Inspection

Assembly: End of Line

Semiconductor Assembly and Test Process: Flip Chip

Encapsulation

B. Substrate
Preparation

A. Die Preparation

DTF & Lead Finish

To Test Process

AVI

BUMP
REFLOW

WAFER
MOUNT

WAFER SAW
& WASH

APL

C. Assembly Process
CARRIER
TRAY LOAD

Marking
CAM

Test Processes

DEFLUX

EPOXY

Semiconductor Assembly and Test Process: Test Process

Class Test

D. Test Process

Dry Pack

Tape and Reel

PRE BURN
IN CHECK

BURN IN

POST BURN
IN CHECK

E. Backend Process

LASER
MARK

Bake

FQA

BALL
ATTACH &
INSPECT

FVI

PACK

FQA

Semiconductor Assembly: Wafer Level Packaging

[a] wafer encapsulation

[b] electrical contacts are routed
[c] solder bumps are formed
[d] the wafer is singulated
[e] the final wafer is one chip
short of a WLCSP
Source: Tessera Inc.
http://www.semiconductor.net/article/CA6
482835.html

Packaging Material Market Outlook

Chip-scale packaging (CSP),

flip-chip packaging (FCP) and
various
SiP
technologies
require organic substrates,
new
mold
compound
formulations, smaller diameter
wire and, for some packages,
customized underfill materials.
The largest contributor to the 13% growth rate for packaging materials in 2007
will be organic substrates, which are required for the rapidly growing ball grid
array (BGA) and FCP applications. The organic substrates market, which is the
largest segment of the overall packaging materials market, will approach $6.3B
this year, compared with $5.1B last year. Without organic substrates in the yearover-year growth rate calculation, the total packaging materials growth rate
drops to 7% from 13%.
Source: http://www.semiconductor.net/article/CA6445468.html