Professional Documents
Culture Documents
I(s)
+
V(s)
Z (s) =
V (s)
1
= sL +
I (s)
R !1 + sC
Two-ports
Transfer function; measure input at one port, output at
another I1(s)
I (s)
+
V1(s)
MAE140 Linear Circuits
+
V2(s)
-
Inputs
Outputs
152
Cascade Connections
We want to apply a chain rule of processing
TV ( s ) = TV 1( s ) ! TV 2 ( s ) ! TV 3 ( s ) ! ... ! TVk ( s )
When can we do this by cascade connection of OpAmp ccts?
Cascade means output of ccti is input of ccti+1
This makes the design and analysis much easier
153
1
sC1
Cascade Connections
+
+
V1(s) +
_
I1(s)
R1
R2
1
V2(s)
I2(s) sC2
+
V3(s)
R1C1s
1
R1C1s
TVtotal ( s ) = TV 1( s ) ! TV 2 ( s ) =
!
=
R1C1s + 1 R2C2 s + 1 (R1R2C1C2 )s 2 + (R1C1 + R2C2 )s + 1
Mesh analysis
& 1
#
$$
+ R1 !! I1( s ) ' R1I 2 ( s ) = V1( s )
% sC1
"
&
1 #
!! I 2 ( s ) = 0
' R1I1( s ) + $$ R1 + R2 +
sC2 "
%
I 2 (s) =
V3 ( s ) =
& 1
+ R1
$
I
(
s
)
& 1 # $ sC1
$$
!! =
% I 2 ( s ) " $ ' R1
$
%
'1
#
' R1
! V (s)
! &$ 1 #!
1
+ R1 + R2 !! % 0 "
sC2
"
s 2C1C2 R1
V1( s )
2
(R1R2C1C2 )s + (C1R1 + C2 R1 + C2 R2 )s + 1
1
R1C1s
I 2 (s) =
V1( s )
2
sC2
(R1R2C1C2 )s + (R1C1 + R1C2 + R2C2 )s + 1
MAE140 Linear Circuits
154
+
V1(s)
Z2
+
V2(s) Noninverting amplifier
No current drawn from V1 no load
Z1
Z1
Z2
+
-
+
V1(s)
I(s)
V2(s)
Inverting amplifier
V1( s )
Current provided by V1(s) I ( s ) = Z ( s )
1
Need to make sure that stage is
driven by OpAmp output to
avoid loading V1(s)
155
Z1
V1(s) +
_
Z2
Node B:
+
-
V2(s)
VB ( s ) ! V1( s ) VB ( s ) ! V2 ( s )
+
=0
Z1( s )
Z 2 (s)
V2 ( s )
Z 2 (s)
VB ( s ) = 0 " TV ( s ) =
=!
V1( s )
Z1( s )
V1(s) +
_
C
+
-
Z2
B
Z1
V2(s)
Node B:
VB ( s ) " V2 ( s ) VB ( s )
+
=0
Z 2 (s)
Z1( s )
Z1( s ) + Z 2 ( s )
VB ( s ) = V1( s ) ! TV ( s ) =
Z1( s )
156
R2
1
sC1
+
V1(s)
+
-
TV ( s ) =
1
sC2
V2(s)
1 = sR1C1 + 1
=
+
Z1( s ) R1
sC1
sC1
R2
Z 2 (s) =
sC2 =
R2
R2C2 s + 1
R2 + 1
sC2
sR2C1
( sR1C1 + 1)( sR2C2 + 1)
157
R1
R3
+
VO(s)
1
sC2
V2(s)
1
sC3
+
-
+
-
VI(s)
R3 LC3s 2 + 1
sR2C1
TV ( s ) =
(sR1C1 + 1)(sR2C2 + 1)
Ls
158
+
-
Series RL design
1
K!
+
-
1
!
+
s
TV ( s ) = K
s +
Series RC design
MAE140 Linear Circuits
159
First-order stages
1
!
1
K!
1
+
-
1
K
+
s
TV ( s ) = K
s +
Parallel RL design
1
!
1
K!
1
+
-
Parallel RC design
MAE140 Linear Circuits
160
1
1000F
+
-
Stage 1
' 1
$
!
3
! 1000
TV 1( s ) = ! % 10 s "[1]!1 =
%1 + 1
"
s + 1000
!
3
%&
10 s "#
3000 s
( s + 1000)( s + 4000)
3
250F
+
-
TV ( s) =
Stage 2
!1
! 3s
4000
TV 2 ( s ) = ![3]1 +
=
s
s + 4000
161
Stage 1
Voltage
Divider
Stage 2
OpAmp
3000 s
( s + 1000)( s + 4000)
250F
1
Stage 3
Voltage
Divider
162
10
100nF
25nF
30
+
-
10
+
-
163
C2 =
K " ! 02
+
1
C1 =
K
!1
2
"0
"02 ! K
1
K
1
!
2"# 0
1
H
K
1F
1
H
2
!0
2"# 0 !
1
F
2
!0
+
-
R = 2!" 0
164
Circuit Synthesis
Given a stable transfer function TV(s), realize it via a
cct using first-order and second-order stages
TV ( s ) =
#s 2 + "s + !
as 2 + bs + c
TV ( s ) =
"s + !
as + b
165