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Lesson 4
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Outline
Ring Counter
Johnson Counter
Odd Sequencer Switch tail
(Twisted Ring) Johnson counter
Even Sequencer Switch tail
(Twisted Ring) Johnson counter
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Clock
input CLK
QA
QB
D FF D
D FF D
PR
QC After tp QD
D FF D
D FF D
Q
PR
PR
Serial
in = 1
CLR
PR = 1
Each flip flop has output delay tp of and ring
output and input delays by tp of one D-FF
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Outputs
2
0
1
0
0
3
1
0
0
0
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4tp
at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Outputs
2
0
1
0
0
3
1
0
0
0
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4tp
at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
S0
0100
S0
0010
S0
0100
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Ring Counting
When CLR = 0, all FFs are cleared (Q = 0)
except right most, which sets to 1.
When CLR = 1, ring counting starts. On
next clock edge, the QD = 1 left shifts to QC
and since QA = 0 and connects to serial
input at DD, QA = 0 and QC = 1. In next
transition, QB = 1 and QC = 0; and so 1
rotates in ring form..
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Outline
Ring Counters
Johnson Counter
Odd Sequencer Switch tail
(Twisted Ring) Johnson counter
Even Sequencer Switch tail
(Twisted Ring) Johnson counter
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
10
Clock
input CLK
QA
QB
D FF D
PR
D FF D
QC After tp QD
D FF D
D FF D
Q
PR
PR
Serial
in = 1
CLR
PR = 1
11
Output Sequences
QA
Y3
QB
Y2
QC
Y1
QD
Y0
OE
To CLR
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
To CLR
12
S7
0000
S1
S2
S3
0011
0111
1111
S6
S5
S4
1000
1100
1110
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Outputs
3
1
1
1
1
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4tp
at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Outputs
7
0
0
0
0
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4
tp at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Johnson Counter
QA is given as input to rightmost place
instead of QD input in case of ring counter.
When CLR = 0, all Qs and Ds of FFs = 0
cleared except the DD input at right most FF
which sets to 1, as it connects QA.
When CLR = 1, Johnson counting starts. On
the clock edge, the QD = 1 left shifts to QC
and since QA = 1 and connects to serial
input at DD, QA = 1, QA = 1 and QC = 1.
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Johnson Counter
In next cycle, QA = 0 so 0 rotates in
ring form in second half cycle
Johnson counter has 8 sequences:
0001, 0011, 0111, 1111, 1110, 1100,
1000, 0000
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Outline
Ring Counters
Johnson Counter
Odd Sequencer Switch tail
(Twisted Ring) Johnson counter
Even Sequencer Switch tail
(Twisted Ring) Johnson counter
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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QB
D FF D
D FF D
QC After tp QD
D FF D
D FF D
Q
PR
PR
PR
QB
Serial
in = 1
CLR
PR = 1
QA
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
19
20
S1
S2
S3
0011
0111
1111
S6
S5
S4
1000
1100
1110
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Outputs
3
1
1
1
1
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4tp
at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
22
Outputs
0 Repeat
0
0
0
1
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4
tp at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
23
Outline
Ring Counters
Johnson Counter
Odd Sequencer Switch tail
(Twisted Ring) Johnson counter
Even Sequencer Switch tail
(Twisted Ring) Johnson counter
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
24
QB
D FF D
D FF D
QC After tp
D FF D
Q
PR
PR
QB
QB
QA
QA
QD
D FF D
PR
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
Serial
in = 1
CLR
PR = 1
25
26
27
S1
S2
0011
0111
S6
S5
S4
1000
1100
1110
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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Outputs
29
Outputs
0 Repeat 0
0
0
1
Qn+1 means next state after nth clock input and
after a delay of tp at successive FFs. Delay = 4
tp at Qn+1(D) on each transition
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
30
Summary
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
31
We learnt
Ring counter has n-sequences rotating when
n-bit shift register is used with last end Q
FF output connected to first end D input of
FF
Johnson counter has 2n-sequences rotating
when n-bit shift register is used with last
end QA at FF output connected to first end
D input of FF
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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We learnt
Johnson counter twisted has (2n1) sequences
rotating when n-bit shift register is used with last
two QA andQB ANDed and connected to
first end D input of FF
Johnson counter twisted has (2n2) sequences
rotating when n-bit shift register is used with last
two QA andQB ANDed and connected
through OR gate to first end D input of FF and
also last two QA and QB NANDed and
connected through OR gate to first end D input of
FF
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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End of Lesson 4
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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THANK YOU
Ch16L4- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006
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