INSTITUTO TECNOLOGICO DE REYNOSA.

REPORTE: Simulacin de compuertas en VHDL.

DISEO DIGITAL.
Alumno: Diana Carolina Juregui Gmez.
Profesor: ing. Garca Castan Efrn Gerardo.
Fecha: 20/05/2015

Indice.
Practica

Pagina

Compuerta AND.
Compuerta OR.
Compuerta XOR.
Compuerta XNOR.
Compuerta NAND.
Compuerta NOR
Compuerta BUFFER.
Compuerta NOT.

Pag.3
Pag.5
Pag.7
Pag.9
Pag.11
Pag.13
Pag.15
Pag.17

Practica#1.

Compuerta AND.
Cdigo.

Diagrama.

Simulacin:

# Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line
breakpoints, code coverage, and assertion debug will not be available.
# File: c:\My_Designs\compuerta\com\src\and.vhd
# Compile Entity "\and\"
# Compile Architecture "\and\" of Entity "\and\"
# Compile success 0 Errors 0 Warnings Analysis time : 0.1 [s]

Tabla de verdad.

Practica#2.

Compuerta OR.
Cdigo.

Diagrama.

Simulacin:

#
KERNEL: stopped at time: 750 ns
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
run 30 ns
# KERNEL: stopped at time: 780 ns
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
Tabla de verdad.

Practica#3.
Compuerta X-OR.
Cdigo.

Diagrama:

Simulacin:

# KERNEL: ASDB file was created in location

c:\My_Designs\comp_xor\compxor\src\wave.asdb
# 01:06 a.m., jueves, 21 de mayo de 2015
# Simulation has been initialized
# Selected Top-Level: \xor comp\ (\xor comp\)
run
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
Tabla de verdad:

Practica#4.
Compuerta XNOR.
Cdigo.

Diagrama:

Simulacin:

# Warning: DAGGEN_0523: The source is compiled without the -dbg switch. Line
breakpoints, code coverage, and assertion debug will not be available.
# File: c:\My_Designs\xnor_comp\xnor_comp\src\exnor.vhd
# Compile Entity "exnor"
# Compile Architecture "exnor" of Entity "exnor"
# Compile success 0 Errors 0 Warnings Analysis time : 0.1 [s]
Tabla de verdad:

Practica# 5.
Compuerta NAND
Cdigo.

Diagrama:

Simulacin:

# KERNEL: ASDB file was created in location

c:\My_Designs\compuerta_nand\nand comp\src\wave.asdb
# 01:43 a.m., jueves, 21 de mayo de 2015
# Simulation has been initialized
# Selected Top-Level: \comp nand\ (\comp nand\)
run
# KERNEL: Simulation has finished. There are no more test vectors to simulate.

Tabla de verdad:

Practica# 6.
Compuerta NOR.
Cdigo.

Diagrama.

Simulacin.

# KERNEL: Simulation has finished. There are no more test vectors to simulate.
run 100 ns
# KERNEL: stopped at time: 1200 ns
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
# Adding file c:\My_Designs\comp_nor\comp nor\src\untitled.asdb ... Done
# Adding file c:\My_Designs\comp_nor\comp nor\src\untitled.awc ... Done
Tabla de verdad:

Practica# 7.
Compuerta NOT.
Cdigo

Diagrama.

Simulacin.

# KERNEL: ASDB file was created in location

c:\My_Designs\comnot\compnot\src\wave.asdb

# 02:10 a.m., jueves, 21 de mayo de 2015

# Simulation has been initialized
# Selected Top-Level: compnot (compnot)
run
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
Tabla de verdad.

Practica# 8
Compuerta buffer..
Cdigo

Diagrama.

Simulacin.

# Top-level unit(s) detected:

# Entity => \comp buf\
# Compile success 0 Errors 0 Warnings Analysis time : 0.1 [s]
# Design: Design compif already active.
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].

Tabla de verdad.