AP Material Unit-1 PDF

Darshan Institute of
Engineering & Technology
1.
Ans
Advance Processors
UNIT-1
Define the Following.

-
Microprocessor:
It is a multipurpose, programmable device that accepts digital data as input,

processes it according to instructions stored in its memory, and provides results
as output.
Assembler:
An assembler or macro-assembler generally forms a part of the operating

system. Which translates a assembly language program into machine language
program.
Debugger:
It is a program which allows user to test and debug programs. All computers
including microprocessor provide debugging facility. To detect errors a program
can be tested in single steps. Each step of the program is executed and tested.
The debugger allows the user to examine the contents of registers and memory
locations after each step of execution. This also provides facility to insert
breakpoint in the programs.
Linker:
A large program is divided in smaller programs known as modules. A linker is a

program which links smaller programs together to form a large program. While
developing a program subroutines, which are stored in library file, are
frequently used in the program. The linker also links these subroutines with the
main program.
Stack:
The stack is an area of memory identified by the programmer for temporary

storage of information having LIFO structure.
Subroutine:
A subroutine is a group of instructions that will be used repeatedly in different

locations of the program.
Instruction:
An instruction is a binary pattern designed inside a microprocessor to perform a

specific function
Opcode:
selects the operation performed by the microprocessor
Operand:
The data on which the operation is to be performed as well as the result of an

operation.
Interrupt:
Interrupt is a change of path in program execution caused by hardware request,

software execution or internal processor error.
ISR:
A small program or a routine that when executed services the corresponding

interrupting source is called ISR.
Bus:
A group of lines, pins or signals having common function is teamed as bus.
Clock
The processing speed of microprocessor depends upon the clock frequency.
Frequency:
Program execution speed is determined by this parameter (number of

instructions/sec).
Swati R. Sharma
Page 1
Advance Processors
UNIT-1
2.
Introduction to 8086 microprocessor OR Features of 8086 microprocessor
Ans
General Features:
8086 is a 16-bit processor, which implies that

-
16-bit data bus
16-bit ALU, that perform 16-bit operation at the same time
16-bit registers
Speed of processor
There are three versions based on the frequency of operation

8086 -> 5MHz (5 million cycles per second)
8086 has a 20 bit address bus can access up to 220 memory locations.( 220=1048576 bytes =1 MB)
It can support up to 64K I/O ports. (216 I/O ports-> 216=65536 bytes=64 Kb)
In 8086 two Unit works in parallel:

-
Bus Interface Unit (BIU)
Execution Unit (EU)
8086 has 256 vectored interrupt.
8086 contains powerful instruction set , that supports Multiply and Divide operation (this operation
were not possible in previous versions of 8086)
8086 can perform operation on bit, byte (8-bit), word (16-bit) or string types of data.
Special Features:
8086 is a pipelined processor
8086 is two staged pipelined architecture:
i.
Fetch Stage: It pre-fetch up to 6 bytes of instruction and store them in the queue.
ii.
Execute stage: Executes the instruction
8086 can operate in 2 modes

i.
Minimum mode: A system with only one processor i.e.8086
ii.
Maximum mode: A system with multiple processors.

e.g. 8086 + math co-processor(8087),
8086+ I/O processor (8089),
Multiple 8086 processors
8086 uses memory bank

-
In 8086 entire data is not stored in single sequential memory of 1MB.
The memory is divided into two banks of 512KB each.
i.
Lower Bank/ Even Bank: Stores the data types at even locations (0,2,4)
ii.
Higher Bank/ Odd Bank: Stores the data types at odd locations (1,3,5)
8086 uses memory segmentation

-
Segmentation means dividing memory into logical components.
In 8086 memory is divided into 16 segments of capacity 2 16 bytes each and used as code, stack,
data and extra segment
Swati R. Sharma
Page 2
3.
Advance Processors
UNIT-1
Explain 8086 Architecture

OR State the function of components of 8086 internal architecture.
Ans
The Block diagram for the internal architecture of 8086 is as follows:-
In 8086 CPU is divided into two independent functional parts BIU and EU.
Dividing the work between these two units speeds up the processing.
BIU (Bus Interface Unit)
Components of BIU
-
Instruction queue
It holds the instruction bytes of the next instruction to be executed by EU
Segment Registers
Four 16-bit register that provides powerful memory management mechanism
ES (extra segment), CS (code segment), SS (stack segment) , DS (data segment).
The size of each register is 64kb.
Instruction pointer (IP)

Register that holds 16-bit address or offset of next code byte within code segment
Address Generation and bus control

Generation of 20-bit physical address
Swati R. Sharma
Page 3
Advance Processors
UNIT-1
Task carried out by BIU
Fetch instruction from memory
Read/ Write instruction from / to the memory
Input/ Output (I/O) of data from / to peripheral ports
Write the data to memory.
Address generation for memory reference
Queuing of instruction (The instruction bytes are transferred to the instruction queue)
Thus, BUI handles all transfer of data and address on the buses for Execution unit.
BIU works in synchronous with machine cycles
EU (Execution Unit)
Components of EU
-
ALU (Arithmetic logic Unit)

Contains 16-bit ALU, that performs add, subtract, increment, decrement, compliment,
shift binary numbers, AND, OR, XOR etc.
CU (Control Unit)
Directs internal operation
Flag Register
16-bit flag register
EU contains 9 active flags
General Purpose Registers (GPR)

EU has 4 general purpose 16-bit register
i.e. AX, BX, CX, DX
each register is the combination of two 8-bit register
AH, AL, BH, BL, CH, CL, DH, DL where L means Lower byte and H means higher byte.
Index Register
16-bit Register is SI (source index) and DI (destination index).
Both the register are used for string related operation and for moving block of memory
from one location to the other.
Pointers
16-bit Register.
i.e. SP (stack pointer), BP (base pointer)
BP : is used when we need to pass parameter through stack
SP:
It always points to the top of the stack. Used for sequential access of stack
segment.
-
Decoder (instruction decoder)

Translates the instruction fetched from into series of action which EU carries out
Task carried out by EU
Decodes the instruction
It executes instructions ( executes decoded instructions)
Tells BIU from where to fetch the instruction
Swati R. Sharma
Page 4
Decodes instruction (decode the fetched instruction)
EU takes care of performing operation on the data
EU is also known as execution heart of the processor
Advance Processors
UNIT-1
4.
Explain 8086 Registers
Ans
The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer as
follows:General Purpose Register
1. AX: - Accumulator register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX.
- AX works as an intermediate register in memory and I/O operation.
- Accumulator is used for the instruction such as MUL and DIV.
2. BX: - Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX.
- BX register usually contains a data pointer used for based, based indexed or register indirect
addressing.
3. CX: - Count register consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. Count register can be used in Loop, shift/rotate instructions and
as a counter in string manipulation.
4. DX: - Data register can be used together with AX register to execute MUL and DIV instruction.
- Data register can be used as a port number in I/O operations.
Segment Register
Types of Segment registers are as follows:1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment
of the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data
Segment by an offset address or the content of other register that holds the offset address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the
destination data
Pointer Registers
The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively.
1. Stack Pointer (SP): SP is a 16-bit register pointing to program stack in stack segment.
2. Base Pointer (BP): BP is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
3. Instruction Pointer (IP): IP is a 16-bit register pointing to next instruction to be executed.
Swati R. Sharma
Page 5
Advance Processors
UNIT-1
Index registers
The Index Registers are as follows:1. Source Index (SI): SI is a 16-bit register used for indexed, based indexed and register indirect
addressing, as well as a source data addresses in string manipulation instructions.
2. Destination Index (DI) : DI is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data addresses in string manipulation instructions.
Flag Registers
1. The 16-bit flag register of 8086 contains 9 active flags (six conditional & 3 control flags), other 7
flags are undefined.
2. Status Flags: It indicates certain condition that arises during the execution. They are controlled by
the processor.
3. Control Flags: It controls certain operations of the processor. They are deliberately set/ reset by the
user.
15
14
13
12
11
10
OF
DF
IF
TF
SF
ZF
AF
PF
CF
U- Undefined
CF- Carry Flag
TF- Trap Flag
PF- Parity Flag
IF- Interrupt Flag
AF- Auxiliary Flag
DF- Direction Flag
ZF- Zero Flag
OF- Overflow Flag
SF- Sign Flag
The Flag Registers are classified as follows :-
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
4. Trap Flag (TF):
-
It is used for single step control.
It allows user to execute one instruction of a program at a time for debugging.
When trap flag is set, program can be run in single step mode.
5. Interrupt Flag (IF):

-
It is an interrupt enable/disable flag.
If it is set, the mask able interrupt of 8086 is enabled and if it is reset, the interrupt is disabled.
It can be set by executing instruction sit and can be cleared by executing CLI instruction.
Swati R. Sharma
Page 6
Advance Processors
UNIT-1
6. Direction Flag (DF):

-
It is used in string operation.
If it is set, string bytes are accessed from higher memory address to lower memory address.
When it is reset, the string bytes are accessed from lower memory address to higher memory
address.
Status Flag
1. Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also
used in multiple-precision arithmetic.
2. Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e.
D0 D3) to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag.
This is not a general-purpose flag, it is used internally by the processor to perform Binary to BCD
conversion.
3. Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result
contains even number of 1s, the Parity Flag is set and for odd number of 1s, the Parity Flag is reset.
4. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
5. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set.
6. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. OF=1 indicates that the
result has exceeded the capacity of machine.
5.
Explain Addressing modes of 8086
Ans
When 8086 executes an instruction, it performs the specified function on data. These data are called its
operands and may be part of the instruction, reside in one of the internal registers of the microprocessor,
stored at an address in memory or held at an I/O port, to access these different types of operands,
the 8086 is provided with various addressing modes.
There are 12 addressing modes in 8086 as follows:1. Immediate Mode
-
If a source operand is part of the instruction instead of the contents of a register or memory location,
it represents what is called the immediate operand.
In other word it is constant data contained in an instruction
If source operand is the part of instruction rather than register or memory, then referred as
immediate addressing mode.
Operand = address field
E.g. MOV AL, 05H; instruction copies immediate number 05H to AL register
Immediate data may be 8-bits or 16-bits in length

Instruction
Opcode
Swati R. Sharma
Immediate Operand
Page 7
Advance Processors
UNIT-1
Advantage:
-
Operand can be accessed quickly as they are directly available in instruction queue.
No need of External bus or bus-cycles to obtain data.
No memory reference to fetch data
Comparatively Faster execution
Limitation:
-
The operand can only be used as a source operand.
Value of the operand will remain Constant
2. Register Addressing Mode

-
The operand is stored in one of the CPU register.
Register may be used as source operand or destination operand or both
E.g. ADD r1, r2; adding r1 and r2 and store the result in r2
E.g. MOV AX,BX ; move value from BX to AX register
Advantage:
-
This mode is normally preferred, as the execution of instruction is faster and compact, because all
the registers reside on the same chip.
Therefore, data transfer is within the chip and no External bus is required.
Limitation:
-
Number of CPU registers are limited
3. Direct Addressing Mode

-
Address field of Instruction contains address of operand
Benefit:
-
Single memory reference is required to access data
No additional calculations to work out effective address
Equation: Physical Address PA ={starting address of Segment Register } + {Direct memory address}
Swati R. Sharma
Page 8
Advance Processors
UNIT-1
E.g.
MOV [30540], TEMP; moving value of TEMP to memory location [30540]
DS=3060 and direct memory address=0030
3 0 6 0 0 (0 is added to LSB by BIU)
+
0 0 3 0 ( direct address)
--------------------3 0 6 3 0 (physical address)

-
4. Register Indirect Addressing

In this addressing mode effective address of memory is calculated from base register (BX) or index
register (SI, DI), specified in the instruction. Then it is added to the segment register to generate
physical address.
Equation: Physical Address PA ={starting address of Segment Register } + { [BX] or index register }
E.g. MOV [DI], BX; value of BX is moved to the memory location specified in DI
MOV [BX], AX ; value of AX is moved to the memory location specified in BX
Swati R. Sharma
Page 9
Advance Processors
UNIT-1
Benefit:
-
Large address space
Limitation:
-
Slower access, as multiple memory accesses is needed to find operand.
5. Based Addressing Mode

When memory is accessed PA is computed from BX and DS, when the stack is accessed PA is computed
from BP and SS.
Equation:
PA ={starting address of Segment Register } + { [BX] or [BP] }+ (8 or 16 bit) displacement
E.g. MOV AL, TEMP [BX]; segment register address+ BX+ offset
MOV AL, TEMP [BP]; segment register address+ BP+ offset
Assume DS=3060, BX=0050 and displacement=08
3 0 6 0 0 H (starting address of segment register)
+
+
0 0 5 0 H(base register)
0 8 H(offset)
---------------------------------------3 0 6 5 8 H(physical address)

6. Indexed Addressing Mode
-
In this addressing mode offset address is added to index register and finally the sum is added to
segment register.
E.g. MOV BH, TEMP [SI] ; TEMP is the offset address
Equation:
PA ={starting address of Segment Register } + { [SI] or [DI] }+ (8 or 16 bit) displacement
Assume DS=3060, SI=0050 and displacement=08
+
+
0 0 5 0 H (Source Index)
0 8 H (offset)
---------------------------------------3 0 6 5 8 H (physical address)
Swati R. Sharma
Page 10
Advance Processors
UNIT-1
7. Based Indexed Addressing Mode

-
This mode generates the effective address, which is sum of Base address +Index Address + (8 or 16
bit) displacement address.
This sum is added to segment register to generate effective address.
E.g. MOV CX, TEMP[BX] [SI]
Equation: PA ={starting address of Segment Register } + {[BX] or [BP]}+({ [SI] or [DI] }+ (8 or 16

bit) displacement
Assume DS=5000, BX=3000, SI=0400 and displacement=08

+
3 0 0 0 H (base register)
0 4 0 0 H (Source Index)
0 8 H (offset)
---------------------------------------5 3 4 0 8 H (physical address)
Swati R. Sharma
Page 11
Advance Processors
UNIT-1
8. String Addressing Mode

The string instructions automatically assume SI to point to the first byte or word of the source operand
and DI to point to the first byte or word of the destination operand. The contents of SI and DI are
automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word.
Source address : 20500, assume it contains 38
PA : [DS] + [SI] = 20000+0500=20500
Destination address : [ES] + [DI] = 40000+0300
After executing MOV SI, DI
[40300] = 38
[SI] = 0501
incremented
[DI] = 03
9. Relative addressing mode:
Relative address means relative to IP (Instruction Pointer).
Example : JNC START ; jump to label if no carry is generated
-
If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START,
otherwise the next instruction is executed.
Displacement is calculated on the basis of next location to be executed.
10. Implied addressing mode:

Instructions using this mode have no operands.
E.g.
CLC; which clears carry flag to zero.

STC; set the carry flag
11. I/O mode (direct) :

Port number is an 8 bit immediate operand.
Example : OUT 05 H, AL
Outputs value of AL to 8 bit port 05 H
IN and OUT instructions are allowed to use only AL or AX registers.
12. I/O mode (indirect):
I/O port address is provided in DX register. Port address ranges from 0000 to FFFFH.
The port number is taken from DX.
Example 1 : IN AL, DX
IN and OUT instructions are allowed to use only AL or AX registers.
Swati R. Sharma
Page 12
Advance Processors
UNIT-1
6.
Draw and explain 8086 pin diagram
Ans
The 8086 pins and signals are shown as follows:
Total number of pins in 8086 = 40 pins
The 8086 operates in single processor or multiprocessor configuration to achieve high performance.
The 8086 signals can be categorized in six groups

1
Power Supply pins [3]
GND 1, GND2, VCC
Clock Related pins[3]
CLK, RESET, READY
Interrupt Related pins[3]
NMI, INTR, INTA
Address and Data pins [21]
AD0-AD15, A16/S3- A19/S6, BHE/S7
Control pins [3]
TEST, MN/MX, RD
Mode Multiplexed pins [8]
HOLD, HLDA, WR, M/IO, DT/R, DEN, ALE,

INTA
Power Supply pins

i.
ii.
GND1, GND 2
Ground signal (Vss)
VCC
It is a power supply input signal and +5V DC is supplied through this pin.
Clock Related pins

i.
CLK
Input signal
Generates clock signals that synchronize the operation of processor.
ii.
RESET
It is an active high input signal
When high, microprocessor enters into reset state and Terminates activity
Swati R. Sharma
of processor
Page 13
Advance Processors
UNIT-1
Clears PSW, IP, DS,SS,ES, and the instruction queue
CS to FFFF; IP to 0000H; SS to 0000H; DS to 0000H; PSW to 0000H
Processor requires 4 clock cycle to reset. Thus RESET signal must be 1 for at least 4 clock cycles
iii.
READY
This is an acknowledgement signal from I/O devices or memory.
When READY
= high; it indicates that the device is ready to transfer data.

=low; microprocessor is in wait state.
Interrupt Related pins

i.
NMI
It is a non-mask able interrupt signal.
It is an edge triggered interrupt.
ii.
INTR
It is an interrupt request signal.
iii.
INTA
It is an active low output signal.
This is an interrupt acknowledge signal.
When microprocessor receives INTR signal, it acknowledges the interrupt by generating this
signal.
Address and Data pins

i.
AD0-AD15 (bidirectional)
These lines are multiplexed bidirectional address/data bus.
During T1, they carry lower order 16-bit address and in the remaining clock cycles, they carry
16-bit data.
AD0-AD7 carry lower order byte of data and AD8-AD15 carry higher order byte of data.
During T1 machine cycle, when ALE=1, then Address bus gets enabled, else Data bus will get
enabled.
ii.
A16/S3- A19/S6 (unidirectional)
These lines are multiplexed and unidirectional address and status bus.
During T1, they carry higher order 4-bit address.
In the remaining clock cycles, they carry status signals.
S5 gives the status of Interrupt Flag (IF)
S6 goes low, when 8086 controls the shared system bus.
Swati R. Sharma
Page 14
Advance Processors
UNIT-1
S3 and S4 indicates the segment register as shown below:-
iii.
S4
S3
Register
ES
SS
CS
DS
BHE/S7
BHE stands for Bus High Enable.
Active low output signal.
BHE signal is used to indicate the transfer of data over higher order data bus (D8 D15).
8-bit I/O devices use this signal.
S7 is reserved for future development.
Control Pins
i. TEST
-
Active low input signal.
It is used to test the status of math coprocessor 8087.
The BUSY pin of 8087 is connected to this pin of 8086.
If low, execution continues, else microprocessor is in wait state.
ii. MN/MX
-
Input signal
8086 works in two modes:
Minimum Mode [Active high input signal]
Maximum Mode [ Active low input signal]
If MN/MX is high, it works in minimum mode.
If MN/MX is low, it works in maximum mode.
Pins 24 to 31 issue two different sets of signals.
One set of signals is issued when CPU operates in minimum mode.
Other set of signals is issued when CPU operates in maximum mode.
iii. RD (READ)
-
It is a read signal used for read operation.
When the signal is low, then read from memory or I/O
Mode Multiplexed pins

i. INTA (QS1)
-
This is an interrupt acknowledge signal.
When microprocessor receives INTR signal, it acknowledges the interrupt by generating this signal.
ii. ALE(QS0)
-
It is an active high output signal and remains high during T1 state.
Swati R. Sharma
Page 15
Advance Processors
UNIT-1
This is an Address Latch Enable signal.
It indicates that valid address is available on bus AD0 AD15
iii. DEN (S0)

-
It is an active low output signal
This is a Data Enable signal
This signal is used to enable the transceiver
Transceiver is used to separate the data from the address/data bus
iv. DT/R (S1)

-
This is a Data Transmit/Receive signal.
When it is high= >data is transmitted out ,low=>data is received in
v. M/IO(S2)
-
This signal is issued by the microprocessor to distinguish memory access from I/O access.
When it is high=> memory is accessed.

low=> I/O devices are accessed
Operation carried out by Maximum mode (pin 26, 27, 28)
vi.
S2
S1
S0
Machine Language
Interrupt acknowledgement
Read I/O
Write I/O
HALT
Code Access
Read Memory
Write Memory
Passive
LOCK (WR)
This signal indicates that other processors should not ask CPU (8086) to hand over the system
bus.
When it goes low, all interrupts are masked and HOLD request is not granted.
Thus the master bus controller cant take control over the system bus, till the instruction gets
completed.
This pin is activated by using LOCK prefix on any instruction.
WR: It is an active low output signal. It is used to write data in memory or output signal,
depending on status of M/IO signal.
vii.
HOLD (RQ/GT0)
It is an active high input signal.
When DMA controller needs to use address/data bus, it sends a request to the CPU through this
pin.
When microprocessor receives HOLD signal, it issues HLDA signal to the DMA controller.
Swati R. Sharma
Page 16
Advance Processors
UNIT-1
viii.
-
It is an active high output signal.
It is a Hold Acknowledge signal.
It is issued after receiving the HOLD signal.
ix.
7.
HLDA (RQ/GT1)
RQ/GT0 and RQ/GT1 For maximum mode (pin 30 and 31)
These are Request/Grant bi-directional pins.
Other processors request the CPU through these lines to release the system bus.
After receiving the request, CPU sends acknowledge signal on the same lines.
RQ/GT0 has higher priority than RQ/GT1
Explain Segmentation in 8086
Ans
In Segmentation, the total memory size is divided into segments of various sizes.
What is Segment?
Segment is just an area in memory.
What is Segmentation?
The
process
of
dividing
memory
into segments
of various
sizes
is
called
Segmentation.
Why Segmentation?
Memory is huge collection of bytes. In order to organize these bytes in an efficient
manner Segmentation is used.
The complete 1Mbyte memory is divided into 16 logical segments.

-
In memory, data is stored as bytes.
Each byte has a specific address.
Intel 8086 has 20 lines address bus.
With 20 address lines, the memory that can be addressed is 220 bytes.
20 lines= 220 = 1,048,576 bytes =1 MB= 1111 1111 1111 1111 1111=
FFFFF H
At a time 8086 can only access 4 segments.

i.e 64KB * 4=256KB of segments can be accessed at a time.
8086 memory with address ranging from 000000 H to FFFFFF H.
Size of each Segment Register is 16-bit
216 = 65535 bytes = 64K [size of each segment ]
Total number of segments:
Swati R. Sharma
Page 17
Advance Processors
UNIT-1
Total memory available/size of each segment= 1MB/64KB=1024KB/64KB = 16

segments.
What is the need of Segment Register?
-
Segment Registers are used to hold the upper 16-bit of the starting address for each of
the segment.
The 16-bit of the starting address is the starting address of the segment from where the
BIU is currently fetching instruction code bytes.
The BIU always inserts zeros for the LSB of the 20-bit address for a segment. Because
the segment registers cannot store 20 bits, they only store the upper 16 bits.
How is a 20-bit physical address obtained if data bus is of 16-bit?
The 20-bit address of a byte is called its Physical Address (PA).

PA= Base Address : Offset
Offset is the displacement of the memory location from the starting location of the
segment.
The value of Data Segment Register (DS) is 2222 H.
To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of the base
address.
After appending, the starting address of the Data Segment becomes 22220H.
If the data at any location has an address specified as: 2222 H: 0016 H where the
number 0016 H is an offset.
To calculate the effective address of the memory, BIU uses the following formula:
Physical Address = Starting Address of Segment + Offset
To find the starting address of the segment, BIU appends the contents of Segment
Register with 0H and then, it adds offset to it.
EA = 2 2 2 2 0 H
+ 0016H
---------------22236H
Swati R. Sharma
Page 18
Advance Processors
UNIT-1
8.
Explain 8086 Instruction Set
Ans
An instruction is a binary pattern designed inside a microprocessor to perform a specific function.

The entire group of instructions that a microprocessor supports is called Instruction Set. 8086 has
more than 20,000 instructions.
STRING MANIPULATION INSTRUCTION
-
String in assembly language is just a sequentially stored bytes or words.
There are very strong set of string instructions in 8086.
By using these string instructions, the size of the program is considerably reduced.
Implicit addressing mode (string instruction doesnt contain any operand)
MOVSB/MOVSW
-
Move string byte/move string word
It causes moving of byte or word from one string to another.
Implicit Addressing mode.
No flags are affected

Algorithm: MOVSB
Algorithm: MOVSW
ES:[DI]=DS:[SI]
ES:[DI]<=DS:[SI]
If DF=0
If DF=0
Else
then
SI=SI+1
SI=SI+2
DI=DI+1
DI=DI+2
SI=SI-1
Else
SI=SI-2
DI=DI-1
2
DI=DI-2
CMPSB/CMPSW
-
Compare string byte/ Compare string word

Algorithm: CMPSB
Algorithm: CMPSW
ES:[DI]-DS:[SI]
ES:[DI]-DS:[SI]
If DF=0
If DF=0
Else
then
SI=SI+2
DI=DI+1
DI=DI+2
SI=SI-1
Else
SI=SI-2
DI=DI-2
LODSB/LODSW
-
Load string byte from DS: [SI] into AL or AX.

Algorithm: LODSB
Algorithm: LODSW
AL=DS:[SI]
AX=DS:[SI]
If DF=0
If DF=0
then
SI=SI+1
Else SI=SI- 1
4
then
SI=SI+1
DI=DI-1
3
then
then
SI=SI+2
Else SI=SI-2
STOSB/STOSW
-
Store string byte from AL or AX to ES:[DI]
Swati R. Sharma
Page 19
Advance Processors
UNIT-1
No flags are affected by this instruction.
Algorithm: STOSB
Algorithm: STOSW
ES:[DI]=AL
ES:[DI]=AX
If DF=0
If DF=0
then
DI=DI=1
DI=DI+2
Else DI=DI- 1
5
Else DI=DI-2
SCASB/ SCASW
-
Scan a string byte/ word.
This instruction compares a byte in AL or word AX with ES:[DI].
The string which is to be scanned should be in ES and in offset DI.
After comparison DI will be automatically incremented.

Algorithm: SCASB
Algorithm: SCASW
AL-ES:[DI]
AX-ES:[DI]
If DF=0
If DF=0
then
DI=DI=1
then
DI=DI+2
Else DI=DI- 1
6
then
Else DI=DI-2
REP
-
Repeat until specified condition exist
Used as prefix for string instruction.

Algorithm: REP
IF CX< > 0 then
CX=CX-1
Repeat the instruction with prefix REP
ELSE
Exit from REP cycle
REPE/ REPZ
-
Repeat while equal/ Repeat while zero.
String instruction will be repeated as long ZF=1 and CX!=0
Exit condition=> ZF=0 and CX=0

Algorithm: REPE/REPZ
IF CX< > 0 then
CX=CX-1
If ZF=1 then
Repeat the instruction with prefix REPE/REPZ
Else Exit from REPE/REPZ cycle
ELSE
Exit from REPE/REPZ cycle
REPNE/REPNZ
-
Repeat while not equal/ Repeat not while zero.
String instruction will be repeated as long ZF=0 and CX!=0
Exit condition=> ZF=1 and CX=0
Swati R. Sharma
Page 20
Advance Processors
UNIT-1
Algorithm: REPNE/REPNZ
IF CX< > 0 then
CX=CX-1
If ZF=1 then
Repeat the instruction with prefix REPNE/REPNZ
Else Exit from REPNE/REPNZ cycle
ELSE
Exit from REPNE/REPNZ cycle
DATA TRANSFER INSTRUCTION

-
These instructions are used to transfer data from source to destination.
The operand can be a constant, memory location, register or I/O port address.
MOV
-
Syntax: MOV Destination, Source
Copies data from source to destination.
Source operand can be register, memory location or immediate operand.
Destination can be register or memory operand.
Both Source and Destination cannot be memory location at the same time.
Both Source and Destination cannot be segment register at the same time.
e.g. MOV CX, 037A H
MOV AL, BL
MOV BX, [0301 H]
PUSH
-
Syntax: PUSH source
It pushes the operand into top of stack.
This instruction operates only for 16-bit data.
It is invalid to push immediate data and CS to top of the stack

E.g.: PUSH BX
POP
-
Syntax: POP destination
It pops the operand from top of stack to Destination.
This instruction operates only for 16-bit data.
Destination can be a general purpose register, segment register (except CS) or memory
location.
E.g.: POP AX
XCHG
-
Syntax: XCHG destination, source
This instruction exchanges Source with Destination.
It cannot exchange two memory locations directly.

E.g.: XCHG DX, AX
Swati R. Sharma
Page 21
Advance Processors
UNIT-1
XLAT
-
It can be used for an ASCII to EBCDIC code conversion.
Operation: ((AL)+(BX)+(DS))->(AL).
Implicit Addressing mode.
The content of BX represents the offset of the starting address of the look up table from the
beginning of the current data segment while the content of AL represents the offset of the
element which is to be accessed from the beginning of the look up table.
As an example, let DS = 0300 H, BX = 1234 H and AL = 05 H.
Hence, PA = 03000 H + 1234 H + 05 H = 04239 H
IN
-
Syntax: IN Accumulator, Port Address
It transfers the operand from specified port to accumulator register.
E.g.: IN AX, 0028 H
OUT
-
Syntax: OUT Port address, Accumulator
It transfers the operand from accumulator to specified port.
E.g.: OUT 0028 H, AX
LEA (Load Effective Address)

-
Syntax: LEA Destination, Source
It loads a 16-bit register with the offset address of the data specified by the Source
E.g.: LEA BX, [DI]
LEA SI, VAR
This instruction loads the contents of DI (offset) into the BX register.
LDS (Load DS)

-
Syntax: LDS Destination, Source
It loads 32-bit pointer from memory source to destination register and DS.
The offset is placed in the destination register and the segment is placed in DS.
To use this instruction the word at the lower memory address must contain the offset and
the word at the higher address must contain the segment.
10
E.g.: LDS BX, [1000 H]
LES (Load ES)

-
Syntax: LES Destination, Source
It loads 32-bit pointer from memory source to destination register and ES.
The offset is placed in the destination register and the segment is placed in ES.
This instruction is very similar to LDS except that it initializes ES instead of DS.
E.g.: LES BX, [0301 H]
Swati R. Sharma
Page 22
11
12
13
14
Advance Processors
UNIT-1
LAHF
-
Load AH with lower byte of flag register
It copies the lower byte of flag register to AH
Implicit Addressing Mode
SAHF
-
Store AH to lower byte of flag register
It copies the contents of AH to lower byte of flag register
PUSHF
-
Pushes flag register to top of stack
POPF
-
Pops the stack top to flag register
ARITHMETIC INSTUCTIONS
1
ADD (Addition)
-
Syntax: ADD destination, source
It adds a byte to byte or a word to word.
It affects AF, CF, OF, PF, SF, ZF flags.
Both source and destination should be of same type

E.g.:
ADD AL, 10H
ADD DX, AX
ADD AX, [BX]
ADC (Addition with Carry)

-
Syntax: ADC destination, source
It adds the two operands with CF.
Destination= Destination + source + carry

E.g.:
ADC AL, 10H
ADC DX, AX
ADC AX, [BX]
SUB (Subtraction)
-
Syntax: SUB destination, source
It subtracts a byte from byte or a word from word.
For subtraction, CF acts as borrow flag.

E.g.:
Swati R. Sharma
Page 23
Advance Processors
UNIT-1
SUB AL, 10H

SUB DX, AX
SUB AX, [BX]
4
SBB (Subtraction with borrow)

-
Syntax: SBB destination, source
It subtracts the two operands and also borrows from the result.

E.g.:
SBB AL, 10H
SBB DX, AX
SBB AX, [BX]
INC (Increment)
-
Syntax: INC destination
It increments the byte or word by one.
The operand can be a register or memory location.
It affects AF, OF, PF, SF, ZF flags.

E.g.: INC AX
DEC (Decrement)
-
Syntax: DEC destination
It decrements the byte or word by one.
The operand can be a register or memory location.
It affects AF, OF, PF, SF, ZF flags.

E.g.: DEC AX
CMP (Compare)
-
Syntax: CMP destination, source
It compares two specified bytes or words.
The Source and Destination can be a constant, register or memory location.
Both operands cannot be a memory location at the same time.
The comparison is done simply by internally subtracting the source from destination.
The value of source and destination does not change, but the flags are modified to indicate
the result.
NEG (Negate)
-
Syntax: NEG destination
Makes operand negative (two's complement).

Algorithm
Step1: Invert all bits of the operand
Step2: Add 1 to inverted operand
E.g.: NEG AL
Swati R. Sharma
Page 24
Advance Processors
UNIT-1
AAA (ASCII Adjustment for Addition)

-
This instruction allows us to add the ASCII codes.
Corrects result in AH and AL after addition when working with BCD values.
Implicit addressing mode

Algorithm
AH must be cleared before execution of AAA instruction
If AL[L] is between range (0-9) and AF=0 then
Set AL[H]=0
Set AL[H]=0
AH=AH+1
If AL [L] > 9
then
AL = AL +06H
AH=AH+1
AL[H]=00H
AF=1;CF=1
10
AAS (ASCII Adjustment for Subtraction)

-
This instruction allows us to subtract the ASCII codes.
Corrects result in AH and AL after subtraction when working with BCD values.
Implicit addressing mode

Algorithm
AH must be cleared before execution of AAS instruction
Set AL[H]=0
Set AL[H]=0
AH=AH-1
If AL[L] > 9
then
AL = AL 06H
AH=AH1
AL[H]=00H
AF=1,CF=1
11
AAM (ASCII Adjustment for Multiplication)

-
Corrects the result of multiplication of two BCD values.
Performed after multiplication.

Algorithm
Step1: AH=AL/10
Step2: AL=Remainder
Swati R. Sharma
Page 25
12
Advance Processors
UNIT-1
AAD (ASCII Adjustment for Division)

-
ASCII Adjust before Division.
Prepares two BCD values for division.

Algorithm
Step1: AL = (AH * 10) + AL
Step2: AH=00H
13
DAA (Decimal Adjustment for Addition)

Corrects the result of addition of two packed BCD values.
Implicit addressing mode.

Algorithm
If AL[L] > 9 or AF=1 then
AL=AL+06H
Set AF=1
If AL[H] > 9 or CF=1 then
AL=AL+60H
Set CF=1
14
DAS(Decimal Adjustment for Subtraction)

-
Corrects the result of subtraction of two packed BCD values.

Algorithm
If AL[L] > 9 or AF=1 then
AL=AL-06H
Set AF=1
If AL[H] > 9 or CF=1 then
AL=AL-60H
Set CF=1
15
CBW (Convert Byte to Word)

-
This instruction converts byte in AL to word in AX

Algorithm
If MSB of AL=1 then
AH = 255 (0FFh)
Else
16
AH=0
CWD (Convert Word to Double Word)

-
This instruction converts word in AX to double word in AX and DX

Algorithm
If MSB of AX=1 then
DX= 65535 (0FFFFh)
Swati R. Sharma
Page 26
Else
Advance Processors
UNIT-1
DX=0
BIT MANIPULATION (LOGICAL) INSTRUCTION

1
AND
-
Syntax: AND destination, source
Logical AND between all bits of two operands. Result is stored in destination.
Source can be a register, memory location or immediate value, while destination can be
either register or memory location
Flag CF and OF get reset and PF, SF and ZF get updated after the execution of this
instruction.
These rules apply:

1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
E.g.: AND AL, 11011111b
AND AX,BX
OR
-
Syntax: OR destination, source
Logical OR between all bits of two operands. Result is stored in destination.
either register or memory location.
instruction.
These rules apply:

1 OR 1 = 1
1 OR 0 = 1
0 OR 1 = 1
0 OR 0 = 0
E.g.: OR AL, 11011111b
OR AX,BX
NOT
-
Syntax: NOT destination
Invert each bit of the operand (1s compliment).
Destination cannot be immediate value or segment register.
No flags are affected.

Algorithm:
If bit is 1 then
Set bit to 0
Else if bit is 0 then
Set bit to 1
Swati R. Sharma
Page 27
Advance Processors
UNIT-1
E.g.: NOT AL
4
XOR
-
Syntax: XOR destination, source
It performs XOR operation of two operands. Result is stored in destination.
either register or memory location.
instruction.
These rules apply:

1 XOR 1 = 0
1 XOR 0 = 1
0 XOR 1 = 1
0 XOR 0 = 0
E.g.: XOR AL, BL
TEST
-
Syntax: TEST destination, source
Similar to AND instruction but result is not stored at destination.
Affects bits of flag registers

E.g.: TEST AX, BX
BIT MANIPULATION (SHIFT) INSTRUCTION

1
SHL/SAL (Shift Left/ Shift Arithmetic Left)

-
Syntax: SHL destination, count or SAL destination, count
It shift bits of byte or word left, by count and puts zero(s) in LSBs.
Destination can be either register or memory and source can be either immediate value or
count register (CX)
Algorithm
Step-1: Shift all the bits of operand to left
Step-2: set CF with MSB
Step-3: Shift 0 to LSB
E.g.: SHL AX,01H; Shift all the bits of AX to left once
SAL AX,CL; CL=02h, shift all the bits of AX to left twice
SHR( Shift Right)

-
Syntax: SHR destination, count
It shift bits of byte or word right, by count and puts zero(s) in LSBs.
count register (CX)
Algorithm
Step-1: Shift all the bits of operand to right
Step-2: set CF with LSB
Step-3: Shift 0 to MSB
Swati R. Sharma
Page 28
Advance Processors
UNIT-1
E.g.: SHR AX,01H; Shift all the bits of AX to right once.

3
SAR ( Shift Arithmetic Right)

-
Syntax: SAR destination, count
It shifts bits of byte or word right, by count.
Only difference between SHR and SAR is that, in SAR the MSB value will not change after
the execution shift right operation.
count register (CX).
Algorithm
Step-2: set CF with LSB
Step-3: Shift old_MSB (MSB before shift) to new_MSB (MSB after shift)
E.g.: SAR AX,01H; Shift all the bits of AX to right once
BIT MANIPULATION (ROTATE) INSTRUCTION

1
ROL (Rotate Left)

-
Syntax: ROL destination, count
It rotates bits of byte or word left, by count.
Algorithm
Step-2: Set CF with MSB
Step-3: Set LSB with MSB
E.g.: ROL AX,02H; Rotate all the bits of AX to left twice
ROL AX,CX; Rotate all the bits of AX to left CX times (CX=2h)
ROR (Rotate Right)

-
Syntax: ROR destination, count
It rotates bits of byte or word right, by count.
Algorithm
Step-2: Set CF with LSB
Step-3: Set MSB with LSB
E.g.: ROR AX,01H; Rotate all the bits of AX to right once
RCL (Rotate Left through carry)

-
Syntax: RCL destination, count
It rotates bits of byte or word left, by count through carry
Swati R. Sharma
Page 29
Advance Processors
UNIT-1

Algorithm
Step-2: Set LSB with CF
Step-3: Set new_CF with MSB
E.g.: RCL AX,01H; Rotate all the bits of AX and CF to left once
4
RCR (Rotate Right through carry)

-
Syntax: RCR destination, count
It rotates bits of byte or word right, by count.
Algorithm
Step-2: Set CF with MSB
Step-3: Set new_CF with LSB
E.g.: RCR AX,01H; Rotate all the bits of AX and CF to right once
PROCESSOR CONTROL INSTRUCTION

FLAG OPERATION
1
STC (Set Carry Flag)

-
This instruction set the value of carry flag to 1
Except CF no other flags are affected

Algorithm: set CF=1
CLC (Clear Carry Flag)

-
This instruction reset the value of carry flag to 0

Algorithm: set CF=0
CMC (Compliment Carry Flag)

-
This instruction compliments the value of CF.

Algorithm:
If CF=0 then, CF=1
Else if CF=1 then, CF=0
STD (Set Direction Flag)

-
This instructions set the value of direction flag to 1

SI and DI will be decremented.
Except DF no other flags are affected
Swati R. Sharma
Page 30
Advance Processors
UNIT-1
Algorithm: set DF=1

5
CLD (Clear Direction Flag)

-
This instructions set the value of direction flag to 0
SI and DI will be incremented.
Except DF no other flags are affected

Algorithm: set DF=0
STI (Set Interrupt Flag)

-
Set Interrupt enables flag.
This enables INTR interrupt of 8086
Except IF no other flags are affected

Algorithm: set IF=1
CLI (Clear Interrupt Flag)

-
Reset Interrupt enable flag.
8086 will not respond to interrupt signal on INTR input.
Except IF no other flags are affected
CLI has no effect on NMI.

Algorithm:
set IF=0
NO OPERATION
1
NOP (No Operation)

-
Execution of this instruction causes CPU to do nothing.
This instruction uses 3-clock cycles and increments the IP to the point of next instruction.
It is used to delay the execution.
Implicit Addressing mode and does not affect any flag.
EXTERNAL SYNCHRONIZATION
1
HLT
-
Halt the System.
Instruction will stop Fetch and execute operation.
This instruction is used as a alternative to an endless software loop.
Ways to recover from the HLT instruction are as follows:

i.
Interrupt signal on INTR pin.
ii.
Interrupt signal on NMI pin.
iii.
Enable RESET pin.
E.g.: MOV AX, 5

HLT
Swati R. Sharma
Page 31
Advance Processors
UNIT-1
WAIT
-
This pin is used to synchronize 8086 with external hardware.
8086 will stay in IDLE state when this instruction executes and remain until TEST pin is
made low or INTR / NMI pin is enabled.
ESC
-
Syntax: Opcode, source
It is used to pass instruction to co-processor e.g. 8087 math co-processor.
When 8086 fetches instruction, the co-processor decodes the instruction and carries out
task specified in 6-bit Opcode embed within instruction.
LOCK
-
It is a PREFIX instruction.
This instruction allows microprocessor to make sure that another processor does not take
control over the system bus.
In 8086 the individual microprocessor are connected together by a shared system bus.
Thus, LOCK prefix prevents any other processor from taking over the system bus in middle
of critical instruction execution.
PROGRAM CONTROL INSTRUCTION

UNCONDITIONAL TRANFER INSTRUCTION
1
JMP (unconditional jump)

-
Syntax: JMP label
Transfers control to another part of the program.

E.g.: MOV AL, 5
JMP label1
; jump to label 1
MOV AL, 0
label1:
MOV BL,0
2
CALL
-
Syntax: CALL procedure name
Transfers control to procedure.
Instruction is used to call subroutine from main program.
Two types of Call

i.
NEAR CALL: Intra-segment CALL (call within segment)
ii.
FAR CALL: Inter-segment CALL (call outside segment)
E.g.: CALL p1
ADD AX, 1
RET
; return to OS.
p1 PROC
; procedure declaration.
MOV AX, 1234h

RET
Swati R. Sharma
; return to caller.
Page 32
Advance Processors
UNIT-1
p1 ENDP
3
RET
-
Return from procedure.
When this instruction executes the previous stored content of IP, CS and flag registers are
retrieved back.
E.g.: p1 PROC
; procedure declaration.
MOV AX, 1234h

RET
; return to caller.
p1 ENDP
CONDITIONAL TRANFER INSTRUCTION
1
JC (Jump if Carry)
-
Syntax: JC label
Algorithm
if CF = 1 then jump to label
JNC(Jump if Not Carry)

-
Syntax: JNC label

Algorithm
if CF = 0 then jump to label
JO(Jump if Overflow)
-
Syntax: JO label
Algorithm
if OF = 1 then jump to label
JNO(Jump if Not Overflow)

-
Syntax: JNO label

Algorithm
if OF = 0 then jump to label
JZ/JE(Jump if Zero/Equal)
-
Syntax: JZ label/ JE label
This instruction refers to the result of CMP instruction

Algorithm
if ZF = 1 then jump to label
JNZ/JNE(Jump if NOT Zero/Equal)

-
Syntax: JNZ label/ JNE label
This instruction refers to the result of CMP instruction.

Algorithm
if ZF = 0 then jump to label
JP/JPE(Jump if Parity/Parity is EVEN)

-
Syntax: JP label/ JPE label

Algorithm
if PF = 1 then jump to label
Swati R. Sharma
Page 33
JNP/JPO(Jump if Not Parity/Parity is ODD)

-
Syntax: JNP label/ JPO label

Algorithm:
Advance Processors
UNIT-1
if PF = 0 then jump to label
JS(Jump if Sign)
-
Syntax: JS label
This instruction will jump to the label when number is negative.

Algorithm
if SF = 1 then jump to label
10
JNS(Jump if Not Sign)

-
Syntax: JNS label
This instruction will jump to the label when number is positive.

Algorithm
if SF = 0 then jump to label
11
JL/JNGE(Jump if Less/Jump if Not Greater or Equal)

-
Syntax: JL label/JNGE label

Algorithm
If SF < > OF then jump to label
12
JNL/JGE(Jump if Not Less/Jump if Greater or Equal)

-
Syntax: JNL label/JGE label

Algorithm
If SF = OF then jump to label
13
JLE/JNG(Jump if Less or Equal/Jump if Not Greater)

-
Syntax: JLE label/JNG label

Algorithm
If SF < > OF or ZF = 1 then jump to label
14
JNLE/JG(Jump if Not Less or Equal/Jump if Greater)

-
Syntax: JNLE label/JG label

Algorithm
If (ZF = 0) and (SF = OF) then jump to label
15
JB/JNAE(Jump if Below/Jump if Not Above or Equal)

-
Syntax: JB label/JNAE label

Algorithm
If CF = 1 then jump to label
Swati R. Sharma
Page 34
16
Advance Processors
UNIT-1
JNB/JAE(Jump if Not Below/Jump if Above or Equal)

-
Syntax: JNB label/JAE label

Algorithm
If CF = 0 then jump to label
17
JBE/JNA(Jump if Below or Equal/Jump if Not Above)

-
Syntax: JBE label/JNA label

Algorithm
If CF = 1 or ZF=1 then jump to label
18
JNBE/JA(Jump if Not Below or Equal/Jump if Above)

-
Syntax: JNBE label/JA label

Algorithm
If (CF = 0) and (ZF = 0) then jump to label
ITERATION CONTROL INSTRUCTION

1
LOOP
-
Syntax: LOOP label
This instruction is used for the repetition of group of instruction.
Instruction refers to auto decrement counter register (CX) for loop count.
Algorithm
CX=CX-1
If CX < > 0 then jump to the label
LOOPE/LOOPZ (LOOP if Equal/Zero)

-
Syntax: LOOPE label/ LOOPZ label
This instruction is used for the repetition of group of instruction if ZF is set.
Algorithm
CX=CX-1
If CX < > 0 and ZF=1 then jump to the label
LOOPNE/LOOPNZ(LOOP if Not Equal/Not Zero)

-
Syntax: LOOPE label/ LOOPZ label
This instruction is used for the repetition of group of instruction if ZF is set.
Algorithm
CX=CX-1
If CX < > 0 and ZF=0 then jump to the label
Swati R. Sharma
Page 35
Advance Processors
UNIT-1
INERRUPT CONTROL INSTRUCTION

This instruction allows ISR to be activated by program as well by the external hardware.
1
INT
-
Syntax: INT type
Instruction causes 8086 to call far procedure
Type refers to the range between (0-255)

Algorithm:
Step-1:Push flag register to stack
Step-2: Push CS to stack
Step-3: Push IP to stack
Step-4: Calculate new value of IP
New IP=Type*4
Step-5: Calculate new value of CS
New CS= IP+2
Step-6: Reset IF and TF
E.g.: INT 21H

2
INTO (Interrupt if Overflow)

-
This instruction will cause 8086 to do an indirect far call to the procedure that handles
overflow condition.
Algorithm:
If OF=1 then INT
Reset IF and TF
IRET (Interrupt Return)

-
Instruction is used to end Interrupt Service Routine.

Algorithm:
Step-1: POP IP
Step-2: POP CS
Step-3: POP Flag Register
9.
Explain Minimum mode of 8086 in detail.
Ans
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic1.
In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system. The remaining components in the
system are latches, transceivers, clock generator, memory and I/O devices.
Some type of chip selection logic may be required for selecting memory or I/O devices, depending
upon the address map of the system.
Swati R. Sharma
Page 36
Advance Processors
UNIT-1
Block diagram for Minimum mode of 8086 is shown below:-
Figure: Minimum Mode of 8086

Timing Diagram
The working of the minimum mode configuration system can be better described in terms of the
timing diagrams rather than qualitatively describing the operations.

T-State: One clock period is referred to as a T-State. An operation takes an integer number of T-
States.
CPU Bus Cycle: A bus cycle consists of 4 or more T-States.
Since a memory read or write should be complete within one bus-cycle (4-CLK pulses, T1 -T4),
related timing states as follows:
-
T1 (1st clock pulse)- starts the bus cycle. Actions include setting control signals to give the
required logic values for IO/M, ALE, DT/R and a valid address onto the address bus.
T2 - the RD or WR control signals are issued, DEN is asserted and in the case of a write, data is
put onto the data bus.
The DEN turns on the data bus buffers to connect the CPU to the external data bus.
The READY input to the CPU is sampled at the end of T2 and if READY is low, wait state (TW) is
inserted before T3 begins.
T3 - this clock period is provided to allow memory to access the data. If the bus cycle is a read
Swati R. Sharma
Page 37
Advance Processors
UNIT-1
cycle, the data bus is sampled at the end of T3 or the 3rd clock pulse of the bus-cycle.
-
T4 - all bus signals are deactivated in preparation for the next clock cycle.
The 8088 also finishes sampling the data (in a read cycle) in this period.
For the write cycle, the trailing edge of the WR signal transfers data to the memory.
Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read
cycle and the second is the timing diagram for write cycle shown below.
Figure: Read Cycle of Minimum Mode
Figure: Write Cycle of Minimum Mode
Read Cycle
To complete the minimum-mode memory-read bus-cycle, the required control signals with appropriate
active logic levels are :
-
IO/M = logic 0, to select memory interface
MN/MX = logic 1, to select minimum-mode of operation
DT/R = logic 0, to activate the data-receive mode of Data-bus-buffer
Valid Physical-address of memory-location via address-bus (A19 to A0)
ALE-pulse, to latch the valid Physical-address
RD = logic 0, to initiate reading data into CPU. Note, WR = logic 1
DEN = 0, enables the Data-Bus-transceiver-buffer to let data pass
Reset RD=DEN=logic1, to END the read-bus-cycle.
Write Cycle
To complete the minimum-mode memory-write bus-cycle, the required control signals with appropriate
-
MN/MX = logic 1, to select minimum-mode of operation
DT/R = logic 1, to activate the data-transmit mode of Data-bus-buffer
Valid Physical-address of memory-location via address-bus (A19 to A0)
ALE-pulse, to latch the valid Physical-address.
WR = logic 0, to initiate memory data writing. Note, RD = logic 1
Reset WR=DEN=logic1, to END the write-bus-cycle.
Swati R. Sharma
Page 38
Advance Processors
UNIT-1
10.
Ans
Explain Maximum mode of 8086 in detail.

In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type
8087 or another processor is interfaced with 8086.

-
The Memory, Address Bus, Data Buses are shared resources between the processors.
The control signals for Maximum mode of operation are generated by the Bus Controller chip
8788.
Block diagram for Maximum mode of 8086 is shown below:-
Figure: Maximum Mode of 8086
In Maximum mode, for multiprocessor environment WR, IO/M, DT/R, DEN, ALE, INTA signals are
not available. Instead available signals are as follows:MRDC (memory read command)
MWRT (memory write command)
IORC (I/O read command)
IOWC (I/O write command)
INTA (interrupt acknowledge)
Swati R. Sharma
Page 39
Advance Processors
UNIT-1
The below table shows the Operation carried out by Maximum Mode.
S2
S1
S0
Machine Language
Interrupt acknowledgement
Read I/O
Write I/O
HALT
Code Access
Read Memory
Write Memory
Passive
Table: Operation carried out by Maximum Mode
Figure: Read Cycle of Maximum Mode
Figure: Write Cycle of Maximum Mode
Read Cycle
To complete the minimum-mode memory-read bus-cycle, the required control signals with appropriate
-
MN/MX = logic 0, to select maximum-mode of operation
DT/R = logic 0, to activate the data-receive mode of Data-bus-buffer
Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
Proper status code S0 to S2 (as shown in table of slide 8) is generated by
CPU to initiate data reading (MRDC) from the desired memory bank
Reset MRDC and DEN signals to END the read-bus-cycle
Swati R. Sharma
Page 40
Advance Processors
UNIT-1
Write Cycle
To complete the maximum-mode memory-write bus-cycle, the required control signals with appropriate
-
MN/MX = logic 0, to select maximum-mode of operation
DT/R = logic 1, to activate the data-transmit mode of Data-bus-buffer
Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
Proper status code S0 to S2 (as shown in table of slide 8) is generated by
CPU to initiate data writing (MRTC) from the desired memory bank
Reset MRTC and DEN signals to END the read-bus-cycle
11.
Differentiate minimum and maximum mode of 8086.
Ans
Maximum Mode
i.
When MN/MX (bar) low 8086 is in maximum mode.
ii. There are multiple processors in the system

iii. Maximum mode unique signals
Name
Function
RQ/GT
Request/ Grant bus access control
0,1
LOCK
Bus priority lock control
Status
Bus cycle status
QS 0,1
Instruction queue status
iv. In maximum mode interfacing, master/slave and multiplexing and several such control signals
are required.
v. In maximum mode a bus controller is required to produce control signals. This bus controller
produces MEMRDC, MEMWRC, IORDC, IOWRC, ALE, DEN, DT/R control signals.
vi. Maximum mode operation control signals must be generated externally requires an additional
external bus controller 8288. Thus maximum mode operation is more expensive.
Minimum Mode
i.
When MN/MX (bar) high 8086 is in minimum mode.
ii. There is only one processor in the system minimum mode.

iii. In minimum mode no interfacing or master/slave signals is required.
iv. In minimum mode direct RD WR signals can be used. No bus controller required. A simple demultiplexer would do the job of producing the control signals.
Minimum mode operation is less expensive as all the control signal is generated for the
input/output and memory by processor itself.
Swati R. Sharma
Page 41
Advance Processors
UNIT-1
v. Minimum mode unique signals
12.
Ans
Name
Function
HOLD
Hold request
HLDA
Hold acknowledge
WR
Write control
IO/M
Input output/ memory control
DT/R
Data transmit/ receive
DEN
Data enable
Status
Status line
ALE
Address Latch Enable
INTA
Interrupt acknowledge
Explain Memory bank. Briefly explain ODD and EVEN bank concept in 8086.
-
A memory bank is a designated section of computer memory used for storing data.
In 8086 there is 20 bit address bus, so it can address 1,048,576 addresses. At each address we
can store 8 bit address (1-byte)but if want to write a word(16-bit)into a memory segment to
store data in byte form then we write the data in two consecutive memory address which are
even(low) and odd(high) memory.
The 8086 memory address space can be viewed as a sequence of one million bytes in which any
byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit
data element.
There is no constraint on byte or word address boundaries.
The address space is physically connected to a 16-bit data bus by dividing the address space into
two 8-bit banks of up to 512K bytes each.
Even Memory bank

-
One bank is connected to the lower half of the 16-bit data bus (D0 D7) and contains even
address bytes. i.e., when A0 bit is low, the bank is selected.
To access memory bytes from Even address, information is transferred over the lower half of the
data bus (D0 - D7). The A0 is output LOW and BHE is output HIGH enabling only the even
address bank.
Odd Memory bank

-
The other bank is connected to the upper half of the data bus (D8 - D15) and contains odd
address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank is selected.
To access memory byte from an odd address information, is transferred over the higher half of
the data bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is output high
to disable the lower memory bank.
Swati R. Sharma
Page 42
Advance Processors
UNIT-1
Figure: Memory Bank

13.
Ans
Instruction format 8086

-
The 8086 instruction sizes vary from one to six bytes.
Depending on the type of coding, an instruction may have more than one Hexcode.
The Opcode field occupies 6-bits. It defines the operation to be carried out by the instruction.
Figure: 8086 Instruction format

-
Register Direct bit (D) occupies one bit. It defines whether the register operand in byte 2 is the
source or destination operand.
D=1 Specifies
that
the
register
operand is
the
destination
operand.
D=0 indicates that the register is a source operand.

-
Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data.
W=0 indicates 8 bit operation

W=1 indicates 16 bit operation
Mod Bits 6-7 (mode; determines how R/M field is interpreted)
Reg Bits 3-5 (register) or SREG (Seg register)
Swati R. Sharma
Page 43
R/M Bits 0-2 (register/memory)
The instruction format of 8086 is shown below.
Advance Processors
UNIT-1
14.
Briefly explain short, near direct and far jump in 8086.
Ans
Short jump:
A near jump where the jump range is limited to -128 to +127 from the current value.
Near jump:
A jump to an instruction within the current code segment (the segment currently pointed
to by the CS register), sometimes referred to as an intra-segment jump.
Far jump:
A jump to an instruction located in a different segment than the current code segment
but at the same privilege level, sometimes referred to as an intersegment jump.
15.
Explain Assembler Directives.
Ans
An assembler directive is a statement to give direction to the assembler to perform the task of
assembly process.
The assembler directives control organization of the program and provide necessary information
to the assembler to understand assembly language programs to generate machine codes.
They indicate how an operand or section of a program is to be processed by the assembler.
An assembler supports directives to define data, to organize segments to control procedures, to

define macros etc.
The Assembler Directives of 8086 are shown below.

1.
SEGMENT:
The SEGMENT directive is used to indicate the start of a logical segment.

Preceding the SEGMENT directive is the name you want to give the segment. For
example, the statement CODE SEGMENT indicates to the assembler the start of
a logical segment called CODE. The SEGMENT and ENDS directive are used to
bracket a logical segment containing code of data.
2.
ENDS:
This directive is used with the name of a segment to indicate the end of that
logical segment.
CODE SEGMENT; Start of logical segment containing code instruction statements
CODE ENDS;End of segment named CODE
3.
END:
The END directive is put after the last statement of a program to tell the
assembler that this is the end of the program module. The assembler will ignore
any statements after an END directive, so you should make sure to use only one
END directive at the very end of your program module. A carriage return is
required after the END directive.
4.
ASSUME:
The ASSUME directive is used tell the assembler the name of the logical
segment it should use for a specified segment. The statement ASSUME CS:
CODE, for example, tells the assembler that the instructions for a program are
in a logical segment named CODE. The statement ASSUME DS: DATA tells the
assembler that for any program instruction, which refers to the data segment, it
should use the logical segment called DATA.
5.
DB:
The DB directive is used to declare a byte type variable, or a set aside one or
(DEFINE BYTE)
more storage locations of type byte in memory.
Swati R. Sharma
Page 44
Advance Processors
UNIT-1
E.g.
PRICES DB 49H, 98H, 29H
;Declare array of 3 bytes named PRICE and
initialize them
NAMES DB THOMAS ;Declare array of 6 bytes and initialize with ASCII codes
TEMP DB 100 DUP (?)
; Set aside 100 bytes of storage in memory and give it

the name TEMP. But leave the 100 bytes un-initialized.
PRESSURE DB 20H DUP (0);Set aside 20H bytes of storage in memory, give it
the name PRESSURE and put 0 in all 20H locations.
6.
DW:
The DW directive is used to tell the assembler to define a variable of type word
(DEFINE WORD)
or to reserve storage locations of type word in memory. The statement

MULTIPLIER DW 437AH, for example, declares a variable of type word named
MULTIPLIER, and initialized with the value 437AH when the program is loaded
into memory to be run.
E.g.
WORDS DW 1234H, 3456H
;Declare an array of 2 words and initialize them
STORAGE DW 100 DUP (0) ;Reserve an array of 100 words of memory and
initialize all
100 words with 0000. Array is
named as STORAGE.
STORAGE DW 100 DUP (?)
; Reserve 100 word of storage in memory and give

it name STORAGE, but leave the words uninitialized.
7.
DD:
The DD directive is used to declare a variable of type double word or to reserve
(DEFINE
memory locations, which can be accessed as type double word. The statement
DOUBLE WORD)
ARRAY DD 25629261H, for example, will define a double word named ARRAY
and initialize the double word with the specified value when the program is
loaded into memory to be run. The low word, 9261H, will be put in memory at a
lower address than the high word.
8.
DQ:
The DQ directive is used to tell the assembler to declare a variable 4 words in
(DEFINE
length or to reserve 4 words of storage in memory. The statement BIG_NUMBER
QUADWORD)
DQ
243598740192A92BH,
for
example,
will
declare
variable
named
BIG_NUMBER and initialize the 4 words set aside with the specified number
when the program is loaded into memory to be run
9.
DT:
The DT directive is used to tell the assembler to declare a variable, which is 10
(DEFINE TEN
bytes in length or to reserve 10 bytes of storage in memory. The statement
BYTES)
PACKED_BCD
DT
11223344556677889900
will
declare
an
array
named
PACKED_BCD, which is 10 bytes in length. It will initialize the 10 bytes with the
values 11, 22, 33, 44, 55, 66, 77, 88, 99, and 00 when the program is loaded
into memory to be run. The statement RESULT DT 20H DUP (0) will declare an
array of 20H blocks of 10 bytes each and initialize all 320 bytes to 00 when the
program is loaded into memory to be run.
Swati R. Sharma
Page 45
10.
Advance Processors
UNIT-1
EQU:
EQU is used to give a name to some value or symbol. Each time the assembler
(EQUATE)
finds the given name in the program, it replaces the name with the value or
symbol you equated with that name. Suppose, for example, you write the
statement FACTOR EQU 03H at the start of your program, and later in the
program you write the instruction statement ADD AL, FACTOR. When the
assembler codes this instruction statement, it will code it as if you had written
the instruction ADD AL, 03H.
11.
LENGTH:
LENGTH is an operator, which tells the assembler to determine the number of

elements in some named data item, such as a string or an array. When the
assembler reads the statement MOV CX, LENGTH STRING1, for example, will
determine the number of elements in STRING1 and load it into CX. If the string
was declared as a string of bytes, LENGTH will produce the number of bytes in
the string. If the string was declared as a word string, LENGTH will produce the
number of words in the string.
12.
OFFSET:
OFFSET is an operator, which tells the assembler to determine the offset or

displacement of a named data item (variable), a procedure from the start of the
segment, which contains it. When the assembler reads the statement MOV BX,
OFFSET PRICES, for example, it will determine the offset of the variable PRICES
from the start of the segment in which PRICES is defined and will load this value
into BX.
13.
PTR:
(POINTER)
The PTR operator is used to assign a specific type to a variable or a label. It is

necessary to do this in any instruction where the type of the operand is not
clear. When the assembler reads the instruction INC [BX], for example, it will
not know whether to increment the byte pointed to by BX. We use the PTR
operator to clarify how we want the assembler to code the instruction. The
statement INC BYTE PTR [BX] tells the assembler that we want to increment the
byte pointed to by BX. The statement INC WORD PTR [BX] tells the assembler
that we want to increment the word pointed to by BX. The PTR operator assigns
the type specified before PTR to the variable specified after PTR.
14.
EVEN:
The EVEN directive tells the assembler to increment the location counter to the
next even address, if it is not already at an even address. A NOP instruction will
be inserted in the location incremented over.
15.
PROC:
The PROC directive is used to identify the start of a procedure. The PROC
(PROCEDURE)
directive follows a name you give the procedure. After the PROC directive, the
term near or the term far is used to specify the type of the procedure. The
statement DIVIDE PROC FAR, for example, identifies the start of a procedure
named DIVIDE and tells the assembler that the procedure is far.
Swati R. Sharma
Page 46
16.
Advance Processors
UNIT-1
ENDP:
The directive is used along with the name of the procedure to indicate the end of
(END
a procedure to the assembler. The directive, together with the procedure
PROCEDURE)
directive, PROC, is used to bracket a procedure.

DIET_CE PROC; Start of procedure
DIET_CE ENDP; End of procedure
17.
ORG:
The ORG directive allows you to set the location counter to a desired value at
(ORIGIN)
any point in the program. The statement ORG 2000H tells the assembler to set
the location counter to 2000H.
18.
NAME:
The NAME directive is used to give a specific name to each assembly module
when programs consisting of several modules are written.
19.
LABEL:
The LABEL directive is used to give a name to the current value in the location
counter. The LABEL directive must be followed by a term that specifics the type
you want to associate with that name.
20.
EXTRN:
The EXTRN directive is used to tell the assembler that the name or labels
following the directive are in some other assembly module. For example, if you
want to call a procedure, which in a program module assembled at a different
time from that which contains the CALL instruction, you must tell the assembler.
21.
PUBLIC:
The PUBLIC directive is used to tell the assembler that a specified name or label
will be accessed from other modules. An example is the statement PUBLIC
DIVISOR, DIVIDEND, which makes the two variables DIVISOR and DIVIDEND
available to other assembly modules.
22.
SHORT:
The SHORT operator is used to tell the assembler that only a 1 byte
displacement is needed to code a jump instruction in the program. The
destination must in the range of 128 bytes to +127 bytes from the address of
the instruction after the jump. The statement JMP SHORT NEARBY_LABEL is an
example of the use of SHORT.
23.
TYPE:
The TYPE operator tells the assembler to determine the type of a specified
variable. The assembler actually determines the number of bytes in the type of
the variable. For a byte-type variable, the assembler will give a value of 1, for a
word-type variable, the assembler will give a value of 2, and for a double wordtype variable, it will give a value of 4.
24.
GLOBAL:
The GLOBAL directive can be used in place of a PUBLIC directive or in place of

an EXTRN directive. For a name or symbol defined in the current assembly
module, the GLOBAL directive is used to make the symbol available to other
modules. The statement GLOBAL DIVISOR, for example, makes the variable
DIVISOR public so that it can be accessed from other assembly modules.
25.
INCLUDE:
This directive is used to tell the assembler to insert a block of source code from
the named file into the current source module.
Swati R. Sharma
Page 47
16.
Ans
Advance Processors
UNIT-1
What is the minimum and maximum size of a segment in 8086? How are they computed?
-
In 8086 microprocessor the total memory addressing capability is 1 mega bytes.
For representing 1MB there are minimum 4 hex digits are required i.e., 20 bits, but 8086 has
fourteen 16-bit registers. That is there are no registers for representing 20 bit address. So, the
total memory is divided into 16 logical segments and each segment capacity is 64 KB (kilo
bytes).
17.
Ans
That is 16*64kb=1 MB. So, for representing 64 kb only 16 bit register is sufficient.
Therefore, Size of segments is from minimum 64KB to maximum 1MB.
How to define a stack in 8086 assembly language program.

-
The stack is the section of memory used for pushing or popping registers and storing the return
address when a subroutine is called.
The stack often holds temporary and local variables.
If the main module is written in a high-level language, that language handles the details of
creating a stack.
Use the .STACK directive only when writing a main module in assembly language.
The .STACK directive creates a stack segment.
By default, the assembler allocates 1K of memory for the stack. This size is sufficient for most
small programs.
To create a stack of a size other than the default size, give .STACK a single numeric argument
indicating stack size in bytes:
E.g.
.STACK 2048
18.
Ans
; Use 2K stack
Explain Macro
-
MACRO is a sequence of instructions to which a name is assigned is called macro.

Macros and subroutines are similar. Macros are used for short sequence of instructions whereas
subroutines for longer ones.
Macros executes faster than subroutines.
The MACRO directive informs assembler the beginning of a macro.
This is used with ENDM directive to enclose a macro.
The general format of the MACRO directive is :

Macro
definition:
name
MACRO [parameters...]
<instructions>
ENDM
-
The difference is that a procedure is accesses via a CALL instruction, while a macro and all the
instructions defined in the macro, are inserted in the program at the point of usage.
Creating macro is very similar to creating a new op-code that can be used in the program.
Swati R. Sharma
Page 48
Advance Processors
UNIT-1
Example:
MyMacro
MACRO p1, p2, p3
MOV AX, p1
MOV BX, p2
MOV CX, p3
ENDM
-------------------------------------------ORG 100h
MyMacro 1, 2, 3
MyMacro 4, 5, DX
RET
19.
The interrupt vector table is always created in the first 1K area of the memory. Justify the
statement.
Ans
When the CPU receives an interrupt type number from the PIC, it uses this number to look up the
corresponding interrupt vector in memory. There are 256 interrupt types. Each interrupt vector occupies
4 bytes. Therefore, a total of 4 x 256 = 1K bytes of memory is reserved at the beginning of the
processor memory address space for storing interrupt vectors.
20.
Explain the operation of IRET instruction.
Ans
The Interrupt return (IRET) instruction is used only with software or hardware interrupt service
procedures. Whenever an IRET instruction executes, it stores the contents of I and T from the stack. This
is important because it preserves the state of the flag bits. If interrupts were enabled before an interrupt
service procedure, they automatically re-enabled by the IRET instruction because it restores the flag
register.
21.
Explain Memory Models in 8086
Ans
The Memory models used in 8086 are as follows:-
Tiny:
Code and data combined must be less than 64K
Small:
Code <=64K and Data<= 64K
Medium:
Data<=64K code any size multiple code segment
Compact:
Code<=64K data any size multiple data segment
Large:
Code>64K and data>64K multiple code and data segment
Huge:
Same as the Large except that individual section can be > 64K
Swati R. Sharma
Page 49

AP Material Unit-1 PDF

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

AP Material Unit-1 PDF

Uploaded by

Copyright:

Available Formats

Darshan Institute of

Engineering & Technology

Define the Following.

It is a multipurpose, programmable device that accepts digital data as input,

An assembler or macro-assembler generally forms a part of the operating

A large program is divided in smaller programs known as modules. A linker is a

The stack is an area of memory identified by the programmer for temporary

A subroutine is a group of instructions that will be used repeatedly in different

An instruction is a binary pattern designed inside a microprocessor to perform a

selects the operation performed by the microprocessor

The data on which the operation is to be performed as well as the result of an

Interrupt is a change of path in program execution caused by hardware request,

A small program or a routine that when executed services the corresponding

A group of lines, pins or signals having common function is teamed as bus.

The processing speed of microprocessor depends upon the clock frequency.

Program execution speed is determined by this parameter (number of

Introduction to 8086 microprocessor OR Features of 8086 microprocessor

8086 is a 16-bit processor, which implies that

16-bit data bus

16-bit ALU, that perform 16-bit operation at the same time

There are three versions based on the frequency of operation

In 8086 two Unit works in parallel:

Bus Interface Unit (BIU)

Execution Unit (EU)

8086 has 256 vectored interrupt.

8086 is a pipelined processor

8086 is two staged pipelined architecture:

Execute stage: Executes the instruction

8086 can operate in 2 modes

Minimum mode: A system with only one processor i.e.8086

Maximum mode: A system with multiple processors.

8086 uses memory bank

In 8086 entire data is not stored in single sequential memory of 1MB.

The memory is divided into two banks of 512KB each.

8086 uses memory segmentation

Segmentation means dividing memory into logical components.

Explain 8086 Architecture

The Block diagram for the internal architecture of 8086 is as follows:-

Instruction pointer (IP)

Address Generation and bus control

Task carried out by BIU

Fetch instruction from memory

Read/ Write instruction from / to the memory

Input/ Output (I/O) of data from / to peripheral ports

Write the data to memory.

Address generation for memory reference

BIU works in synchronous with machine cycles

ALU (Arithmetic logic Unit)

General Purpose Registers (GPR)

Decoder (instruction decoder)

Decodes the instruction

It executes instructions ( executes decoded instructions)

Tells BIU from where to fetch the instruction

Decodes instruction (decode the fetched instruction)

EU takes care of performing operation on the data

EU is also known as execution heart of the processor

Explain 8086 Registers

CF- Carry Flag

TF- Trap Flag

PF- Parity Flag

IF- Interrupt Flag

AF- Auxiliary Flag