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DuoLu<
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>
Outline
Themicrocontroller(similartoMicrochipPIC12,simplifiedextensively,notcompatiblein
instructionset)inthisprojectisa3cyclenonpipeline8bitHarvardstructuremicrocontroller,
illustratedasthefollowingblockdiagram.Thestagegroupincludescomponentsworkingin
thatstage.Datapathisshownasblackarrows,andcontrolsignalsareredarrows.
Thefollowingtwotypeofcomponentsholdprogrammingcontext.
Programcounter,programmemory,datamemory,accumulator,statusregister(green
boxes).Theyareprogrammervisibleregistersandmemories.
Instructionregisteranddataregister(purpleboxes).Theyareprogrammerinvisible
registers.
Thefollowingtwotypeofcomponentsarebooleanlogicsthatdotheactualcomputationwork.
Theyarestateless
ALU,MUX1,MUX2,Adder(blueboxes),usedasfunctionalunit.
ControlLogic(yellowbox),usedtodenoteallcontrolsignals(redsignal)
Thetimingandstatetransitionisshowninthefollowingdiagram.
Eachinstructionneeds3clockcyclestofinish,i.e.FETCHstage,DECODEstage,and
EXECUTEstage.Notethatitisnotpipelined.TogetherwiththeinitialLOADstate,itcanbe
consideredasaFSMof3states(technically4states).
States:
1. LOAD(initialstate):loadprogramtoprogrammemory,whichtakes1cycleper
instructionloaded
2. FETCH(firstcycle):fetchcurrentinstructionfromprogrammemory
3. DECODE(secondcycle):decodeinstructiontogeneratecontrollogic,readdata
memoryforoperand
4. EXECUTE(ofthirdcycle):executeinstruction
Transitions:
1. LOAD>FETCH(initializationfinish)
a. ClearcontentofPC,IR,DR,Acc,SRDMemisnotrequiredtobecleared.
2. FETCH>DECODE(risingedgeofsecondcycle)
a. IR=PMem[PC]
3. DECODE>EXECUTE(risingedgeofthirdcycle)
a. DR=DMem[IR[3:0]]
4. EXECUTE>FETCH(risingedgeoffirstcycleandfourthcycle)
a. Fornonbranchinstruction,PC=PC+1forbranchinstruction,ifbranchis
taken,PC=IR[7:0],otherwisePC=PC+1
b. ForALUinstruction,iftheresultdestinationisaccumulator,Acc=ALU.Outif
theresultdestinationisdatamemory,DMem[IR[3:0]]=ALU.Out.
c. ForALUinstruction,SR=ALU.Status
Thetransitionscanbesimplifiedusingenableportofcorrespondingregisters,e.g.assign
ALU.OuttoAccateveryclockrisingedgeifAcc.Eissetto1.SuchcontrolsignalsasAcc.E
aregeneratedasabooleanfunctionofbothcurrentstateandthecurrentinstruction.
Components
Registers
Themicrocontrollerhas3programmervisibleregister:
1. ProgramCounter(8bit,denotedasPC):containstheindexofcurrentexecuting
instruction.
2. Accumulator(8bit,denotedasAcc):holdsresultand1operandofthearithmeticor
logiccalculation.
3. StatusRegister(4bit,denotedasSR):holds4statusbit,i.e.Z,C,S,O.
a. Z(zeroflag,SR[3]):1ifresultiszero,0otherwise.
b. C(carryflag,SR[2]):1ifcarryisgenerated,0otherwise.
c. S(signflag,SR[1]):1ifresultisnegative(as2scomplement),0otherwise.
d. O(overflowflag,SR[0]):1ifresultgeneratesoverflow,0otherwise.
Eachoftheseregistershasanenableport,asaflagforwhetherthevalueoftheregister
shouldbeupdatedinstatetransition.TheyaredenotedasPC.E,Acc.E,andSR.E.
Themicrocontrollerhas2programmerinvisibleregister(i.e.theycannotbemanipulatedby
programer):
1. InstructionRegister(12bit,denotedasIR):containsthecurrentexecutinginstruction.
2. DataRegister(8bit,denotedasDR):containstheoperandreadfromdatamemory.
Similarly,eachoftheseregistershasanenableportasaflagforwhetherthevalueofthe
registershouldbeupdatedinstatetransition.TheyaredenotedasIR.E,andDR.E.
Program memory
Themicrocontrollerhasa256entryprogrammemorythatstoresprograminstructions,
denotedasPMem.Eachentryis12bits,theithentryisdenotedasPMem[i].Theprogram
memoryhasthefollowinginput/outputports.
Enableport(1bit,input,denotedasPMem.E):enablethedevice,i.e.ifitis1,thenthe
entryspecifiedbytheaddressportwillbereadout,otherwisenothingisreadout.
Addressport(8bit,input,denotedasPMem.Addr):specifywhichinstructionentryis
readout,connectedtoPC.
Instructionport(12bit,output,denotedasPMem.I):theinstructionentrythatisread
out,connectedtoIR.
3specialportsareusedtoloadprogramtothememory,notusedforexecutinginstructions.
Loadenableport(1bit,input,denotedasPMem.LE):enabletheload,i.e.ifitis1,
thentheentryspecifiedbytheaddressportwillbeloadwiththevaluespecifiedbythe
loadinstructioninputportandtheinstructionportissuppliedwiththesamevalue
otherwise,theentryspecifiedbytheaddressportwillbereadoutoninstructionport,
andvalueoninstructionloadportisignored.
Loadaddressport(8bit,input,denotedasPMem.LA):specifywhichinstructionentry
isloaded.
Loadinstructionport(12bit,input,denotedasPMem.LI):theinstructionthatisloaded.
Forexample,iftheaddresspointissuppliedwith8b0000_0011andenableissetto1,the
fourthentryisreadoutoninstructionport.
Notethatprogramloadonlytakeseffectonclockrisingedge,whileinstructionreadout
happensallthetime.
Data memory
Themicrocontrollerhasa16entrydatamemory,denotedasDMem.Eachentryis8bits,the
ithentryisdenotedasDMem[i].Theprogrammemoryhasthefollowinginput/outputports.
Enableport(1bit,input,denotedasDMem.E):enablethedevice,i.e.ifitis1,thenthe
entryspecifiedbytheaddressportwillbereadoutorwritteninotherwisenothingis
readoutorwrittenin.
Writeenableport(1bit,input,denotedasDMem.WE):enablethewrite,i.e.ifitis1,
thentheentryspecifiedbytheaddressportwillbewrittenwiththevaluespecifiedby
thedatainputportandthedataoutputportissuppliedwiththesamevalueotherwise,
theentryspecifiedbytheaddressportwillbereadoutondataoutputport,andvalue
ondatainputportisignored.
Addressport(4bit,input,denotedasDMem.Addr):specifywhichdataentryisread
out,connectedtoIR[3:0].
Datainputport(8bit,input,denotedasDMem.DI):thevaluethatiswrittenin,
connectedtoALU.Out.
Dataoutputport(8bit,output,denotedasDMem.DO):thedataentrythatisreadout,
connectedtoMUX2.In1.
Forexample,iftheaddresspointissuppliedwith80000_0011,datainputportissupplied
with80000_0000,enableissetto1,andwriteenableissetto1,thefourthentryofthedata
memoryiswrittenwithvalue0andthedataoutputportshows80000_0000.
Asanotherexample,iftheaddresspointissuppliedwith80000_0011,datainputportis
suppliedwith80000_0000,enableissetto1,whilewriteenableissetto0,thefourthentryof
thedatamemoryisreadoutondataoutputport.
Notethatwriteonlytakeseffectonclockrisingedge,whilereadhappensallthetime,similar
toprogrammemory.
PC adder
PCadderisusedtoaddPCby1,i.e.movetothenextinstruction.Thiscomponentispure
combinational.Ithasthefollowingport.
Adderinputport(8bit,input,denotedasAdder.In):connectedtoPC.
Adderoutputport(8bit,output,denotedasAdder.Out):connectedtoMUX1.In2.
MUX1
MUX1isusedtochoosethesourceforupdatingPC.Ifthecurrentinstructionisnotabranch
oritisabranchbutthebranchisnottaken,PCisincrementedby1otherwisePCissetto
thejumpingtarget,i.e.IR[7:0].Ithasthefollowingport.
MUX1input1port(8bit,input,denotedasMUX1.In1):connectedtoIR[7:0].
MUX1input2port(8bit,input,denotedasMUX1.In2):connectedtoAdder.Out.
MUX1selectionport(1bit,input,denotedasMUX1.Sel):connectedtocontrollogic.
MUX1outputport(8bit,output,denotedasMUX1.Out):connectedtoPC.
ALU
ALUisusedtodotheactualcomputationforthecurrentinstruction.Thiscomponentispure
combinational.Ithasthefollowingport.ThemodeofALUislistedinthefollowingtable.
ALUoperand1port(8bit,input,denotedasALU.Operand1):connectedtoAcc.
ALUoperand1port(8bit,input,denotedasALU.Operand2):connectedtoMUX2.Out.
ALUenableport(1bit,input,denotedasALU.E):connectedtocontrollogic.
ALUmodeport(4bit,input,denotedasALU.Mode):connectedtocontrollogic.
Currentflagsport(4bit,input,denotedasALU.CFlags):connectedtoSR.
ALUoutputport(8bit,output,denotedasALU.Out):connectedtoDMem.DI.
ALUflagsport(4bit,output,denotedasALU.Flags):theZ(zero),C(carry),S(sign),
O(overflow)bits,fromMSBtoLSB,connectedtostatusregister.
mode(binary)
mode(hex)
function
comments(instructions)
0000
Out=Operand1+Operand2
0001
Out=Operand1Operand2
0010
Out=Operand1
forMOVAM
0011
Out=Operand2
forMOVMAandMOVIA
0100
Out=Operand1ANDOperand2
0101
Out=Operand1OROperand2
0110
Out=Operand1XOROperand2
0111
Out=Operand2Operand1
1000
Out=Operand2+1
1001
Out=Operand21
1010
Out=(Operand2<<Operand1[2:0])
|(Operand2>>8Operand1[2:0])
forROTATEL
1011
Out=(Operand2>>Operand1[2:0])
|(Operand2<<8Operand1[2:0])
forROTATER
1100
Out=Operand2<<Operand1[2:0]
logicalshiftleft
1101
Out=Operand2>>Operand1[2:0]
logicalshiftright
1110
Out=Operand2>>>Operand1[2:0]
arithmeticshiftright
1111
Out=0Operand2
2scomplement
MUX2
MUX1isusedtochoosethesourceforoperand2ofALU.IfthecurrentinstructionisMtype,
operand2ofALUcomesfromdatamemoryifthecurrentinstructionisItype,operand2of
ALUcomesfromtheinstruction,i.e.IR[7:0].Ithasthefollowingport.
MUX2input1port(8bit,input,denotedasMUX2.In1):connectedtoIR[7:0].
MUX2input2port(8bit,input,denotedasMUX2.In2):connectedtoDR.
MUX2selectionport(1bit,input,denotedasMUX2.Sel):connectedtocontrollogic.
MUX2outputport(8bit,output,denotedasMUX2.Out):connectedtoALU.Operand2.
Instruction Set
Eachinstructionis12bits.Thereare3typesofinstructionsbyencoding,shownasfollowing:
1. Mtype:oneoperandisaccumulator(sometimesignored)andtheotheroperandis
fromdatamemorytheresultcanbestoredintoaccumulatororthedatamemoryentry
(sameentryasthesecondoperand).
2. Itype:oneoperandisaccumulatorandtheotheroperandisimmediatenumber
encodedininstructiontheresultisstoredintoaccumulator.
3. Stype:specialinstruction,nooperandrequired.(e.g.NOP)
Theinstructionencodingspaceisshowninthefollowingtable.
codespace
(binary)
code
spac
e
(hex)
instructions
#of
ins
comments
0000_0000_0000
0000_1111_1111
000
0FF
specialinstructions(Stype)
256
CurrentlyonlyNOP
used,255freeslots
0001_0000_0000
0001_1111_1111
100
1FF
unconditionaljump(Itype)
GOTO
0010_0000_0000
0011_1111_1111
200
3FF
ALUinstructions(Mtype)
32
16instructions,2
destinationchoiceseach
0100_0000_0000
0111_1111_1111
400
7FF
conditionaljump(Itype)
JZ,JC,JS,JC
1000_0000_0000
1111_1111_1111
800
FFF
ALUinstructions(Itype)
Currently7used,1free
slot
Theseinstructionscanbegroupedinto4categorybyfunction.
1. ALUinstruction:usingALUtocomputeresult
2. Unconditionalbranch:theGOTOinstruction
3. Conditionalbranch:theJZ,JC,JS,JOinstruction
4. Specialinstruction:theNOP.
M type instructions
ThegeneralformatofMtypeinstructionisshownasfollowing.
ThefollowingtablecontainsthedetailedinformationofeachMtypeinstruction.Notethat
aaaaencodesthe4bitaddressofdatamemory,andthedbitmeansdestinationofthe
result,i.e.ifd=1,resultiswrittentoAcc,otherwisetheresultiswrittentothesamememory
locationastheoperand.
NotethatallMtypeinstructionsareALUinstructions.
instruction
mnemonics
function
encoding
(binary)
status
affected
example
(encoding)
(assembly)
(meaning)
ADD
addamemoryentrywith
accumulator
001d_0000_aaaa
Z,C,S,O
0011_0000_0001
ADDAcc,Acc,DMem[1]
(Acc=Acc+DMem[1])
SUBAM
subtractaccumulatorbya
memoryentry
001d_0001_aaaa
Z,C,S,O
0011_0001_0000
SUBAMAcc,Acc,DMem[0]
(Acc=AccDMem[0])
MOVAM
movethevalueofaccumulator
toamemoryentry
0010_0010_aaaa
none
0010_0010_0000
MOVAMDMem[0],Acc
(Acc=DMem[0])
MOVMA
movethevalueofamemory
entrytoaccumulator
0011_0011_aaaa
none
0011_0011_0000
MOVMAAcc,DMem[0]
(DMem[0]=Acc)
AND
bitwiseANDamemoryentry
withaccumulator
001d_0100_aaaa
0010_0100_0000
ANDDMem[0],Acc,DMem[0]
(DMem[0]=DMem[0]ANDAcc)
OR
bitwiseORamemoryentrywith
accumulator
001d_0101_aaaa
0010_0101_0000
ORDMem[0],Acc,DMem[0]
(DMem[0]=DMem[0]ORAcc)
XOR
bitwiseXORamemoryentry
withaccumulator
001d_0110_aaaa
0010_0110_0000
XORDMem[0],Acc,DMem[0]
(DMem[0]=DMem[0]XORAcc)
SUBMA
subtractamemoryentryby
accumulator
001d_0111_aaaa
Z,C,S,O
0010_0001_0000
SUBAMDMem[0],DMem[0],
Acc
(DMem[0]=DMem[0]Acc)
INC
incrementamemoryentry
0010_1000_aaaa
Z,C,S,O
0011_1000_0000
INCDMem[0]
(DMem[0]=DMem[0]+1)
DEC
decrementamemoryentry
0010_1001_aaaa
Z,C,S,O
0011_1001_0000
DECDMem[0]
(DMem[0]=DMem[0]1)
ROTATEL
circulativeshiftleftamemory
entry,bythenumberofbits
specifiedbyaccumulator
0010_1010_aaaa
none
0010_1010_0000
ROTATELDMem[0]
(seecommentsbelow)
ROTATER
circulativeshiftleftamemory
entry,bythenumberofbits
specifiedbyaccumulator
0010_1011_aaaa
none
0010_1011_0000
ROTATERDMem[0]
(seecommentsbelow)
SLL
shiftamemoryentryleft,bythe
numberofbitsspecifiedby
accumulator
0010_1100_aaaa
Z,C
0010_1100_0000
SLLDMem[0]
(seecommentsbelow)
SRL
shiftamemoryentryright,
logical(fill0),bythenumberof
0010_1101_aaaa
Z,C
0010_1101_0000
SRLDMem[0]
bitsspecifiedbyaccumulator
(seecommentsbelow)
SRA
shiftamemoryentryright,
arithmetic(filloriginalMSB),by
thenumberofbitsspecifiedby
accumulator
0010_1110_aaaa
Z,C,S
0010_1110_0000
SRADMem[0]
(seecommentsbelow)
COMP
take2scomplementofa
memoryentry,i.e.0subtracted
bythememoryentry
0010_1111_aaaa
Z,C,S,O
0010_1111_0000
COMPDMem[0]
(DMem[0]=DMem[0])
Comments:
1. Forcirculativeshift,onlytheoperandfrommemoryentryisrotated,i.e.flagsarenot
involved.Forexample,if8b1000_0000isshiftedleftcirculativefor1bit,itbecomes
8b0000_0001,andnoflagisaffected.
2. Forlogicalshiftinstructions,0isalwaysfilledin,andCflagissettothelastbitthatis
shiftedout.Forexample,if8b1000_0000isshiftedleftlogicallyfor1bit,itbecomes
8b0000_0000,andC=1.Anotherexample,if8b0000_0100isshiftedrightlogically
for3bit,itbecomes8b0000_0000,andC=1.Ifnobitisshiftedout,ZflagandCflag
arenotaffected.
3. Forarithmeticshiftrightinstructions,theMSBisfilledin,andCflagissettothelastbit
thatisshiftedout.Forexample,if8b1000_0001isshiftedrightarithmeticallyfor1bit,
itbecomes8b1100_0000,andC=1.Anotherexample,if8b0000_0100isshifted
rightarithmeticallyfor3bit,itbecomes8b0000_0000,andC=1.Ifnobitisshifted
out,ZflagandCflagarenotaffected.
I type instructions
ThegeneralformatofMtypeinstructionisshownasfollowing.
ThefollowingtablecontainsthedetailedinformationofeachMtypeinstruction.
NotethatItypeinstructionscontainsunconditionalbranch,conditionalbranch,andALU
instructions.
instruction
mnemonics
function
encoding
status
affected
example
(encoding)
(assembly)
(meaning)
GOTO
unconditionalbranch
0001_xxxx_xxxx
none
0001_0000_0111
GOTO7
(gotothe8thinstruction)
JZ
jumptotheinstructionindexed
bytheimmediatenumber,ifZ
flagis1
0100_xxxx_xxxx
none
0100_0000_0111
JZ7
(gotothe8thinstructionifSR[3]==
1)
JC
jumptotheinstructionindexed
bytheimmediatenumber,ifC
flagis1
0101_xxxx_xxxx
none
0101_0000_0111
JC7
(gotothe8thinstructionifSR[2]==
1)
JS
jumptotheinstructionindexed
bytheimmediatenumber,ifS
flagis1
0110_xxxx_xxxx
none
0110_0000_0111
JS7
(gotothe8thinstructionifSR[1]==
1)
JO
jumptotheinstructionindexed
bytheimmediatenumber,ifO
flagis1
0111_xxxx_xxxx
none
0111_0000_0111
JO7
(gotothe8thinstructionifSR[0]==
1)
ADDI
addaccumulatorwith
immediatenumber
1000_xxxx_xxxx
Z,C,S,O
1000_0000_1000
ADDIAcc,Acc,8
(Acc=Acc+8)
SUBAI
subtractaccumulatorby
immediatenumber
1001_xxxx_xxxx
Z,C,S,O
1001_0000_1000
SUBAIAcc,Acc,8
(Acc=Acc8)
RSV
(reserved,donothing)(actually
itmovethevalueof
accumulatortoaccumulator)
1010_xxxx_xxxx
none
MOVIA
moveimmediatenumberto
accumulator
1011_xxxx_xxxx
none
1011_0000_0000
MOVIAAcc,0
(Acc=0)
ANDI
bitwiseANDaccumulatorwith
immediatenumber
1100_xxxx_xxxx
1100_0000_1111
ANDIAcc,Acc,0x0F
(Acc=AccAND0x0F)
ORI
bitwiseORaccumulatorwith
immediatenumber
1101_xxxx_xxxx
1101_1111_0000
ORIAcc,Acc,0xF0
(Acc=AccOR0xF0)
XORI
bitwiseXORaccumulatorwith
immediatenumber
1110_xxxx_xxxx
1110_0000_1111
XORIAcc,Acc,0x0F
(Acc=AccXOR0x0F)
SUBIA
subtractaccumulatorby
immediatenumber
1111_xxxx_xxxx
Z,C,S,O
1111_0000_1000
SUBIAAcc,8,Acc
(Acc=8Acc)
S type instructions
ThegeneralformatofStypeinstructionisshownasfollowing.
ThereisonlyoneStypeinstruction,i.e.theNOPinstruction.
instruction
mnemonics
NOP
function
nooperation
encoding
0000_0000_0000
status
affected
none
example
NOP
Control Signal
Controlsignalisderivedfromthecurrentstateandcurrentinstruction.Thecontrollogic
componentispurelycombinational.Thereareintotal12controlsignals,listedasfollowing.
PC.E:enableportofprogramcounter(PC)
Acc.E:enableportofaccumulator(Acc)
SR.E:enableportofstatusregister(SR)
IR.E:enableportofinstructionregister(IR)
DR.E:enableportofdataregister(DR)
PMem.E:enableportofprogrammemory(PMem)
DMem.E:enableportofdatamemory(DMem)
DMem.WE:writeenableportofdatamemory(DMem)
ALU.E:enableportofALU
ALU.Mode:modeselectionportofALU
MUX1.Sel:selectionportofMUX1
MUX2.Sel:selectionportofMUX2
Thefollowingtabledocumentsthedetailofhowthesecontrolsignalsaregenerated.
importantsignalsaremarkedinred.
Ins
Stage
PC
.E
Acc.
E
SR.
E
IR.
E
DR.
E
PMem
.E
DMem
.E
DMem
.WE
ALU.
E
ALU.
Mode
MUX
1.Sel
MUX
2.Sel
NOP
(0000)
FETCH
DECODE
EXECUTE
FETCH
DECODE
EXECUTE
FETCH
DECODE
EXECUTE
IR[8]
IR[8]
IR[8]
IR[7 : 4]
FETCH
DECODE
EXECUTE
SR*
FETCH
DECODE
EXECUTE
IR[10 : 8]
GOTO
(0001)
ALU
MType
(001x)
JZ,JC,
JS,JO
(01xx)
ALU
IType
(1xxx)
Comments:
1. NotethatinEXECUTEstateofconditionalbranchinstructions,thevalueofMUX1.Sel
isactuallySR[IR[9:8]]
2. NotethatinEXECUTEstageofALUItypeinstruction,thevalueofALU.Modeis
actually{0,IR[10:8]}.Inthetableabove0extensionisassumed.
3. BecarefulthatPMem.LEisnotshowninthistable.IftheprocessorisnotinLOAD
state,PMem.LEisalwayssetto0.
Thetypeandcategoryofinstructioncanbeidentifiedbythefirst4bitsoftheinstruction,i.e
IR[11:8],asdenotedinthefirstcolumnoftheabovetable.
Besides,whenloadingtheprogram,thecontrolsignalisgeneratedasbelow.
State
PMem
.LE
PC.
E
Acc.
E
SR.
E
IR.
E
DR.
E
PMem
.E
DMem
.E
DMem
.WE
ALU.
E
ALU.
Mode
MUX
1.Se
l
MUX
2.Sel
LOAD
IftheprocessorisinLOADstate,PMem.LEisalwayssetto1.
instruction
(binary)
instruction
(assembly)
instruction
(meaning)
0000_0000_0000
NOP
(nooperation)
1011_0000_0001
MOVIAAcc,1
Acc=1
0010_0010_0000
MOVAMDMem[0],Acc
DMem[0]=Acc=1
1011_0000_0000
MOVIAAcc,0
Acc=0
0011_0011_0000
MOVMAAcc,DMem[0]
Acc=DMem[0]=1
0001_0000_0101
GOTO5
(jumptoitself,i.e.infiniteloop)
instruction
(binary)
instruction
(assembly)
instruction
(meaning)
0000_0000_0000
NOP
(nooperation)
1011_0000_0001
MOVIAAcc,1
Acc=1
0010_0010_0000
MOVAMDMem[0],Acc
DMem[0]=Acc=1
0011_0000_0000
ADDAcc,Acc,DMem[0]
Acc=Acc+DMem[0]=1+1=2
0010_0000_0000
ADDDMem[0],Acc,DMem[0]
DMem[0] =Acc+DMem[0]=1+2=3
0011_0001_0000
SUBAMAcc,Acc,DMem[0]
Acc=AccDMem[0]=23=1
0010_0001_0000
SUBAMDMem[0],Acc,DMem[0]
DMem[0]=AccDMem[0]=(1)3=4
0011_0111_0000
SUBMAAcc,DMem[0],Acc
Acc=DMem[0]Acc=(4)(1)=3
0010_0111_0000
SUBMADMem[0],DMem[0],Acc
DMem[0]=DMem[0]Acc=(4)(3)=1
0001_0000_1001
GOTO9
(jumptoitself,infiniteloop)
instruction
(binary)
instruction
(assembly)
instruction
(meaning)
0000_0000_0000
NOP
(nooperation)
1011_0000_0101
MOVIAAcc,0x05
Acc=0x05
0010_0010_0000
MOVAMDMem[0],Acc
DMem[0]=Acc=0x05
0010_0010_0001
MOVAMDMem[1],Acc
DMem[1]=Acc=0x05
0010_0010_0010
MOVAMDMem[2],Acc
DMem[2]=Acc=0x05
1011_0000_0011
MOVIAAcc,0x03
Acc=0x03
0010_0100_0000
ADDDMem[0],Acc,DMem[0]
DMem[0]=AccANDDMem[0]=0x03AND0x05=0x01
0010_0101_0001
ORDMem[1],Acc,DMem[1]
DMem[1]=AccORDMem[1]=0x03OR0x05=0x07
0010_0110_0010
XORDMem[2],Acc,DMem[2]
DMem[2]=AccXORDMem[2]=0x03XOR0x05=0x06
0001_0000_1001
GOTO9
(jumptoitself,infiniteloop)
instruction
(binary)
instruction
(assembly)
instruction
(meaning)
0000_0000_0000
NOP
(nooperation)
1011_0000_0001
MOVIAAcc,1
Acc=1
1010_0000_0000
RSV
(reservedinstruction,donothing)
1000_0000_0111
ADDIAcc,Acc,7
Acc=Acc+7=1+7=8
1001_0000_0110
SUBAIAcc,Acc,6
Acc=Acc6=86=2
1111_0000_0111
SUBIAAcc,7,Acc
Acc=7Acc=72=5
1100_0000_0011
ANDIAcc,Acc,0x03
Acc=AccAND0x03=0x05AND0x03=0x01
1101_0000_0101
ORIAcc,Acc,0x05
Acc=AccOR0x05=0x01OR0x05=0x05
1110_0000_0011
XORAcc,Acc,0x03
Acc=AccXOR0x03=0x05XOR0x03=0x06
0001_0000_1001
GOTO9
(jumptoitself,infiniteloop)