Professional Documents
Culture Documents
Steering Logic
Contemporary Logic Design
Randy H. Katz
University of California, Berkeley
June 1993
No. 4-1
Inputs
Dense array of
AND gates
Product
terms
Dense array of
OR gates
Outputs
No. 4-2
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Input Side:
Personality Matrix
Product
term
AB
BC
AC
BC
A
Inputs
A B C
1 1 - 0 1
1 - 0
- 0 0
1 - -
Outputs
F0 F 1 F 2 F 3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1
1 = asserted in term
0 = negated in term
- = does not participate
Reuse
of
terms
Output Side:
No. 4-3
Example Continued
No. 4-4
Example Continued
No. 4-5
Short-hand notation
so we don't have to
draw all the wires!
No. 4-6
Design Example
Multiple functions of A, B, C
ABC
A
F1 = A B C
B
C
A
F2 = A + B + C
B
C
F3 = A B C
ABC
ABC
ABC
F4 = A + B + C
ABC
ABC
F5 = A xor B xor C
ABC
ABC
F6 = A xnor B xnor C
F1
F2
F3
F4 F5
F6
No. 4-7
No. 4-8
AB
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
AB
00
01
11
10
00
01
CD
00
01
11
10
00
01
11
10
CD
D
11
10
D
C
K-map for W
K-map for X
AB
AB
00
01
11
10
00
01
11
10
CD
00
01
11
10
00
01
11
10
CD
W=A+BD+BC
D
C
X = B C
Y=B+C
K-map for Y
K-map for Z
Programmed PAL:
0
0
0
0
0
ABCD
\A
B
D
B
C
\A
\B
\C
D
W
B
C
D
A
D
B
C
22
1
X
3
4 4
\D
\B
C
\D
\C
\B
AB
AB
00
01
11
10
00
01
11
10
CD
01
11
10
00
01
11
ABCD
10
AC
D
C
ABCD
00
CD
ABCD
ABCD
D
K-map for EQ
K-map for NE
AB
01
11
10
00
01
BD
AB
00
CD
AC
BD
00
01
11
10
00
01
CD
ABD
BCD
D
11
ABC
11
10
BCD
C
10
K-map for LT
K-map for GT
EQ NE LT
GT
No. 4-12
Non-Gate Logic
Introduction
AND-OR-Invert
PAL/PLA
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
S
I
0
S
1
S
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
Z0
I
S
Z1
S
No. 4-14
Z1
S
"0"
S
No. 4-15
Multiplexers/Selectors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
Sum
Ss
DEMUX
S0
S1
No. 4-16
General Concept
2
used to connect 2
Z = A' I0 + A I1
A
0
1
Z
I0
I1
Functional form
Logical form
I1
0
0
0
0
1
1
1
1
I0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
I0
2:1
mux
I1
Z = A' I 0 +
A I1
A
I0
I1
I2
I3
4:1
mux
I0
I1
I2
I3
8:1
mux
I4
I5
I6
I7
In general, Z =
A
n
2 -1
m I
k=0
k k
n
in minterm shorthand form for a 2 :1 Mux
No. 4-18
Alternative Implementations
A
I0
I1
I2
I3
Gate
GateLevel
Level
Implementation
Implementation
of
of4:1
4:1Mux
Mux
Transmission
TransmissionGate
Gate
Implementation
Implementationof
of
4:1
4:1Mux
Mux
twenty transistors
No. 4-19
0 4:1
1 mux
2
3 S1 S0
I4
I5
I6
I7
0 4:1
1 mux
2
3 S1 S0
B
8:1
mux
0 2:1
mux
1 S
I1
1 S
I2
I3
1 S
0
1
I4
I5
1 S
I6
I7
1 S
2
3 S0
S1
C
No. 4-20
n-1
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1
0
1
2
3
4
5
6
7
A
0
0
0
0
1
1
1
1
8:1
MUX
S2 S1 S0
A
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
0
1
0
0
0
1
1
C
C
0
1
C
C
0
0
1
2
3
4:1
MUX
S1
S0
"Lookup Table"
No. 4-21
Generalization
I1 I2
n-1 Mux
control variables
single Mux
data variable
In
0
1
F
0
0
0
1
1
0
1
1
In
In
Four possible
configurations
of the truth table rows
Can be expressed as
a function of In, 0, 1
No. 4-22
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
K-map
Choose A,B,C
as control variables
1
D
0
1
D
D
D
D
0
1
2
3
4
5
6
7
8:1
mux
S2
A
S1
B
S0
C
Multiplexer
Implementation
TTL
TTLpackage
packageefficient
efficient
May
Maybe
begate
gateinefficient
inefficient
No. 4-23
Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2 n outputs
- control inputs (called select S) represent Binary index of
output to which the input is connected
- data input usually called "enable" (G)
1:2 Decoder:
3:8 Decoder:
O0 = G S0 S1 S2
O0 = G S; O1 = G S
O1 = G S0 S1 S2
2:4 Decoder:
O2 = G S0 S1 S2
O0 = G S0 S1
O3 = G S0 S1 S2
O1 = G S0 S1
O4 = G S0 S1 S2
O2 = G S0 S1
O5 = G S0 S1 S2
O3 = G S0 S1
O6 = G S0 S1 S2
O7 = G S0 S1 S2
No. 4-24
Alternative Implementations
G
Output0
Select
/G
Select
Output0
Output1
Output1
/G
Select0
Output0
Output0
Output1
Output1
Output2
Output2
Output3
Output3
Select0
Select1
Select1
Select
G
Output
Output
0
Select
Select
Select
Select
"0"
Select
Output
1
Select
Select
Output
Select
"0"
Select
No. 4-26
Select
Output
"0"
"0"
S0 = 0, S1 = 0
Output
1
"0"
"0"
Output
"0"
"0"
Output
"0"
"0"
No. 4-27
3:8
dec
S2
A
S1
B
S0
2
3
4
5
6
7
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
No. 4-28
Decoder/Demultiplexer
Decoder as a Logic Building Block
Enb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4:16
dec
S3 S2 S1 S0
A
B C
A BCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
F1
F2
ABCD
ABCD
ABCD
ABCD
F3
No. 4-29
Multiplexers/Decoders
Alternative Implementations of 32:1 Mux
I7
I6
I5
I4
I3
I2
I1
I0
C
D
E
EN
I31 7 151
EN 1 6
5
1
Y5
I23 7 151
41 4
6
3
W 6
EN 1 5 52 2
1 4
3 1Y 5
I15 7 151
4
40
1 6 51 3
6
W
EN 1 5
22
3
3 1 Y 19
1 4
5C
7 151
4
B
4 0W 1 6A
6 51 3
22
5
9C 0
1
3
1
5B
4
4 0Y 1
13
1 6A
W0
2
9
1
1 1 C
B
0 1A
S2 0
1
S1
S0
A
B
1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
1
5
Multiplexer Only
153
YA 7
B3
B2
YB 9
B1
B0
GBS1SO
2 14
A B
F(A, B, C, D, E)
1 1G 1Y3
1Y2
3 139
1B
2 1A 1Y1
1Y0
15 2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0
7
6
5
4
9
10
11
12
7 EN 146
5
154
I31 7 151
13
6
7 EN
22
I5 145
3
154
I23 7 I4151
1 5
40 Y
3
7 EN 146 I3 1
W 6
I5 5 I2 2 2
9
154 I1 3 1 Y 10
5C
I15 7 I4151
B
4
1
I3
3
I0
0
7 EN 146
W 116A
I5 5 I2 2 2 C 9 C
S2
154 I1 3 1Y 10
5 S1
I7 7 I4 151
D 116B
I6 6 I3 1 3 I0 4 0W
A
I5 5 I2 2 2 C 9 C
S2E S0
5B
I4 4 I1 3 1 Y 10
D 11S1
I3 3 I0 4 0 W
6A
I2 2 C 9 C
S2E S0
I1 1 10B
S1
I0 0 D 11A
C S2E S0
D S1
E S0
F(A, B, C, D, E)
Multiplexer + Decoder
No. 4-30
Multiplexers/Decoders
5:32 Decoder
\EN
S4
S3
1G 1Y3
139 1Y2
1B 1Y1
1A 1Y0
2G 2Y3
2Y2
2B 2Y1
2A 2Y0
\EN
S2
S1
S0
\Y31
5:32
Decoder
Subsystem
.
.
.
S2
S1
S0
\Y0
S4 S3 S2 S1 S0
S2
S1
S0
S2
S1
S0
G1
G2A
G2B
Y7
Y6
Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A
\Y31
\Y30
\Y29
\Y28
\Y27
\Y26
\Y25
\Y24
Y7
G1
G2A Y6
G2B Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A
\Y23
\Y22
\Y21
\Y20
\Y19
\Y18
\Y17
\Y16
Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
C
Y2
Y1
B
Y0
A
\Y15
\Y14
\Y13
\Y12
\Y11
\Y10
\Y9
\Y8
G1 Y7
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A
\Y7
\Y6
\Y5
\Y4
\Y3
\Y2
\Y1
\Y0
No. 4-31
A OE F
X 0 Z
0 1 0
1 1 1
Non-inverting buffer's
timing waveform
A
OE
F
"Z"
"Z"
No. 4-32
OE
Input
OE
SelectInput
No. 4-33
OE
Input
OE
SelectInput
F
I
OE
0
No. 4-34
\EN
S1
S0
1G 1Y3
1Y2
3 139 1Y1
2 1B
1A 1Y0
15
2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0
7
6
5
4
9
10
11
12
D3
D2
D1
D0
No. 4-35
OC NAND gates
Wired AND:
If A and B are "1", output is actively pulled low
if C and D are "1", output is actively pulled low
if one gate is low, the other high, then low wins
if both gates are "1", the output floats, pulled
high by resistor
Hence, the two NAND functions are AND'd
together!
No. 4-36
\EN 1
Y3
139 Y2
Y1
S1 3 B
Y0
S0 2 A
G
+5V
7
6
5
4
\I3
OR
\I2
OR
\I1
OR
\I0
OR
No. 4-37
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
Dec
n-1
Bit Lines
Address
Internal Organization
No. 4-38
Read-Only Memories
Example: Combination Logic Implementation
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1
Address
ROM
8 w ords by
4 bits
A B C
address
F0
F1
F2
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F0
0
1
0
0
1
1
0
0
F1
0
1
1
0
0
0
0
1
F2
1
1
0
0
1
0
0
0
F3
0
0
0
1
1
0
1
0
Word Contents
F3
outputs
No. 4-39
Read-Only Memories
Memory array
Not
Notunlike
unlikeaaPLA
PLA
structure
structurewith
withaa
fully
fullydecoded
decoded
AND
ANDarray!
array!
Decoder
2n word
lines
n address
lines
2n words by
m bits
m output
lines
Read-Only Memories
2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10 O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE
A13
/OE
A12:A0
D15:D8
D7:D0
+
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE
2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE
16K x 16
Subsystem
No. 4-41
No. 4-42
No. 4-43
+ 5%
Spec
Spec
Spec
- 5%
- 5%
- 10%
ROD
Too
Long
ROD
Within
Spec
ROD
Too
Short
No. 4-44
Too
Long
Too
Short
Within
Spec
Spectification
- 5%
Specification
+ 5%
No. 4-45
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Function
X
X
X
X
too short
X
in spec
too long
No. 4-46
7 outputs C0 C6
C0 C1 C2 C3 C4 C5 C6
C0
C5
C6
C4
C3
C1
BCD-to-7-segment
control signal
decoder
C2
C C C C C C C
0 1 2 3 4 5 6
Block Diagram
No. 4-47
No. 4-48
AB
AB
00
01
11
10
00
01
11
10
CD
01
11
10
00
01
11
10
10
00
01
11
10
D
C
K-map for C1
K-map for C2
AB
00
01
11
10
00
01
11
01
11
10
00
01
11
01
11
10
00
01
11
00
01
11
10
00
01
11
10
CD
D
C
C
10
AB
00
CD
C
1
AB
00
CD
11
K-map for C0
AB
10
01
D
C
CD
00
CD
D
C
AB
00
CD
10
K-map for C3
K-map for C4
K-map for C5
K-map for C6
C0 = A + B D + C + B' D'
C1 = A + C' D' + C D + B'
C2 = A + B + C' + D
No. 4-49
First
fuse
numbers
12
16
20
24
28
0
32
64
96
128
160
192
224
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
17
768
800
832
864
896
928
960
992
16
1024
1056
1088
1120
1152
1184
1216
1248
15
1280
1312
1344
1376
1408
1440
1472
1504
14
1536
1568
1600
1632
1664
1696
1728
1760
13
16H8PAL
Can Implement
the function
8
1792
1824
1856
1888
1920
1952
1984
2016
12
11
Note: Fuse number = first fuse number + increment
No. 4-50
01 2 3
10
12
14
16
18
20
24
27
First
fuse
numbers
14H8PAL
Cannot Implement
the function
23
0
28
56
84
22
1
112
140
21
168
196
20
224
252
19
280
308
18
336
364
17
392
420
16
448
476
504
532
15
10
14
11
13
No. 4-51
No. 4-52
52 literals
33 gates
Ineffective use of don't cares
No. 4-53
No. 4-54
4 TTL packages:
4 x 2-input NAND
4 x 2-input NOR
2 x 2-input XOR
8:1 MUX
A
B
A
B
+
5
V
DD D D D D D D S
01 2 3 4 5 6 7 0
S
E
1
N
Q
S
O
2
C2
C1
C0
F
No. 4-55
AB
C 0=0
01
11
10
1
1
11
10
1
1
C1 C 2
00
00 1
AB
C 0=1
01
01
11
01
single package
11
10
No. 4-56
Device A - 1st
Device B - 2nd
Device C - 3rd
Device D - 4th
Device B
RB
OB
SB
Device C
RC
OC
SC
RD
RA
Device A
OD
OA
Device D
Priority Multiplexer
SD
SA
OUTPUT
The Priority Mux connects a device output (OA, OB, OC, OD) to the
output line (OUTPUT) based on priorities. Each device has a request
line (RA, RB, RC, RD) that is asserted when the system output line is
requested by that device. The Mux must return a signal (SA, SB, SC,
SD) to each device indicating whether the request was accepted.
These signals should be asserted only if a request has been received
from the device and the device output has been connected to the
system output.
No. 4-57
7
6
Inputs
7-LPE
4
3
MSB
2
1
LSB
No. 4-58
Chapter Review