LIST OF VLSI PROJECTS

a) Microcontroller and microprocessor based projects

IEEE PROJECTS
1. Architecture-Level Thermal Characterization for Multicore
Microprocessors(IEEE OCT 2009)
2. Predictive-Flow-Queue-Based Energy Optimization for Gigabit Ethernet
Controllers (IEEE AUG 2009)
3. Synthesis Algorithm for Application-Specific Homogeneous Processor Networks
(IEEE SEP 2009)
4. Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers
for Reed–Solomon Codec (IEEE JUNE 2009)
5. Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus (IEEE AUG
2009)
6. Static Minimization of Total Energy Consumption in Memory Subsystem for
Scratchpad-Based Systems-on-Chips (IEEE FEB 2009)
7. Energy- efficient subthreshold processor design (IEEE AUG 2009)
NON IEEE PROJECTS
8. A Controller Area Network protocol controller
9. Wishbone controller
10. I2c (Inter Intergrated circuits)
11. JTAG tap controller
12. VGA/LCD Controller
13. PCI-Express core design
14. UART Core design
15. ADC & DAC Interface
16. USB(universal serial bus)
17. Neural Network Based Branch Prediction
18. Support Vector Machine Based Dynamic Branch Predictor

For further details contact

E-Mail: projects.2009.finalyear@gmail.com

Contact No: 9788886488, 9789807638, 9962544925

 b) Multimedia and Signal Processors based projects
IEEE PROJECTS
1. A VLSI – inspired image reconstruction algorithm for continous-wave diffuse
optical tomography system (IEEE MAY 2009)
2. Signal Assignment to Hierarchical Memory Organizations for Embedded
Multidimensional Signal Processing Systems (IEEE SEP 2009)
3. Realizing a Sub-Linear Time String-Matching Algorithm With a Hardware
Accelerator Using Bloom Filters (IEEE AUG 2009)
4. Throughput-Oriented NoC Topology Generation and Analysis for High
Performance SoCs (IEEE OCT 2009)
5. FleXilicon Architecture and its VLSI implementation (IEEE AUG 2009)
NON IEEE PROJECTS
6. Hilbert Transformer
7. FirGen/MultGen
8. Real Time Analysis of  Medical Data
9. Hough Transform for Circle Detection
10. Hardware Implementation of DFT Processor
11. High –efficient soft-error –tolerant digital signal processing using fine –grain
subword-detection processing

c) Communications and security based projects

IEEE PROJECTS
1. Pruned bit-reversal interleaver (IEEE AUG 2009)
2. A Distributed, Adaptive Protocol For Handling Interference in Wireless
Communications (IEEE APRIL 2008)
3. Data Encryption And Decryption In Crpyography (IEEE AUG 2009)
4. Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic (IEEE
JULY 2009)
5. Switching controller for high capacity non blocking internet router (IEEE AUG
2009)

For further details contact

E-Mail: projects.2009.finalyear@gmail.com

Contact No: 9788886488, 9789807638, 9962544925

 6. Asyncronous protocol converter s for two phase delay- insensitive global
communication (IEEE JULY 2009)

7. Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff (IEEE
AUG 2009)

8. Low-Power, High-Speed Transceivers for Network-on-Chip Communication

(IEEE JAN 2009)
9. Decoding the Golden Code: a VLSI design (IEEE JAN 2009)
10. Custom Networks-on-Chip Architectures With Multicast Routing (IEEE MARCH
2009)
11. Fast Scaling in the Residue Number System (IEEE MARCH 2009 )
12. Fault Secure Encoder and Decoder for NanoMemory Applications (IEEE APRIL
2009)
13. Design and implementation of a field programmable CRC circuit architecture
(IEEE AUG 2009)
14. Introduction to the Special Section on Nanocircuits and Systems (IEEE APRIL
2009)
15. Flexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime
Fields (IEEE AUG 2009)
NON IEEE PROJECTS
16. Fast Ad Hoc On-Demand Distance Vector (AODV) Router
17. Design and Implementation of an Adaptive Self Learning Synchronizer
18. Implementation of an Asymmetric Latch
19. Direct Memory Access Supporting AXI Interface
20. Synchronizer Test Chip
21. Hamming EEC Unit
22. Inter-Clock Domain Interface
23. DMA for Packet Communication
24. Implementation of Register Exchange Viterbi Decoder
25. Implementation of a Parallel Packet Switch
For further details contact

E-Mail: projects.2009.finalyear@gmail.com

Contact No: 9788886488, 9789807638, 9962544925

 26. Efficient Layout Design of NOC Router
27. Hardware Implementation of Viterbi Decoder
28. Implementation of Parallel Turbo Decoder

d) Low power and FPGA based projects

1. A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-
Time (IEEE OCT 2009).
2. A Low-Power Field-Programmable Gate Array Routing Fabric (IEEE OCT
2009).
3. Low power programmable FPGA routing circuitry (IEEE AUG 2009)
4. The design of a micro power management system for applications using
photovoltic cells with the maximum output power control (IEEE AUG 2009)
5. Power reduction of asyncronous logic circuits using active detection (IEEE JULY
2009)
6. Floating –point FPGA : Architecture and modeling (IEEE JULY 2009)
7. A Low-Power Delay Buffer Using Gated Driver Tree (IEEE SEP 2009)
e) Arithmetic core based projects
IEEE PROJECTS

1. CGADL: An Architecture Description Language for Coarse-Grained

Reconfigurable Arrays (IEEE SEP 2009)
2. Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings
(IEEE JULY 2009)
3. Checksum-Based Probabilistic Transient-Error Compensation for Linear Digital
Systems (IEEE OCT 2009)
4. Multiplication Acceleration Through Twin Precision (IEEE SEPT 2009).

NON IEEE PROJECTS

5. CORDIC core
6. Cellular Automata PRNG
7. Discrete Cosine Transform core
For further details contact

E-Mail: projects.2009.finalyear@gmail.com

Contact No: 9788886488, 9789807638, 9962544925

 8. Floating point adder and multiplier
9. Single clock unsigned division algorithm
10. Sinusoidal Computator
f) Memory cores based projects
IEEE PROJECT
1. An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs (IEEE
SEP 2009)
NON IEEE PROJECTS
2. High Performance Dynamic Memory Controller
3. Asynchronous WISHBONE-compatible SDRAM controller

For further details contact

E-Mail: projects.2009.finalyear@gmail.com

Contact No: 9788886488, 9789807638, 9962544925