Some potential switching ideas are presented above.

The builder is in total control of the tuning range and must calibrate the L and C values
according to needs and the parts on hand. Output power will vary according to the L-C ratios and some designs include automatic signal
amplitude leveling and/or RF gain controls.

3. FET Matching

I find matching high IDSS FETs like the J310 to be a pain. I generally matched them for IDSS and occasionally for IDSS and VP. Observations
that when the IDSS of 2 or more FETs match, their pinch-off voltage (VP) also matches, led me to not measure VP. In addition, the variability of
VP measurements causes me distress. Click here for a tutorial if you don't understand the terms IDSS and VP.

Above The device I use to measure IDSS and VP. From Ken Kuhn's web site.
Conceptually IDSS and VP aren't difficult to understand measuring them is another story. With the above device, first IDSS is measured; the
final drain voltage potentiometer setting is left and then I measure VP. While measuring IDSS in high IDSS FETs, heating can occur and you
may actually see current start to drop as you increase the drain voltage (negative temperature coefficient). On J310 specification sheets, the
manufacturers state they pulse the current during measurement to prevent heating. While performing IDSS measurements, I am fearful of
destroying the FET I am trying to characterize! Measuring VP is also problematic.
I have tried 3 methods to quantify VP:

Adjust the 0 - 6 volt supply until I think the current goes to 0. Serial measurements 1 day apart can vary by a variation of as much as 0.5 volts;
it's quite subjective.
Adjust the 0 - 6 volt supply and measure the gate voltage that produces a drain current somewhere between 0.1 and 1 percent of IDSS and
declare that to be VP.
Adjust the 0 - 6 volt supply so the ammeter reads IDSS and multiply this voltage by - 2.0. Refer to Ken Kuhn's site for details. Although
reasonably accurate, the second order math is only a rough approximation the real math is impossible to do by hand as it involves fractional
exponents and these exponents and other factors vary as a function of the physical JFET geometry.

Above The breadboard of the device I use to measure IDSS and VP. There is no actual switch, I either ground the green wire to the copper
board, or tack solder it to the 0 - 6 volt potentiometer wiper. 10 megohm resistors plus the pot ground wire anchor each pot to the copper clad
board.
All 3 methods to quantify VP frustrate me. There must be a way to match J310s or other FETs without characterizing them. I frequently
collaborate with readers to problem solve and learn. A potential solution contributed by a supportive reader follows:

Above A bridge is used to match a pair of JFETS. It's often best to match devices in a circuit that closely resembles the one that you intend to
use them in. The differential output of each drain is measured by placing a DVM lead on each drain and recording the voltage. Generally, I stick a
FET in the Q2 slot and put FETs from my parts bin in the Q1 slot to match it. The results of 5 different FET pairs are tabled above. A match <=
50 mV is probably acceptable and in 1 case, I found a match of 3 mV! You can match 1 FET with many using this device.
Note the poor match when an MPF102 and a J310 were tested. 1% tolerance resistors are recommended for the bridge.

Above A set and forget precision bridge using trimmers to establish a perfect DC match on both halves. If you don't have 1% parts, the
trimmer resistors offer a solution. You can place a trimmer at either the drain or source end as shown and just use 5% resistors. Calibrate each
half of the bridge with your ohm meter. I cover bridges on this web page if you need more information on them.