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Published in IET Power Electronics
Received on 6th February 2014
Revised on 9th August 2014
Accepted on 15th August 2014
doi: 10.1049/iet-pel.2014.0099
ISSN 1755-4535
Abstract: The objective of this study is to present a voltage compensator based on a matrix converter without energy storage,
which can cope with common power quality problems presented in power distribution systems. The proposed scheme
acquires from the grid the necessary energy during the disturbance, which eliminates the drawbacks imposed by the use of a
dc-link and the need of energy storage components. A matrix converter study under unbalanced input voltage conditions is
exposed, as well as a detailed explanation of the proposed modied direct space vector modulation (MDSVM). It has been
veried that even when the supply voltage exhibits unbalanced conditions and harmonic distortion, the control strategy does
not exhibit difculties to synthesise the compensation voltages, provided the restrictions imposed by the formulation are
fullled. Numerical simulations and experimental results from a laboratory scale prototype are presented to validate the
performance of the compensator.
Introduction
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Fig. 1 Generation of the output line-to-line and input current reference vectors using SVM strategy
a Required states for tracking U out(ref ) within sector I
b Fixed vectors for current vector I in(ref ) tracking
Vin sin(vt )
va (t)
k V sin vt 2p + u
1
3
V p = vb (t) = 1 in
(1)
vc (t)
4p
+ u2
k2 Vin sin vt
3
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099
www.ietdl.org
where coefcients k1 and k2 specify the degree of unbalance
in two of the input voltage magnitudes. Likewise, by
adding the angles 1 and 2, it is possible to include angles
different from 2/3 among phases. Under such conditions,
the line-to-line input voltages become
x V sin
vt b
1
in
1
vab (t)
vca (t)
x V sin vt + b
in
(2)
U = 3 v2 (t) + v2 (t) + v (t) v (t)
inl
ab
bc
ab
bc
/U inl = tan
(3)
(4)
(5)
(6)
(7)
3vbc (t)
2vab (t) + vbc (t)
/U inl = /U inp +
p
6
I
II
U outl(ref ) = U outl mI + U outl mII
(14)
III
IV
U outl(ref ) = U outl mIII + U outl mIV
(15)
(10)
(11)
Ti
i = {I, II, III, IV }
Ts
(16)
Ts is the sample time and Ti is the time elapsed while the ith
state is on. From Fig. 1 and [3336] the following
expressions may be deducted
I
II
U outl(ref ) = U outl mI + U outl mII
2.2
U outl(ref )
Then,
U = 3 U
inl
inp
(8)
(9)
(13)
2
p j(p/6)
e
=
U outl(ref ) cos /U outl(ref )
3
3
(17)
III
IV
= U outl mIII + U outl mIV
2
p j(p/6)
e
=
U outl(ref ) cos /U outl(ref ) +
3
3
(18)
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voltages and the sector where U inp is located, despite
unbalanced conditions.
Rearranging (17) and (18) in terms of the input line-to-line
voltage vector
p
U outl(ref ) cos /U outl(ref )
3
4p
= U inl cos /U inl mI U inl cos /U inl
mII
3
(19)
p
U outl(ref ) cos /U outl(ref ) +
3
4p
mIV
= U inl cos /U inl mIII U inl cos /U inl
3
(20)
2.3
II
I in
mII
I in(ref ) = I in mI
IV
+ I in mIV
(21)
III
+ I in mIII
(22)
Solving the equations set (19), (20) and (23), (24) [32], the
duty cycles become
U
outl(ref
)
2
mI =
U inl
3
p
p
cos + /I in(ref )
cos /U outl(ref )
3
3
cos uin
2 U outl(ref )
mII =
U inl
3
p
p
cos /I in(ref )
cos /U outl(ref )
3
3
cos uin
Vout
mIV
U
outl(ref
)
2
=
U inl
3
p
p
cos /I in(ref )
cos /U outl(ref ) +
3
3
cos uin
(27)
(28)
p
p
p
p
, /U outl(ref ) , , , /I in(ref ) ,
6
6
6
6
(29)
Current tracking
I in(ref )
mIII
2 U outl(ref )
=
U inl
3
p
p
cos + /I in(ref )
cos /U outl(ref ) +
3
3
cos uin
1
Vin
3 2
(25)
(26)
If the sum of duty cycles is less than one, the use of zero states
is required. Substituting (25)(28) into (30) results [32],
3
U inl
U outl(ref )
2
cos /U
cos uin
cos
/I
outl(ref )
in(ref )
(31)
Considering
that for each sector it holds that
= 1 and cos /U outl(ref )
= 1, from (8),
cos /I in(ref )
max
max
the inputoutput voltage relationship q = (Vout /Vin ) can
be established (see (32))
in Appendix 1. From
where variables , l and j are specied
(32) it may be observed that U in is a time variant quantity
which depends on the unbalance degree. Besides, it can be
noted that the maximum voltage relationship is reached
when cosin = 1. Then, (see (33) at the bottom of the page).
Equation (33) implies that under unbalanced conditions on
input voltages, the reference output voltage vector is at the
most 0.866 times the minimum value of the input voltage
Park vector. For example, during balanced conditions the
maximum balanced output voltage vector that may be
generated, corresponds to 0.866 times the maximum circle
that can be inscribed inside the hexagon, Fig. 2a. On the
other hand, if a sag of 50% takes place on input phase b,
the input vector describes an ellipse, thus reducing the
available locus for the output voltage generation. In this
particular case, the maximum magnitude of the balanced
output voltage that can be generated is reduced by a factor
of 2/3, Fig. 2b. The latter also can be applied in the case of
harmonic distortion present on input voltages, where, as
long as the output voltage vector magnitude remains below
the 86.6% of the input voltage vector magnitude at any
time, compensation can be achieved.
lg
2
2
2
g + l + g + l + w 2gl sin 2vt +
cos uin
w
324
& The Institution of Engineering and Technology 2015
(30)
(32)
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Fig. 2 Comparison of the maximum balanced output voltages obtained under balanced and unbalanced conditions on input voltages
a Voltage vectors for balanced input voltage condition
b Voltage vectors for unbalanced condition (50% sag on phase-b)
mIII
(35)
U outl(ref )
p
(vbc (t) vab (t))
=
2 cos /U outl(ref ) +
U
3
inl
mIV
(36)
U outl(ref )
p
(vca (t) vbc (t))
=
2 cos /U outl(ref ) +
U
3
inl
(37)
Vout
1
Vin
3 2
Voltage controller
l
g
g + l + g2 + l2 + w2 2gl sin 2vt +
w
(33)
max
325
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MAX
3/2U
inl MIN
(39)
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3.2
Simulations
1
2p Lf Cf
(40)
(41)
10 F
2.2 mH
50
4.7 F
25 mH
100
120
213 mH
113.13 V
0.7835 A
The Park vectors U inl and U outl on the complex plane are
displayed in Fig. 5 and Fig. 6a displays the input voltages
in time domain. In this case, voltage imbalance is exhibited
on both sets of terminals in the matrix converter.
Nonetheless, as long as the vector U outl remains inside the
vector U inl loci, the control algorithm will be able to
synthesise the output-voltage. Figs. 6 and 7 depict voltage
and current waveforms during the voltage sag period. Note
that the RL load acts as a low-pass lter, reducing almost
all the current harmonic components. Likewise, the matrix
converter generates a set of unbalanced voltages to achieve
the compensation, which provokes a distortion in the
currents drawn by the converter and consequently the
system currents are distorted as well, Fig. 7. The total
harmonic distortion (THD) of output voltages and system
currents during the disturbance are exhibited in Fig. 8. The
control algorithm has accomplished to reduce the
imbalanced percent from 15.38% at the input voltages to
0.42%, value which fulls the NEMA criterion about
permitted imbalance percent of 1. Besides, each output
phase voltage presents an average THD lower than 3%
during the fault, which falls inside the guidelines
established in the IEEE-519 for general power systems of
medium voltage.
Once evidenced the capacity of the proposed topology to
operate in a satisfactory way under unbalanced conditions,
its behavior was veried under the presence of harmonic
components on the input voltage (results are omitted for the
sake of brevity) [32].
327
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3.3
Experimental results
Fig. 9 Experimental results: Supply and load voltages during unbalanced voltage sag test
a Pre-sag condition
b Sag condition (20 V/div, 5 ms/div)
c Pre-sag condition
d Sag condition (20 V/div, 10 ms/div)
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099
329
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Fig. 10 Experimental results: Supply voltages (top) and load currents (bottom) during the distorted voltage test
a Without compensation
b With compensation (20 V/div, 5 ms/div)
c Without compensation
d With compensation (0.5 A/div, 5 ms/div)
Conclusions
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DSP-based board eZdsp-TMS320F2812, along with a four
step commutation strategy.
The incorporation of matrix converter technology into
the conventional DVR conguration may result in a
cost-effective and multi-functional solution. Simulated and
experimental results presented show the feasibility of the
proposed topology. This analysis may be useful to study the
use of the matrix converter in future applications.
Acknowledgment
References
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IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099
Appendix 1
p
1 + k12 2k1 sin u1
6
p
x2 = k12 + k22 2k1 k2 sin u1 u2
6
5p
x3 = 1 + k22 2k2 sin u2
6
x1 =
k
cos
u
+
(5
p
/6)
1
2
b1 = tan1
1 k1 sin u1 (p/6)
1 k1 cos u2 + (5p/6) k2 cos u2 + (p/6)
b2 = tan
k1 sin u1 (p/6) k2 sin u2 (5p/6)
k2 cos u2 + (p/6)
1
b3 = tan
k2 sin u2 (5p/6) 1
331
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2p
g = x1 cos b1 + x2 k1 cos b2 cos u1
3
2p
+ x3 k2 cos b3 cos u2 +
3
2p
2p
+ x3 k2 sin b3 sin u2 +
l = x2 k1 sin b2 sin u1
3
3
2p
w = x1 sin b1 + x2 k1 sin b2 + u1
3
2p
+ x3 k2 sin b3 + u2 +
3
Appendix 2
1
vds Rif ids idif idload vdi
Ls
1
= vids +
vqs Rif iqs iqif iqload vqi
Ls
R
f1 = viqs +
f2
f3
f4
f5
332
& The Institution of Engineering and Technology 2015
f6
f7
f8
f9
f10
f11
f12
vqinj
V
+vqo iqof + in vqo
Ui Rof
Rof
vqi
1
= vvdi +
iqs iqload 2
Cif
Ui
vqinj
Vin
v
vqo iqof +
Ui Rof qo Rof
vdinj
V
+vdo idof + in vdo
Ui Rof
Rof
vdinj
1 Vin
= viqof +
vdo
Lof
Lof Ui
vqinj
1 Vin
= vidof +
v
Lof
Lof Ui qo
vdinj
i
1
Vin
i
= viqinj + dof +
vdo
dload
Cof Rof Cof Ui
Rof Cof
Cof
iqof
vqinj
iqload
1
Vin
= v idinj +
+
vqo