DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

BANGLADESH UNIVERSITY OF ENGINNERING AND TECHNOLOGY

LEVEL 4 TERM 1 EEE 453 VLSI I January 2015 Term
COURSE OUTLINE
INSTRUCTOR: HamidurRahman Room ECE 224
Phone: 9665650-6167, 01713-035309
TEXT Book:
Design of VLSI system A practical introduction by Linda E. M. Brackenbury,
MacMillan Education Ltd.
Basic VLSI Design (3rd Edition) by Douglas A. Pucknell and Kamran Eshragian,
Prentice Hall
CMOS VLSI design (4th edition) by Weste, Harris & Banerjee
CMOS Circuit Design, Layout and Simulation( 2nd Edition) by R. Jacob Baker, WileyIEEE
Reference Book:
Fundamentals of Digital Logic with Verilog Design Stephen Brown and
ZvonkoVranesic, Tata McGraw-Hill Publishing Company Ltd, Tata-McGraw-Hill
Edition 2002.
Digital Integrated Circuits by Rabaey
Lecture Plan:
1st week :
Integrated circuit trends, choice of technology, Design approaches. MOS device : structure,
operation, threshold voltage and characteristics equation for NMOS and PMOS devices.
(Text Book1 , 3 Design of VLSI System & Text Book 3)
2nd week:
Principles of inverters : NMOS inverters design with resistive and NMOS enhancement
transistor load. Ratioed and ratioless design. (Text Book1 , 3 Design of VLSI System)
3rd week:
The CMOS inverter : operation, transfer characteristics, design for equal rise and fall time.
(Text Book1, 3 Design of VLSI System)
Class test 1
4th week
Propagation delay, rise time, fall time and power consumption estimation( Text Book 3
-CMOS VLSI design, Hand out)
5th week:
NMOS pass transistor, CMOS pass gate. Buffer chain design to drive large capacitive load.
(Text Book1, 3 Design of VLSI System)
Latch-up in CMOS circuits. (Text Book 2, 3 - Basic VLSI Design)

6th - 7th week:

Integrated circuit fabrication technology. Wafer processing: oxidation, deposition, ionimplantation and diffusion technique. Preparation of photomask, Basic steps of
photolithography, patterning of SiO2 diffusion mask, fabrication process of NMOS and
PMOS transistor.Fabrication of NWELL, PWELL and twin-tub CMOS process. Design rules
of CMOS process. Resistance and capacitance estimation from layout.( Text Book 3 -CMOS
VLSI design)
Class test -2
8th week:
Subsystem design and Layout. Basic logic gates in CMOS. Synthesis of arbitrary
combinational logic in CMOS, pseudo-NMOS, dynamic CMOS, clocked CMOS and CMOS
domino logic. (Text Book 2 - Basic VLSI Design)
9th -10th week:
Examples of structured design : Parity generator, bus arbitration logic for n-line bus,
multiplexers and general logic function block. Programmable logic array (PLA)
design.Clocked sequential circuit design: two phase clocking, inverting and non-inverting
dynamic register element and dynamic shift register.Electromigration and current limitation
for VDD and GND lines. (Text Book 2 - Basic VLSI Design)
Class test 3
11th week:
Digital system design using verilog Hardware Description Language. (Text Book -4)
12th week
Subsystem design process. Basic structure of 4-bit arithmetic processor: bus architectures,
shifter, design of a general purpose ALU. (Text Book 2 - Basic VLSI Design )
13thweek :
Memory elements design: System time consideration, dynamic shift register, three transistor
and one transistor dynamic memory cell. Pseudo-static RAM/register cell.4 transistor
dynamic and 6 transistor static CMOS memory cell. 4x4 bit register array and 16 bit static
CMOS memory array. (Text Book 2 - Basic VLSI Design)
Class test 4
14th Week
Testing VLSI circuits (Niraj K Jha, SandipKundu - soft copy)