Department of Electronics and Communication

T K M College of Engineering
Kollam 691005

Certificate
This is to certify that the project entitled

FFT IMPLEMENTATION ON FPGA

being submitted by

BENVIN BAIJU

11403008

For the award of the degree of bachelor of technology in Electronics and

Communication Engineering of University of Kerala is a Bonafide account of
the work carried out by him in this department during the academic year 2014-15

Dr. SHEEBA.O
(Co-ordinator )

Dr. SHAHUL HAMEED

(Guide)

Dr.S. SURESH BABU

( Head of Department)

ACKNOWLEDGEMENT

We express our sincere gratitude to Dr. S.Suresh Babu, Head of

Department, ECE, for his valuable guidance, encouragement and support
extended to us for preparing the project design.
We would like to express our sincere thanks to Dr. Shahul Hameed and Dr.
Sheeba O, our guide and co-ordinator for the project, for their valuable advices,
which enabled us to complete the designing of the project.
We sincerely thank all the staff of ECE Department for providing their
valuable guidance and support.
Last but not the least, we would like to thank our parents and friends for all
the moral support and help they extended to us in the completion of this project
design.

BENWIN BAIJU

ABSTRACT

The fast Fourier transform (FFT) algorithm now play an important role in the
design of digital signal processing system for communications, measurement and
control applications. Although the algorithm was developed for use on generalpurpose computers, or special purpose microprocessor (DSP Ps),Semiconductor
technology now make it economically feasible to implement FFT using field
programming grids array (FPGA) technique. A large number of FFT algorithms
have been developed over the years, notably the Radix-2, Radix-4, Split- Radix,
Fast Hartley Transform (FHT), Quick Fourier Transform (QFT), and the
Decimation-in-Time-Frequency (DITF), algorithms. How these algorithms fare in
comparison with each other is of considerable interest to developers of signal
processing technology. VHDL is used as a design entity and for simulation Xilinx
ISE. After comparison and simulation the FFT which is most efficient in terms of
speed is implemented on FPGA SPARTAN-6 development board.

CONTENTS

Certificate

Acknowledgement

ii

Abstract

iii

Chapter 1. INTRODUCTION

Chapter 2. FAST FOURIER TRANSFORM

2.1 Review of FFT algorithms

2.2 Types of FFTs

Chapter 3. FPGA IMPLEMENTATION OF FFTs

3.1 Basic Concept Of FPGA

3.2 Field Programmable Devices

3.3 Basic Building Blocks

11

3.4 Steps Involved in the Implementation of VHDL code

On FPGA

12

Chapter 4. IMPLEMENATION TOOLS

14

5.1 XILINX ISE

14

5.2 SPARTAN -6

15

Chapter 5. CONCLUSION

16

References

17