A Stochastic Approach To Digital Control Design and Implementation

The Florida State University
DigiNole Commons
Electronic Theses, Treatises and Dissertations
The Graduate School
10-19-2006
A Stochastic Approach to Digital Control Design

and Implementation in Power Electronics
Da Zhang
Florida State University
Recommended Citation
Zhang, Da, "A Stochastic Approach to Digital Control Design and Implementation in Power Electronics" (2006). Electronic Theses,
Treatises and Dissertations. Paper 543.
http://diginole.lib.fsu.edu/etd/543
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THE FLORIDA STATE UNIVERSITY

COLLEGE OF ENGINEERING
A STOCHASTIC APPROACH TO DIGITAL CONTROL

DESIGN AND IMPLEMENTATION IN POWER
ELECTRONICS
By
DA ZHANG
A Dissertation submitted to the

Department of Electrical and Computer Engineering
in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
Degree Awarded:
Fall Semester, 2006
The members of the Committee approve the Dissertation of Da Zhang defended on Oct.
19th, 2006
Hui Li
Professor Directing Dissertation
Emmanuel G. Collins
Outside Committee Member
Simon Y. Foo
Committee Member
Bing W. Kwan
Committee Member
Approved:
Victor DeBrunner, Chair, Department of Electrical and Computer Engineering
Ching-Jen Chen, Dean, College of Engineering
The Office of Graduate Studies has verified and approved the above named committee
members.
ii
ACKNOWLEDGEMENTS
I would like to thank my academic advisor, Dr. Hui Li for her guidance and
encouragement throughout my graduate program, and my committee members, Dr. Simon
Y. Foo, Dr. Bing W. Kwan and Dr. Emmanuel G. Collins, for their invaluable advice and
guidance. I would also like to thank the academic and administrative staff in the
Department of Electrical and Computer Engineering and the Center for Advanced Power
Systems (CAPS). Most importantly, I would like to thank my family and friends for their
support throughout my graduate school experience.
iii
TABLE OF CONTENTS
List of Tables
................................................................................................
List of Figures
................................................................................................
Abstract
......................................................................................................
Page vii
Page viii
Page xiii
1. INTRODUCTION ..........................................................................................
Page 1
1.1 Background ...........................................................................................

1.2 Objective and organization of dissertation ...........................................
Page 1
Page 5
2. STATE-OF-ART FPGA CONTROLLERS REVIEW...................................
Page 9
2.1 Hybrid DSP and FPGA based digital controller ...................................

2.2 FPGA-based controller .........................................................................
2.2 Stochastic FPGA-based controller........................................................
Page 9
Page 11
Page 15
3. STOCHASTIC ARITHMETIC ......................................................................
Page 16
3.1 Introduction...........................................................................................
3.2 Randomization Process.........................................................................
3.3 Stochastic Multiplication ......................................................................
3.4 Other Stochastic Arithmetic..................................................................
3.5 Derandomization...................................................................................
Page 16
Page 17
Page 21
Page 24
Page 30
4. NEW STOCHASTIC ANTI-WINDUP PI CONTROLLERS........................
Page 33
4.1 Introduction of stochastic integrator .....................................................

4.2 Proposed anti-windup strategies based on the stochastic integrator.....
4.3 Digital implementation of proposed stochastic anti-windup controller
Page 34
Page 36
Page 45
5. STOCHASTIC NEURAL NETWORK..........................................................
Page 46
5.1 Introduction...........................................................................................
5.2 Principles of stochastic neural network ...............................................
5.2.1 Artificial neuron...........................................................................
5.2.2 Stochastic signed multiplication ..................................................
5.2.3 Stochastic approach to sigmoid activation function ....................
Page 46
Page 48
Page 48
Page 49
Page 52
iv
6. STOCHASTIC MOTOR DRIVE CONTROLLER........................................

6.1 Introduction...........................................................................................
6.2 Stochastic speed controller analysis......................................................
6.3 Stochastic estimator design...................................................................
6.3.1 Torque and flux estimation using stochastic arithmetic ..............
6.3.2 Stochastic neural network estimator ............................................
6.4 System design .......................................................................................
6.5 Verification ...........................................................................................
6.5.1 Hardware-in-the-loop verification for stochastic speed controller
6.5.2 Verification of estimator ..............................................................
6.6 Conclusion ............................................................................................
7. STOCHASTIC NEURAL NETWORK WIND SPEED ESTIMATOR.........
Page 61
Page 61
Page 63
Page 65
Page 66
Page 71
Page 76
Page 80
Page 80
Page 82
Page 91
Page 94
7.1 Introduction to sensorless small wind turbine generation system ........

7.2 Design of the ANN wind velocity estimator.........................................
7.2.1 Principle of sensorless small wind turbine system ......................
7.2.2 Neural network estimation principle............................................
7.2.3 Neural Network Training Procedure............................................
7.2.4 Simulation results of the proposed neural network wind speed
estimator.......................................................................................
7.2.5 Hardware-in-the-loop experiment verification of the proposed
neural network wind speed estimator using RTDS and dSPACE
7.3 Stochastic Neural Network wind speed estimator design.....................
7.4 Experimental Result using FPGA and RTDS.......................................
7.5 Conclusion ............................................................................................
Page 94
Page 96
Page 96
Page 98
Page 100
Page 105
Page 112
Page 112
Page 114
8. CONCLUSION...............................................................................................
Page 116
Page 103
8.1 Summary ...............................................................................................

Page 116
8.2 Future work...........................................................................................
Page 117
8.2.1 Implement real experimental verification of stochastic motor
drive controller.............................................................................
Page 117
8.2.2 Improve random engine design....................................................
Page 117
8.2.3 Implement ANN digital hardware with on-line training characteristics Page 118
APPENDIX
................................................................................................
Page 120
A MOTOR NOMENCLATURE AND PARAMETERS.........................

B WIND TURBINE PARAMETERS......................................................
Page 120
Page 121
REFERENCES
................................................................................................
Page 122
BIOGRAPHICAL SKETCH ..............................................................................
Page 128
vi
LIST OF TABLES
Table 4.1: Integral state of the proposed stochastic anti-windup PI controller ...
Page 41
Table 5.1: Comparison of look-up table and stan activation function using
FPGA complier ..................................................................................
Page 60
Table 6.1: Comparison of digital resources used by conventional and proposed

anti-windup PI controllers...................................................................
Page 82
Table 7.1: Weights and biases of the neural network wind speed estimator .......
Page 102
vii
LIST OF FIGURES
Figure 1.1: A control system of a variable speed wind generation system .........
Page 2
Figure 2.1: Generalized concept of a DSP/FPGA digital controller ...................
Page 10
Figure 2.2: A concurrent and simple FPGA controller of an AC/DC converter

with power factor correction .............................................................
Page 13
Figure 2.3: The induction motor field-oriented control scheme implemented

as a stochastic controller ..................................................................
Page 14
Figure 3.1: The randomization process of an input variable ..............................
Page 18
Figure 3.2: Single bit random engines ................................................................
Page 20
Figure 3.3: An improved 8-bit random engine ...................................................
Page 21
Figure 3.4: The comparison between stochastic approach and traditional digital
implementation of unsigned multiplication .....................................
Page 22
Figure 3.5: Simulation diagram and result of stochastic signed multiplication ..
Page 23
Figure 3.6: Stochastic unsigned addition ............................................................
Page 25
Figure 3.7: Stochastic unsigned square ...............................................................
Page 25
Figure 3.8: Stochastic signed subtraction ...........................................................
Page 26
Figure 3.9: Stochastic integrator .........................................................................
Page 26
Figure 3.10: Stochastic square root calculation ..................................................
Page 27
Figure 3.11: Stochastic unsigned division ..........................................................
Page 28
Figure 3.12: Stochastic signed division ..............................................................
Page 29
Figure 3.13: Stochastic unsigned division without saturation problem ..............
Page 30
Figure 3.14: Feedback loop based derandomizer ...............................................
Page 31
viii
Figure 4.1: Structure of a proportional-integral (PI) controller ...........................
Page 33
Figure 4.2: Block diagram of digital integrator ...................................................
Page 34
Figure 4.3: Block diagram of the traditional and stochastic integration schemes
Page 35
Figure 4.4: Randomization process and an example ...........................................
Page 35
Figure 4.5: Traditional anti-windup strategies for digital integrator ...................
Page 37
Figure 4.6: Proposed stochastic anti-windup integration scheme (I)...................
Page 38
Figure 4.7: Proposed stochastic anti-windup integration scheme (II) .................
Page 39
Figure 4.8: Proposed stochastic anti-windup integration scheme (III) ................
Page 40
Figure 4.9: Digital design scheme of stochastic anti-windup PI controller I.......
Page 42
Figure 4.10: Digital design scheme of stochastic anti-windup PI controller II ...
Page 43
Figure 4.11: Digital design scheme of stochastic anti-windup PI controller III..
Page 44
Figure 5.1: (a) Biological neuron (b) Artificial neuron .......................................
Page 48
Figure 5.2: An example of stochastic unsigned multiplication............................
Page 49
Figure 5.3: Probability distribution of N and maximum......................................
Page 51
Figure 5.4: Stochastic approach of tansig activation function.............................
Page 53
Figure 5.5: Approximation: F(x)= (
N
1 + x 2 N 1
)
Vs G(x)= e 2 x ..
1 x
Page 55
Figure 5.6: Approximation maximum error (G(x)-F(x)) with N.
Page 56
Figure 5.7: Tansig( 2 N 1 x) vs. stan(N,x) ..............................................................
Page 57
Figure 5.8: Digital design scheme of stochastic tan-sigmoid activation function

generator .............................................................................................
Page 58
Figure 5.9: FPGA implementation result.............................................................
Page 59
ix
Figure 5.10: Stansig Approximation error with increased N...............................
Page 59
Figure 6.1: General block diagram of motor drive control..................................
Page 61
Figure 6.2: Block diagram of field oriented controlled induction motor drive
showing FGPA based torque and flux estimator ...............................
Page 62
Figure 6.3: Block diagram of proposed anti-windup PI speed controller............
Page 63
Figure 6.4: Simplified block diagram of stochastic based torque and flux
estimator.............................................................................................
Page 67
Figure 6.5: Digital implementation of stochastic flux estimator .........................
Page 69
Figure 6.6: Digital implementation of stochastic torque estimator......................
Page 70
Figure 6.7: Proposed stochastic neural network estimator for field-oriented

induction motor drive.........................................................................
Page 73
Figure 6.8: Conventional approach of neural network estimator of the induction

motor's feedback signals ....................................................................
Page 74
Figure 6.9: Proposed stochastic ANN approach of neural network estimator

of the induction motor's feedback signals..........................................
Page 75
Figure 6.10: Proposed control structure for field-oriented induction motor

drive applying stochastic theory .......................................................
Page 77
Figure 6.11: The hardware realization of proposed control algorithms using

FPGA XC3S400 ...............................................................................
Page 78
Figure 6.12: Hardware-in-the loop test setup using FPGA and RTDS................
Page 79
Figure 6.13: HIL experimental results of step speed response of proposed

controller and conventional controllers
Page 81
Figure 6.14: HIL experimental results of performance comparison of proposed

anti-windup controller and conventional anti-windup controllers...
Page 81
Figure 6.15: Matlab/Simulink model for the field-oriented control motor and
estimator...........................................................................................
Page 83
Figure 6.16: Flux estimation and comparison vs. the traditional method............
Page 84
Figure 6.17: The torque estimation error versus FPGA clock rate ......................
Page 84
Figure 6.18: Comparison between stochastic and DSP torque estimation with
different clock steps .........................................................................
Page 85
Figure 6.19: The experimental setup ...................................................................
Page 86
Figure 6.20: Maxplus II VHDL simulation of dss = (v dss Rs i dss )dt and
qss = (vqss Rs iqss )dt ....................................................................
Page 87
Figure 6.21: Experimental result of the stochastic-FPGA (VHDL coded) and

DSP ................................................................................................
Page 88
Figure 6.22: Hardware-in-the-loop test setup using FPGA and RTDS ...............
Page 90
Figure 6.23: HIL results of NN estimator performance for the induction motors
torque ...............................................................................................
Page 91
Figure 6.24: HIL results of NN estimator performance for the induction motors
flux ................................................................................................
Page 92
Figure 6.25: HIL results of NN estimator performance of unit vector: cosine wave
Page 92
Figure 6.26: HIL results of NN estimator performance of unit vector: sine wave
Page 93
Figure 7.1: Small wind turbine system ................................................................
Page 95
Figure 7.2: Power coefficient vs speed ratio........................................................
Page 97
Figure 7.3: Wind turbine power curves vs rotor speed and wind velocity ..........
Page 97
Figure 7.4: A typical structure of artificial neuron ..............................................
Page 98
Figure 7.5: Wind turbine model with NN wind speed estimator.........................
Page 99
Figure 7.6: Neural network structure of the wind speed estimator......................
Page 100
Figure 7.7: Proposed training scheme for neural network of estimating wind velocity Page 101
xi
Figure 7.8: Wind velocity estimation ANN with five tan-sigmoid neurons and
one linear neuron................................................................................
Page 102
Figure 7.9: Training error of the proposed neural network .................................
Page 103
Figure 7.10: Matlab/Simulink model of the wind speed estimator......................
Page 103
Figure 7.11: The wind turbine system with the NN wind estimator....................
Page 104
Figure 7.12: Matlab/ Simulink simulation result: Estimated wind speed vs actual
wind speed .......................................................................................
Page 104
Figure 7.13: A voltage-feed double PWM converter wind generation system

based on variable speed cage machine.............................................
Page 105
Figure 7.14: Experimental verification of the above system using RTDS ..........
Page 106
Figure 7.15: dSPACE implementation of NN based wind speed estimator ........
Page 107
Figure 7.16: Hardware verfication of the NN based wind speed estimator.........
Page 108
Figure 7.17: A simple sine wave to simulate the effect of the wind speed estimator
Page 109
Figure 7.18: A simple sine wave to simulate the effect of the wind speed estimator
with a low pass filter ........................................................................
Page 109
Figure 7.19: Wind speed vs estimated wind speed using RTDS .........................
Page 110
Figure 7.20: Fast wind speed vs estimated wind speed using RTDS ..................
Page 110
Figure 7.21: Stochastic ANN wind velocity estimator ........................................
Page 111
Figure 7.22: Experimental setup for a varied-speed wind turbine system using
a hardware-in-loop real-time digital simulation ..............................
Page 113
Figure 7.23: (a) Experimental result of wind speed estimation using

stochastic-ANN-FPGA implementation; (b) Experimental result
of wind speed estimation using look-up table -ANN-FPGA
implementation ................................................................................
Page 114
Figure 8.1: Hardware Implementation of a single bit pseudo-random engine ....
Page 117
xii
ABSTRACT
This dissertation uses the theory of stochastic arithmetic as a solution for the FPGA
implementation of complex control algorithms for power electronics applications. Compared
with the traditional digital implementation, the stochastic approach simplifies the computation
involved and saves digital resources. The implementation of stochastic arithmetic is also
compatible with modern VLSI design and manufacturing technology and enhances the ability of
FPGA devices
New anti-windup PI controllers are proposed and implemented in a FPGA device using
stochastic arithmetic. The developed designs provide solutions to enhance the computational
capability of FPGA and offer several advantages: large dynamic range, easy digital design,
minimization of the scale of digital circuits, reconfigurability, and direct hardware
implementation, while maintaining the high control performance of traditional anti-windup
techniques. A stochastic neural network (NN) structure is also proposed for FPGA
implementation. Typically NNs are characterized as highly parallel algorithms that usually
occupy enormous digital resources and are restricted to low cost digital hardware devices which
do not have enough digital resource. The stochastic arithmetic simplifies the computation of NNs
and significantly reduces the number of logic gates required for the proposed the NN estimator.
In this work, the proposed stochastic anti-windup PI controller and stochastic neural
network theory are applied to design and implement the field-oriented control of an induction
motor drive. The controller is implemented on a single field-programmable gate array (FPGA)
device with integrated neural network algorithms. The new proposed stochastic PI controllers are
also developed as motor speed controllers with anti-windup function. An alternative stochastic
NN structure is proposed for an FPGA implementation of a feed-forward NN to estimate the
feedback signals in an induction motor drive. Compared with the conventional digital control of
motor drives, the proposed stochastic based algorithm has many advantages. It simplifies the
arithmetic computations of FPGA and allows the neural network algorithms and classical control
xiii
algorithms to be easily implemented into a single FPGA. The control and estimation
performances have been verified successfully using hardware in the loop test setup.
Besides the motor drive applications, the proposed stochastic neural network structure is
also applied to a neural network based wind speed sensorless control for wind turbine driven
systems. The proposed stochastic neural network wind speed estimator has considered the
optimized usage of FPGA resource and the trade-off between the accuracy and the number of
employed digital logic elements. Compared with the traditional approach, the proposed estimator
uses minimum digital logic resources and enables large parallel neural network structures to be
implemented in low-cost FPGA devices with high-fault tolerance capability. The neural network
wind speed estimator has been verified successfully with a wind turbine test bed installed in
CAPS (Center for Advanced Power Systems).
Given that a low-cost and high-performance implementation can be achieved, it is
believed that such stochastic control ICs will be extended to many other industry applications
involving complex algorithms.
.
xiv
CHAPTER 1
INTRODUCTION
1.1 Background
Power electronics has already shown its importance as an indispensable solid-state
technology for industrial process applications after decades of evolution and advance. The
implementation of power electronics techniques brings energy, cost and space savings,
elimination of severe audio noise, reduction of maintenance and improvement of
performance and reliability. Industrial automation, energy conservation and environmental
pollution controls now increasingly depend on the techniques and development of power
electronics. Due to the drastically reducing cost and dramatically improved system
performance of power electronics, its applications are extended to various areas like
industrial, commercial, residential, municipal, and aerospace systems.
The key element of power electronics is the control of the switching converter. The
raw input power is processed under the controller and generates the desired output power.
A well-designed controller should provide high quality output. For example, when a power
converter is connected to a utility line, a well-regulated output is required. For adjustable
speed AC drives, a carefully designed controller that can provide fast speed-response is
invariably desired. A number of control algorithms and hardware implementations can be
chosen based on different application requirements. Fig. 1.1 shows a control system of a
wind generation system [1]. The system consists of a back-to-back voltage-fed converter. A
vertical wind turbine is coupled to the shaft of a squirrel cage induction generator. A PWM
IGBT (insulated gate bipolar transistor) rectifier is employed to regulate the variable
frequency variable voltage output from the generator. The rectifier also supplies the
excitation needed by the machine. The inverter topology is identical to that of the rectifier
and it supplies the generated power at 60 Hz to the utility grid. The control of both the
rectifier and inverter are highlighted in Fig. 1.1. The rectifier uses indirect vector control in
the inner current control loop while the inverter current controller adopts the direct vector
Wind Turbine
Vw
PWM Rectifier
PWM Inverter
Vd
grid
C
i
r
sl
+
*
dso
r Po
*
e
ids* = 0
Te
Vd
Vd*
UV
iqs*
Controller
Ks
SYNCHRONOUS
CURRENT CONTROL WITH
DECOUPLER AND
VECTOR ROTATOR
Pd
PI
V*
SPWM
MOD
SIGNAL
Pp
iqs*
ids*
ids*
SYNCHRONOUS
CURRENT CONTROL
AND
VECTOR ROTATOR
UV
Controller
V*
SPWM
MOD
SIGNAL
FEEDFORWARD
POWER
PF
-1
Po Calc.
PI
PI
+
+
Po
Po
*
o
Controller
Rectifier control r
Inverter
Control
+r
Figure 1.1 A control system of a variable speed wind generation system [1]
control method. The vector control algorithm permits fast transient response of the system.
In general, power electronics controllers can be classified as analog controller and
digital controller. Until now, the control of power converters is usually based on analog
solutions. The main advantages of an analog solution are low price and ease of use. With
the development of the control techniques and algorithms, the control becomes more and
more complex. Although there are still several analog commercial ICs for solving this type
of control problems, the cost reduction and improving performance of a digital controller
have made it an ideal solution for the power converter control applications. The digital
controller can also reduce the designing time. More and more research on the power
converter control using digital controller has been done in recent years [2-4].
A digital controller for the power electronic systems has the following advantages.
1.
The digital controller is in a much higher density compared with the analog
controller. Unlike an analog controller which is normally composed of several IC parts

such as operational amplifiers, a digital controller can be fully integrated into one single
chip which provides the same functionality as an analog controller does.
2.
The cost of a highly integrated digital control chip is significantly reduced in
recent years with the development of the semi-conductor techniques. It has reached the
point that the price of a single digital controller is much cheaper than the sum of several
analog parts and circuits.
3.
The compact structure of a digital controller helps to improve system
reliability and to eliminate drift and electromagnetic interference (EMI) problems. It

appears to be both cost and time consuming for an analog controller to solve such
problems .
4.
Computer based design and software programming are deeply involved in the
implementation of a digital controller. The hardware can be designed in a universal manner

and the software can be flexible. So it makes the system easy to update when the
requirements change.
5.
There are many software which can simulate the system environment and
control block, for both analog and digital controllers. But for the analog controller design,
most supported software can only do simulation. Designers must rebuild the circuits with
the simulation results. The digital controller is different. The simulation program can
directly or easily be rearranged to the supported software and downloaded to the digital
chip. It significantly saves the time of building the real circuit and also provides reliability
for the controller performance through simulation results.
6.
Normally, it is much easier to test and debug digital circuits compared with
analog circuits. The digital circuits are more stable and noise resistant.
7.
As mentioned above, for a lot of applications (especially in the medium and
high power range), it is hard to reduce the price by large-scale production and so the
engineering cost is still a predominant factor in the final products cost. One solution to
this problem is the modularization and standardization. Having some multifunctional,
flexible and universal building blocks that can be assembled and reconfigured easily to
form a wide range of different applications will reduce the cost of the engineering design
efforts by sharing with more products. A digital controller provides the ability to support
this solution. The design of a digital controller is something like writing a C++ program
that has a rich volume of supporting libraries and also has more relation to the real
hardware.
All these indicate that digital controllers can greatly reduce the expense and take
place of the existing analog power electronics controllers.

There are different kinds of digital controllers. The first generation of digital
controllers is microcontroller. Since the early 1980s, microprocessors, microcontrollers,
and microcomputers have started and tended to present tremendous impact on power
electronics [5]. Different from the existing analog controllers, they can enable the
implementation of sophisticated and complex control techniques with computer programs
in a much easier way. In the 1980s, the single-chip microcontrollers (such as the Intel
16-byte 8096), the 32-byte microprocessors (such as the Motorola 68020, Intel 80386,
Zilogs 2800) and microcomputers had already provided the abilities to performing the
dedicated and flexible jobs. Moreover, they enabled the implementation of modern control
theories (such as vector control, siding-mode control, model-reference-adaptive (MRAC)
control, fuzzy control, and state and parameter estimation) for high performance drives [6].
A DSP is a specialized microprocessor. It has the following characteristics:
1.
A DSP has faster program execution due to its Harvard architecture that
permits the overlap of instruction fetch and execution of consecutive instructions [6].
2.
A DSP chip also uses a dedicated hardware multiplier and barrel shifter and
permits these functions in one instruction cycle time.

3.
DSPs can exploit use C language or assembly code for optimized
performance.
4.
DSPs are well suited for extremely complex maths-intensive tasks. DSPs
operate in step-by-step manner and hence can provide the ability for the simple re-use of
the processing units. For example, the multiplier used for calculating an FIR can be re-used
by another routine that calculates FFTs.
Because of these characteristics, DSPs are very common in power converters
control since it exploits their mathematical oriented resources. Many arithmetic operations
are provided in a DSP to meet the demand of complex algorithms.
Due to the sequential operations, that is, instructions are executed one after the
other, and shared resources like memory busses, DSPs are not very common in high
switching frequency applications or applications that require massively parallel
calculations. Data loss may occur during the transfer of data and additional cost is needed
to solve these problems. For example, if the multiple-loop schemes of the motor controller
are to be realized by a DSP, most of the computation resource will be devoted to the inter
current-loop and PWM gating signal generations and so only very few computation
resources will be left for the other control loops and this will cause trouble to the whole
control system [7].
It is currently a popular tendency to introduce advanced Very Large Scale
Integration (VLSI) techniques such as Field Programmable Gate Array (FPGA) into power
electronics control. Compared with DSPs and Application Specific Integrated Circuits
(ASICs) that dominate the most available motor control applications, FPGA technique
provides a relatively low cost solution by combining the advantage of both two methods.
Different from DSP, all the internal logic elements of the FPGA and all the control
procedures are executed continuously and simultaneously [8]. The ability of carrying out
parallel processing by means of hardware mode enables a system operates at high speed
with good precision. In comparison with the ASICs, whose high-speed hard-wired logic
can also enhance the computation capability and thus relieve the DSP load factor, the
FPGA supports system reconfigurability and hereby readily meeting the requirements of
the industrial drives which are characterized by rapid evolution and diversified
applications. In general, FPGAs are drawing much attention in recent years due to its
shorter design cycle, lower cost, higher density and high calculation speed. In addition,
with programmable characteristics, the users can design their own ASICs according to
their own schemes, thus eliminate the involvement of the semiconductor manufacturer.
1.2 Objective and organization of dissertation
The problem currently encountered in the design of a single FPGA chip based
Power Converters controller is that the limited logic gates available in the device cannot
support complex algorithms which are normally needed for the modern power converter
control. The math-intensive functions in the control algorithms occupy large amount of the
logic elements in the FPGA. Even for a few examples that choose simple control
algorithms and hence are able to be implemented using FPGA controllers, the number of
logic cells used for the control is quite big and so the expensive FPGA chip with more
logic gates have to be selected, which greatly increase the products cost.
The objective of this dissertation is to provide a solution to simplify the
complicated mathematical functions and reduce the logic gates used in the FPGA device
for the complex control algorithms. The stochastic arithmetic based on the statistic theory
is applied to replace the normal mathematical operations to reduce the computational logic
elements involved and to enable the implementation of power converter controller using
one single FPGA device.
Chapter 2 presents a review of the literature on FPGA based digital controller for
power electronics applications. Three different FPGA based digital control topologies are
recognized: DSP and FPGA hybrid controller, FPGA controller and stochastic FPGA
controller. The DSP and FPGA hybrid controller combines the advantages of both
to
provide a solution for complicated control algorithms. However, the increasing cost and
implementation difficulties limit its applications. The FPGA based controller has the
advantages of high calculation speed and low cost, but its limited ability in mathematical
operations calculation hinders it from many applications. The stochastic FPGA based
controller has just been introduced recently [9] and not many applications have been
applied. However, it provides a possible solution to enhance the computational ability of
FPGA with the same amount of digital logical gates.
Chapter 3 introduces the principle of stochastic arithmetic. Stochastic arithmetic
normally contains three processes: randomization, stochastic arithmetic operation and
derandomization. The randomization process transforms the input data into a random
sequence that only has 1 and 0. The probability of 1 appears in the random sequence
containing the input value. The stochastic arithmetic operations include multiplication,
addition, square, subtraction, integration, square root and division. The derandomization
process is to convert the random sequence into the normal value.
Chapter 4 presents the design and implementation of three new stochastic
anti-windup PI controllers using FPGA. Proportional-integral (PI) controllers are probably
the most commonly used controllers among power electronics applications. The developed
designs provide solutions to enhance the computational capability of FPGA and offer
several advantages: large dynamic range, easy digital design, minimization of the scale of
digital circuits, reconfigurability, and direct hardware implementation, while maintaining
the high control performance of traditional anti-windup techniques.
Chapter 5 presents the proposed stochastic neural network structure. Neural
network (NN) algorithms have growing applications in motor drives to estimate machine
parameters, to generate PWM signals and to design neural controllers. The main
advantages of using neural network algorithms are simplifying the complicated algorithms,
reducing heavy computation demands and improving fault tolerance. In spite of the
apparent potential benefits, broader acceptance of neural network algorithms in motor
drives is still hampered mainly by implementation issues. The current analog
implementations of NN suffer from the non-ideal properties of analog circuit and the
traditional digital implementations cannot provide chips with adequate processing power at
an attractive price [10]. FPGA is concurrent, which supports the massively parallel
calculation of neural network. However, the enormous digital resources involved in these
implementations dramatically increase the cost and complexity of the FPGA IC and block
it from most industry motor drive applications. This problem can be resolved with the
utilization of stochastic arithmetic. The stochastic signed multiplication and stochastic
tansig activation approach are discussed.
Chapter 6 presents an FPGA-based control IC for the field-oriented control of an
induction motor drive. The most important difference from the previously proposed motor
drive control ICs is that it is based on stochastic arithmetic to implement the neural
network algorithm and digital PI algorithms with anti-windup function. These advanced
algorithms need too much required silicon area and are normally hard to be achieved in the
motor control IC design. The main advantage of the proposed method is that the required
digital resources for these algorithms are significantly reduced and the whole control
algorithm can be implemented into a low complexity inexpensive FPGA chip. This
approach simultaneously exploits the high speed of hardware implemented complex
algorithms and the capabilities of traditional control algorithms. The proposed control IC is
verified using an FPGA XC3S400. Due to the advantages of debugging, design period and
real time testing, a hardware-in-the-loop (HIL) test platform using Real Time Digital
Simulator (RTDS) is built in the laboratory and the HIL experimental results show that the
proposed FPGA-based control IC can achieve the high performance of adjustable speed
induction motor. Given that a low-cost and high-performance implementation can be
achieved, it is believed that such control IC will be extended to many other industry
applications involving complex algorithms.
Chapter 7 presents another application of a proposed stochastic neural network for
a small wind energy generation system. Artificial neural network (ANN) principles are
applied to implement a novel wind velocity estimator. The proposed stochastic neural
network structure is also introduced to the FPGA implementation of the designed wind
speed estimator. By employing this FPGA based stochastic neural network estimator,
highly precise and fast calculation may be instantly implemented with several stored
weight and bias vectors. Consequently, the complicated algorithm involving the
time-consuming calculation is achieved in a simple and cheap way without losing
accuracy.
Chapter 8 concludes this dissertation. The contributions of the stochastic FGPA
based digital controller to existing power electronics digital controller technology are
summarized and future research directions are provided.
CHAPTER 2
STATE-OF-ART FPGA CONTROLLERS REVIEW
This chapter presents the state-of-art VLSI technology applied to power electronics
controllers using FPGA. Section 2.1 introduces the hybrid DSP and FPGA based digital
controller. Section 2.2 presents the digital controllers using only FPGA. Section 2.3
introduces the stochastic FPGA based digital controller.
2.1
Hybrid DSP and FPGA based digital controller

DSPs have been widely used in the control of power electronics these years. The
high calculation speed provides the ability to implement complex outer loop control
algorithms [11]. However, DSPs depend heavily on their pipeline architecture and cache.
The software and hardware interrupts normally disturb their mechanisms and slow down
execution speed [12]. Although the DMA controller of DSPs is able to move data in and
out without interrupting the CPU, the inner loop control algorithms such as the current
control loop require the data to be processed immediately with a low latency. This
limitation of DSPs could be overcome by adding a FPGA controller for data buffering and
the low-latency current control. Some research works have been done by using a
DSP/FPGA mixed controller. For example, a space-vector PWM control integrated circuit
(IC) [13] is proposed and can be incorporated with a DSP to provide a simple and effective
solution for high-performance ac drives.
Fig 2.1 illustrates the generalized design concept of a DSP and FPGA based
platform for rapid prototyping of power electronic converters. The platform is largely
digitalized since numerous programmable digital building blocks exist with sufficient
computational power, and on the other hand, the programmable analog system building
blocks lack sufficient bandwidth for most converter applications. So the analog section
only includes a high performance analog to digital converter (ADC) and the galvanic
PC
DSP
A
LAN
FPGA
Modular 3-phase inverter
Motor
(Any type)
Additional
outputs
M
3 top/bottom
invertor
outputs
3 current
serial inputs
12-bit
ADC
Current meas.
1 voltage
serial input
Quadrature
Encoder
input (QEP)
Optical
link
12-bit
ADC
DC-bus
voltage meas.
Position
encoder
Connection board
Figure 2.1 Generalized concept of a DSP/FPGA digital controller [12]
10
isolation required for safety and electromagnetic compatibility (EMC). The rest of the
system is fully digitalized. A powerful general-purpose DSP is selected for the signal
processing, user interface and monitoring. A large FPGA is implemented for the data
acquisition and fast control loops. It also provides the function of buffering of the data
subsequently used by the DSP. This platform has been used to design a sampled-data
three-phase dual-band hysteresis current controller and it proves that the FPGA increases
the flexibility and speed of the system.
The DSP/FPGA mixed controller has lots of advantages over the single DSP based
controller. It provides fast control speed, extra system flexibility and easier software design
since the tasks are divided into two parts for DSP and FPGA. However, this structure also
increases the systems complexity and cost due to its dual devices. It also makes the
hardware harder to test thanks to its complicated structure. Also, DSP is still customized
solutions which are based on software implementation. Meanwhile, FPGA supports direct
hardware implementation and gives the user a chance to arbitrarily design their own ASICs
in lab according to their schemes, without having to involve the semiconductor
manufacture. So for the mixed DSP/FPGA controller, only the FPGA part has this feature
of flexibility and the DSP part still requires long development cycle and poor reuse of
codes.
2.2 FPGA based controller

Another approach is to implement the control algorithm in one single FPGA chip
instead of the common DSP solutions or the DSP/FPGA mixed structure. There are few
published researches on this approach. One of these [4] is applied in a single-phase PWM
inverter. The multiple-loop control scheme, which incorporates an inner current loop with
an outer voltage loop to regulate the output voltage of the PWM inverter, is implemented
based on FPGA XC4010 and the complexity of the control system has been tremendously
reduced. Another application of FPGA controller [3] is shown in Fig. 2.2. Fig.2.2 (a)
presents the general structure of a power factor correction converter whose objective is to
take energy from the ac source and reduce the harmonic currents as much as possible. The
11
control algorithm is illustrated in Fig.2.2 (b). It has two control loops: one is the current
loop to make the input current proportional to the input voltage, the other one is the voltage
loop to control the output voltage. The digital version of a charge control [14] for PFC
converter is selected as the current loop control algorithm and shown in Fig.2.2 (c). This
algorithm is not feasible in a DSP because of the DSP sequential nature. At least two
instructions would be necessary after every sample (addition and comparison) and this
makes the DSPs process too slow for obtaining an acceptable duty cycle resolution. By
using FPGA, this algorithm could be implemented. This approach is different from the
traditional algorithms based on PID since no duty cycle is calculated but the switch is
controlled directly. So the average input current is controlled more accurately because the
PWM module is embedded inherently in the proposed algorithm. The voltage control loop
is also calculated for its digital representation and is implemented in the FPGA controller.
Based on the concurrency characteristic of the FPGA device, the new high-speed algorithm
in which all the resources are executed simultaneously can be used for the PFC converter
control while still allowing the system to perform with high accuracy in spite of its
simplicity.
FPGA based digital controller has many advantages compared with the DSP and
mixed DSP/FPGA controllers. It supports high-speed and concurrent control algorithms
and also provides a rapid low-cost manufacturing solution. Moreover, the control
algorithms could be developed in VHSIC (Very High Speed Integrated Circuit) hardware
description language (VHDL) which is now one of the most popular standard HDLs [15].
This language is virtually independent from any particular components or manufacturers
and is supported by all major Computer Aided Engineering (CAE) platforms [16]. The
VHDL code could easily be reused and synthesized into any FPGA and even has a possible
direct path to a customized chip. In this way, the VHDL supports direct hardware
implementation with the same flexibility as software solutions.
The digital controller using only one FPGA device is promising for its cost and
performance. But the number of available logic gates in a typical FPGA device limits its
applications. Also, the complex arithmetic operations in the control algorithm require too
much system resource, which may exceed the devices ability or significantly increase the
12
FPGA
CONTROL
(a) General Scheme of a Power Factor Correction converter
(b) Block diagram of the system and control algorithm
( C ) Current-loop controller scheme

of FPGA
(d) Voltage-loop controller scheme

of FPGA
Figure 2.2 A concurrent and simple FPGA controller of an AC/DC converter with power
factor correction [4]
13
U sqr
isqref
ref
+
-
er
r
sd
U sqs
e j U
s
sd
Ua
2 -> 3
Ub
PWM
Inverter
2 p Lm
3
Unit Vector
Calculator
ia
Rotor Flux
Estimator
ib
er
e+ j
2 <- 3
Figure 2.3 The induction motor field-oriented control scheme implemented as a stochastic controller [9]
14
products cost. Until now, most related research work using FPGA devices are focusing on
the PWM ICs (Integrated Circuits) designs [16]-[19] which is still attached to DSP to
construct the whole controller or some simple converter designs [20]-[22]. The potential of
implementing one FPGA chip based controller has not been fully exploited in the
complicated motor control or complex converter control applications.
2.3 Stochastic FPGA based controller

The limitation for FPGA based controller is its limited number of available logic
gates in a typical chip. Modern motor and converter control algorithms including
intelligence control are normally complex and need large number of calculation elements.
The state-of-the-art FPGAs lack the gate density necessary to implement these complex
control algorithms. On the other hand, stochastic arithmetic has been known for many
years [23] due to its ability to save digital implementation resource. It was first applied in
the areas of machine computation simplification which are faced with large, power hungry,
and relatively unreliable hardware implementations. By using stochastic arithmetic, it is
possible to achieve complex computation with very simple hardware [24]. Recently,
Andrei Dinu proposed to apply this method for Motor Controllers [9]. In his paper, he
proposed the idea to use stochastic controller to implement the traditional field-oriented
control scheme, as shown in Fig. 2.3. However, there is no implementation in his research.
15
CHAPTER 3
STOCHASTIC ARITHMETIC
3.1 Introduction
Stochastic computing principles have been known for many years (B.R. Gains,
1969). The motivation for applying stochastic arithmetic to computation is its simplicity.
The hardware implementations of many control applications are normally
space
consuming due to huge size of digital multipliers, adders, etc. Stochastic arithmetic
provides a way to carry out complex computations with very simple hardware and very
flexible design of the system. The stochastic implementation is also compatible with
modern VLSI design and manufacturing technology [24].
The fundamental principles of the stochastic arithmetic [8], [16] are summarized as
followings:
All inputs are transformed to the binary stochastic pulse streams. This is called
randomization. In this step, the real number is coded into a sequence of binary bits
where the information is contained in the probability of any given bit in the stream
being a logic '1'.
The stochastic arithmetic that consists of digital gate circuits takes place of the
normal arithmetic. After the first step, the real number becomes the one bus random
stream and so the math operations including multiplication, addition, division,
integration and many others can be implemented with simple digital circuits.
The stochastic pulse streams are converted back to the normal numerical values.
After these corresponding math operations, the result is still the stochastic binary
streams. This process is to extract the probability information from the streams and
get the real number with the proper representation type. This step is called
derandomization.
16
The details of the stochastic arithmetic are presented in the following sections.
Section 3.2 presents the principles of randomization and different formats of the stochastic
representation of the real numbers. Section 3.3 uses the multiplication process as an
example to demonstrate the principle of stochastic operation and the advantages over
conventional arithmetic operation. Section 3.4 presents the structures of recently published
stochastic arithmetic. Section 3.5 presents the derandomization process.
3.2 Randomization Process

The Randomization is to transform the real data into binary stochastic pulse
streams. There are three formats for the stochastic representation of the real numbers. If X
is the coded number and p is the probability to have a bit '1' on any position in the bit
stream, then:
a). X in the range of [- ,+ ], the relation is
X =
p
1 p
(3.1a)
b). X in the range of [0,1], the relation is

(3.1b)
X=p
c). X in the range of [-1,1], the relation is

(3.1c)
X = 2 p 1
Each of these three formats has its own advantages and disadvantages. (3.1a) has a
wide data change. However, the calculation accuracy is low. (3.1b) and (3.1c) have a small
range of representation with high accuracy. Normally, (3.1c) is chosen for the stochastic
neural network because of the consideration of accuracy and the threshold characteristic of
the activation functions. To satisfy the range limitation, proper normalization is required.
The randomization process can be further explained in Fig. 3.1. Fig. 3.1 (a)
presents the randomization process of (3.1c) with a normalization gain of 1/C. Fig 3.1 (b)
also shows an example with X=128 and C=256. The probability distribution process is also
presented in Fig 3.1 (c). In general, the objective of randomization is to represent the input
data with a sequence of binary bits in which the information of the input data is coded in
17
Randomization Block
Input X
-C<X<C
A
A>B
B
0.5
Pseudo
Random
Engine
Constant
C
X
+1
C
PX =
2
Output Y
1-bit stream
0<R<C
(A) Stochastic Randomization Process
X=128
C=256
PX =
3
4
Y:
011011101101111011111 ...
...
(B) An example
Distribution of Probability
Probability of 1
appears in the
PX
output 1-bit stream
0
(C) Probability distribution in the output stream
Figure 3.1 The randomization process of an input variable [9]
18
the statistical properties of the random stream. For the data in the range of [0,1),
X = p gives the relationship between the input data and the statistical properties of the
random stream and for the input data in the range of [-1,1], X = 2 p 1 gives the relations
where p is the probability to have a bit 1 on any position in the bit stream and X is the
input data which needs to be coded.
Normally, the streams of random numbers are generated by a random engine which
provides the fundamental of stochastic transformation. In a purely digital environment, true
randomness is extremely hard to be obtained, so a pseudo-random stream is generated
instead. The pseudo-random numbers are not truly random. Rather, they are computed
from a mathematical formula or simply taken from a precalculated list. But in its period,
the pseudo random numbers have the same statistic characteristics compared with the truly
random and so if the period is long enough, the pseudo random numbers could have the
same performance as the truly random numbers. For the stochastic arithmetic, the
necessary equal distribution of probability can be obtained from the pseudo random
streams if the probability corresponding to each of the N bits of the random samples is 0.5
and also the process responsible for the generation of individual bits are not statistically
correlated. Both of the requirements could be simply achieved by selecting the suitable
seeds. In the digital logic circuit, the pseudo random bits could be easily implemented by a
linear feedback shift register (LFSR) with a feed-back loop containing an XOR gate. Fig.
3.2 gives an example circuit of the classical cascaded random engine using D-flip-flops
and a feedback loop closed through an XOR gate. The operation is cyclical. The length and
content of cyclical pattern generated depends on the number of D-flip-flops and on the
signals included in the feedback loop to the XOR gate.
For the N-bit pseudo random stream generation, the length of each one-bit pattern
needs to be even. Otherwise the probability 0.5 required for each bit stream is impossible
to obtain. The length of the combined N-bit pattern is the smallest common multiple of the
individual one-bit pattern lengths and thus the long pseudo random patterns of N-bit
samples can be obtained if the lengths of the one-bit patterns do not have common integer
divisors except 2. For example, the patterns of 5,7,11,13,17,19 constructed a 6-bit
19
randomization engine and the aggregate cycle length is 3,233,230 which is more than
enough for the stochastic arithmetic calculation with the power converter applications [9].
Out
SET
CLR
SET
CLR
SET
CLR
SET
CLR
SET
CLR
SET
CLR
reset
clk
Figure 3.2 single bit random engines
However, for some input values, the direct outputs of Fig. 3.2 cannot be used to
adequately randomize the input variable. If the seeds or default data in these flip-flops have
too many zeroes, only few significant bits are involved in the randomization process and
may result in a relatively short pseudo-random sequence. [9] Especially when the input
sequence only has one 1 and all other 0s, it will only generate a very short cycle which
is repeated throughout the output bit stream. Dinu [9] has proposed a method to eliminate
this drawback. This method adds a supplementary XOR state that generates each output bit
of the randomization engine based on several LSFR signals and effectively increases the
length of the individual bit patterns with just a small increase of the involved digital
sources. Fig 3.3 shows an improved 8-bit random engine proposed by Dinu [9]. However,
several rules need to be set. First, the XOR gate generating the most significant output bits
needs most number of inputs while other XOR gates for the less significant outputs can use
less inputs. The maximum number of inputs for the significant XOR gate is n. Second, it is
preferred to connect the LFSRs with the longest operation periods with the XOR gates that
generates the most significant outputs. Finally, each XOR gates must have different
combinations of the input signals to generate the maximum random sequence.
20
Besides the method introduced above, there are a large number of acceptable
solutions to improve the performance of pseudo random engine. One possible method is to
change the seeds of the pseudo random engine during the run time. Since each one pair of
CLK
L
F
S
R
0
Out0
Out1
L
F
S
R
1
Out2
L
F
S
R
3
L
F
S
R
2
Out3
L
F
S
R
4
Out4
L
F
S
R
5
Out5
L
F
S
R
6
Out6
L
F
S
R
7
Out7
Figure 3.3 An improved 8-bit random engine [9]

seeds could generate one different pattern of pseudo random streams, this method could
increase the period without adding LFSRs which will increase the system complexity.
3.3 Stochastic Multiplication

Multiplication is the basic arithmetic operation and typically presents the advantage
of the stochastic arithmetic. Fig. 3.4 (a) shows the traditional digital logic unsigned
4 4 multiplier which composes of tens of logic gates. However, the stochastic unsigned
21
multiplier shown in Fig. 3.4 (b) greatly reduces the number of the logic elements used for
the calculation. Fig. 3.4 (c) presents an example of unsigned stochastic multiplication. The
stochastic unsigned multiplier uses an AND gate as the arithmetic operator.
m2
m3
m0
m1
q1
PP1
mk
mk +1
q0
q0
q1
cout
q2
cin
Full Adder
A block in the up row
PP2
mk
qj
q3
cout
p7 p 6
p5
p3
p4
p2
p0
p1
Full Adder
cin
A block in the bottom two rows
(a) A traditional 4 4 unsigned multiplier circuit [25]

Comparator
A
A>B
B
Comparator
A
Y
1
Z
Pseudo
Random
Stream
Engine
A>B
D-flip-flop
Px Py
Px
AND
AND
Derandomization
Py
X Y
Comparator
Stochastic unsigned
Multiplication
(b) The Stochastic implementation of unsigned multiplication
1 1 1
1 101100100010110010101101001011 px p y = pout 2 3 = 6
1 000000100000010010000100001000
2
AND
1
6
3 010010100001010010010100001100
(c) An example of unsigned multiplication
Figure 3.4 the comparison between stochastic approach and traditional digital
implementation of unsigned multiplication.
22
With the one-bit stream represented inputs, the unsigned multiplication is as simple
as just one AND gate. It is obvious that ( PX AND PY ) = PX PY = X Y . The digital
implementation of signed multiplication is derived based on the following equations:
X = 2 pX 1
Y = 2 pY 1
X Y = 2 p XY 1
(3.2)
PXNOR = p X pY + (1 p X ) (1 pY ) = 2 p X pY p X pY + 1
(3.3)
X Y = (2 p X 1) (2 pY 1) = 4 p X pY 2 p X 2 pY + 1
(3.4)
= 2 (2 p X pY p X pY + 1) 1 = 2 p XNOR 1
1
Constant1
1/2
Gain1
sine wave1
>=
Relational
Operator1
random
engine1
1
1/2
Constant
Gain2
XOR
NOT
AND2
AND1
>=
In1Out1
derandomizer
Relational
Operator2
Scope1
random
engine2
sine wave2
1
Constant2
dataout
To Workspace1
Product
(a) Simulation Diagram of stochastic signed multiplication

0.4
0.2
Stochastich mulitplication
-0.2
normal mulitplication
-0.4
10
12
14
16
18
20
(b) Comparison between stochastic signed multiplication and normal multiplication

Figure 3.5 Simulation diagram and result of stochastic signed multiplication
23
(3.2) gives the signed representation of X , Y and X Y while the output of a

XNOR gate has the probability relation of (3.3). (3.4) derives the expression of the signed
multiplication and so the signed multiplication could be performed using one XNOR gate.
From this example, the implementation of stochastic arithmetic usually has the
following steps:
1. Transform all the input data into random streams of bits with the information
contained.
2. Replace the normal arithmetic operations with the stochastic arithmetic
calculations. This step could significantly save digital circuits.
3. Convert the result random streams back into normal numerical values.
Fig. 3.5 (a) shows the simulation diagram of signed stochastic signed multiplication
using Matlab/Simulink and Fig. 3.5 (b) presents the simulation result of signed
multiplication.
3.4 Other Stochastic Arithmetic

The previous section discusses the stochastic multiplication in detail. In this
section, the commonly used stochastic arithmetic are briefly introduced including addition,
square, subtraction, integration, division and square root [26].
3.4.1 stochastic addition
Figure 3.6 presents the stochastic unsigned addition. It is based on a two-port

selector and the selection signal is decided by a stream of random bits which has the equal
probability to be 1 and 0. The two inputs are all transformed into stochastic
representations. The selector randomly chooses the output from the two input streams.
Since the possibility of both ports are the same, so the result contains the probability
information from both of the two input ports which gives the addition performance. From
the figure, if the input X has the probability of PX and input Y has the probability of PY, the
output stream has the output probability of
PX + PY
which is automatically normalized.
2
24
Comparator
Px + Py
A
A>B
B
Px
input1
Comparator
A
Y
1
Z
A>B
D-flip-flop
Py
MUX
2:1
input2
select
Derandomization
B
Comparator
Pseudo
Random
Stream
Engine
Figure 3.6 Stochastic unsigned addition
3.4.2 stochastic square
Figure 3.7 presents the stochastic square operation. It composes of a D flip-flop and
an AND gate. The AND gate performs the stochastic unsigned multiplication and the two
inputs are the input X and its sequence after the D flip-flop. Based on the random theory,
the output of the D flip-flop has the same probability as the input sequence. However, it is
independent from its input sequence, which is an important condition for the stochastic
unsigned multiplication.
Comparator
A
X
1
Z
Derandomization
A>B
D-flip-flop
clk
Pseudo
Random
Stream
Engine
Comparator
X2
Figure 3.7 Stochastic unsigned square

3.4.3 stochastic signed subtraction
Fig. 3.8 presents the stochastic signed subtraction. It is similar to the unsigned
addition where a NOT gate is used to change the sign.
25
Comparator
Px Py
A
A>B
B
Px
input1
Comparator
A
Y
1
Z
MUX
2:1
input2
select
Py
Derandomization
A>B
D-flip-flop
B
Comparator
Pseudo
Random
Stream
Engine
Figure 3.8 Stochastic signed subtraction
down
up
N-bit
UP/DOWN
Counter
N-bit A>B
Comparator
B
X (t ) dt
N-bit
Pseudo
Random
Engine
Figure 3.9 stochastic integrator

3.4.4 stochastic integrator
Fig 3.9 shows the stochastic integrator. The signed input is transformed to
stochastic random streams using (3.1c). An N-bit up/down counter is applied to integrate
the input. For positive input, the number of 1s should always be bigger than the number
of 0s appeared in the random sequence. If the input data has large value which means the
probability of 1 appears in the random sequence is high, the output of the up/down
counter will go up in proportion to the value of the input data, or vice versa.
3.4.5 stochastic square root
26
Square root is always not an easy operation to be implemented using digital logic
gates. Besides the traditional complicated implementation, the stochastic arithmetic
provides another approach with simple digital circuits. Fig. 3.10 shows the circuit
schematic of the stochastic square root operation. The input X is first transformed into
stochastic random sequence. Different from the previous stochastic arithmetic, a feedback
loop is introduced in the stochastic square root operation. As shown in the figure, the
output of the stochastic square root operation is fed back through a stochastic square
operator to generate the anticipated input value. This anticipated input value is compared
with the real input value to adjust the output. The close loop structure, which provides the
method to reduce the comparison error until those two values equal, sends out the correct
square root operation result. Compared with the traditional digital implementation, the
stochastic square root operation has the advantages of simple circuit and easy
implementation. However, several drawbacks need to be mentioned due to its close- loop
structure. It normally requires response time and could not send out the correct result at the
beginning and furthermore the stochastic representation will introduce noise and error. So
the applications using this approach should be limited to those who regard slow and rough
calculations as tolerable.
down
N-bit
UP/DOWN
Counter
up
N-bit A>B
Comparator
B
Q=X/Y
Q
clk
N-bit
Pseudo
Random
Engine
Figure 3.10 Stochastic square root calculation
27
down
X
up
N-bit
UP/DOWN
Counter
N-bit A>B
Comparator
B
Q=X/Y
Q=X/Y
Y
N-bit
Pseudo
Random
Engine
Figure 3.11 Stochastic unsigned division

3.4.6 stochastic division
Division is another difficult task for digital logic implementations. Many methods
have been proposed with complicated circuits. Stochastic arithmetic also provides a simple
approach using the similar close-loop structure. Fig. 3.11 shows the circuit schematic of
the stochastic unsigned division. Both the inputs X and Y are first transformed into
stochastic random sequences and then a feedback loop is introduced in the stochastic
unsigned division. As shown in the figure, the output of the stochastic unsigned division is
fed back through a stochastic unsigned multiplication with another input of Y to generate
real input value of X to adjust the output of the unsigned division. The close loop structure
provides the method of reducing the comparison error until those two values equal to send
out the correct unsigned division result.
Fig. 3.12 presents the stochastic signed division. It accepts a similar structure with
a few modifications. The stochastic signed multiplication is introduced to implement the
stochastic signed division. Different from the stochastic unsigned division, two XNOR
gates are used to perform the stochastic signed multiplication. Thus the input Y is fed
through a D flip-flop and multiplies itself to generate the square of Y. The square Y
multiplies the output Q and generates the anticipated value of X Y . The input X also
multiplies Y directly to generate the real value of X Y . The two values are then compared
to control the output until these two values are equal which gives the division result.
28
X Y
down
up
N-bit
UP/DOWN
Counter
N-bit A>B
Comparator
B
Q=X/Y
N-bit
Pseudo
Random
Engine
Q=X/Y
Q Y 2
Y
clk
Figure 3.12 Stochastic signed division
Another important issue of digital division is the saturation problem. It occurs when
the division result is too close to 1 or 0 and therefore the Gaussian distribution of
probabilities in the counter gets distorted. Normally, this saturation problem could be
alleviated by using a large counter and then the Gaussian distribution can be set closer to
the extremes to avoid saturation. However, Dinu [26] proposed a thorough solution to
solve this problem. Fig. 3.13 shows the improved stochastic unsigned division without
saturation problem. It involves three modifications to the previous stochastic unsigned
division [26].
Using an N+2 bit counter that stores signed numbers in the interval [-2N+1, 2N+1-1].
If the counter is already at value 2N-1 but still needs incrementing, then it will be
incremented once more with a probability decided by a second comparator.
Similarly, if the counter is already at level 0 but needs further decrementing, then it
will be decremented twice with probability controller by a third comparator. [9]
29
B
B
Supplied by
the Pseudo
Random
Engine
Comparator
-A>B
Double
down
X
down
UP/DOWN
Counter
up
Double
up
Q=X/Y
A>B
Comparator
Q=X/Y
Y
A/2N>B
Comparator
B
A
Figure 3.13 Stochastic unsigned division without saturation problem [26]
3.5 Derandomization
After the stochastic multiplication, the data needs to be translated back to the
normal output data. The process to get statistical information out of the random streams is
called derandomization. The derandomizaion of the random stream is determined by
counting the number K of bits 1 in a set of N consecutive samples. Large N will give
precise result while it also takes more time to catch the value from the random streams of
bits. Theoretically, K can be any value between [0, N], but some values are much more
probable than others. The results of the followings have been introduced in [27].
From the statistic theory, the probability P(K) to find K bits 1 in a set of N
samples from a stream with probability p is:
P( K ) =
N!
p K (1 p ) N K [26].
K !( N K )!
The function P(K) is a binomial distribution having the maximum at K max = p N and the
standard deviation which is expressed as = N p (1 p ) . When N is large, this
30
Data
X (stochastic
representation)
1
2N
down
up
N-bit
UP/DOWN
Counter
N-bit A>B
Comparator
B
N-bit
Pseudo
Random
Engine
Figure 3.14 feedback loop based derandomizer

probability distribution can almost be considered to have the Gaussian characteristic and
also the K is situated at a distance of 3- from Kmax with a probability of over 99.5%.
With the condition mentioned above, the derandomization error could be calculated
as the following:
p
K 3 3 N 0.5 (1 0.5)
3
[26]
=
=
N
N
N
2 N
(3.6)
Thus, it could be proved that the larger the number N of samples, the smaller the
derandomization error.
Fig. 3.14 shows the scheme of the derandomization process where a feedback close
loop structure is applied for the fast tracking ability. The output of the up/down counter
will be randomized again and compared with the input stream. When the 1 appears more
frequently or less frequently in the input stream than the output stream, the up/down
counter will continue to increase or decrease until these two frequencies are equal. This
31
derandomization method is easy to be implemented but is not suitable for the continuous
signals with extremely fast changes.
32
CHAPTER 4
NEW STOCHASTIC ANTI-WINDUP PI CONTROLLERS
Proportional-integral (PI) controllers are probably the most commonly used
controllers among power electronics applications. The purpose of a PI controller is
normally to stabilize the system, improve the transient response and achieve zero steady
state error. Fig. 4.1 shows the basic structure of a PI controller. It contains both a
proportion component and an integration component with a saturator to guarantee that the
requirement by the physical characteristics of the system will be met.
However, a large step change in the control input will cause the generated control
variable from a PI controller to exceed the prescribed maximum value. Thus a saturator is
applied, which introduces a non-linearity into the system. This phenomenon is called
integrator windup and can lead to large overshoot, long settling times, and even unstable
closed-loop systems [28] since the parameters of the PI controller are normally designed in
a linear region, ignoring the saturation nonlinearity. In an attempt to overcome the windup
phenomenon, a number of anti-windup techniques have been proposed in the literature, for
example [29-33]. Currently, digital implementations of anti-windup PI controllers are
based on a microprocessor or DSP [34]. Hardware solutions such as field programmable
gate arrays (FPGA) have advantages in price, execution speed and flexibility but are
restricted for their poor calculation ability [35] and the low available number of logic gates
uin(t)
Kp
e(t)
Ki
1
S
umax
uout (t)
umax
uin<umax and uin > umax

Figure 4.1 Structure of a Proportional-integral (PI) controller
33
in a typical FPGA [10]. Stochastic arithmetic provides an effective method of enhancing

the computational capability of FPGA with the same logic gates density [9]. This is an
efficient implementation approach that uses simple digital logic circuits but has the
advantage of significantly reducing the circuit complexity compared with the traditional
digital implementation approach.
In this chapter, new anti-windup PI controllers are proposed and implemented in a
FPGA device using stochastic arithmetic. The developed designs provide solutions to
enhance the computational capability of FPGA and offer several advantages: large
dynamic range, easy digital design, minimization of the scale of digital circuits,
reconfigurability, and direct hardware implementation, while maintaining the high control
performance of traditional anti-windup techniques.
4.1 Introduction of stochastic integrator

The digital integrator can be expressed in (4.1) and its structure is shown in Fig.
4.2.
y (n) = x(n) + y (n 1)
(4.1)
Fig. 4.3 (a) presents the traditional accumulator design of a digital integrator. A
large register holds the previous output of the integrator and sent the one step time delayed
output signal back to the adder to perform the integration function. Fig. 4.3 (b) shows
another approach of the digital integrator using stochastic arithmetic. The stochastic digital
X(n)
y(n)
+
Unit
Delay
y(n-1)
Figure 4.2 Block Diagram of Digital Integrator
34
integrator has two elements: a signal value to frequency converter (randomization block)
and an up-down (pulse) counter. In the randomization process shown in Fig. 4.4, the value
of the input signal X is represented by the frequency of 1 appearing in the output bit
stream.
Register
Input X
( a)
Output
Adder
N-bit
Accumulator design of a digital integrator
C =
Counter max
2
Input X
Up
Randomization
Block
- Output
Down
UP/Down Counter
( b ) Stochastic approach of a digital integrator
Figure 4.3 Block diagram of the traditional and stochastic integration schemes
Randomization Block
Input x
-C<X<C
Constant
C
0.5
Pseudo -random
R
engine
A
A >B
B
X
+1
Px = C
2
An example of
randomization process
X=128
Output Y
C=256
1-bit stream
011011101101111011111 ...
Y:
...
X
Number of '1's 3 C +1
Px =
= =
Total bits
4
2
0<R<C
Figure 4.4 Randomization process and an example
35
If p is the probability to have a bit 1 on any position in the bit stream then the value of the
input signal is given by the expression x = (2 p 1) c (where c is a constant and the input x
must in the range of c and c). For example, if the input x equals c, then the output bit
stream will be all 1s and if x equals to c, the output bit stream will be all 0s. After this
process, the Up/Down counter accumulates the incoming pulses and performs the
integration function.
Compared with the traditional approach of implementing digital integration, the
stochastic method has a larger dynamic range and eliminates the n-bit adder that contains
tens of logic gates. Although the randomization process requires extra digital resources for
the pseudo random engine and the comparator, these resources can be shared if many
digital integrators are employed in the same digital Integrated Circuits (ICs).
4.2 Proposed anti-windup strategies based on the stochastic integrator

To date, most developed anti-windup strategies can be classified as either a
conditional integration scheme, a back-calculation scheme or a hybrid scheme, as
illustrated in Fig. 4.5 (a), (b), and (c), respectively. The conditional integration scheme is
reported as the most popular anti-windup strategy due to its simplicity. The integral action
turns off when the output signal reaches saturators limit to avoid the accumulation of
errors which is not able to change the control performance any more. In the backcalculation and the hybrid schemes, the integral term reduces its absolute value when the
output saturates. The free tuning parameter Ka decides the decreasing rate of the integral
terms absolute value. These two schemes suffer complicated and time-consuming design
process in optimizing the free parameters Ka which decides the performance of integrator
when saturation happens.
The proposed stochastic anti-windup digital PI control algorithms are illustrated in
Fig. 4.6, Fig. 4.7 and Fig. 4.8. In Fig. 4.6, the saturation signal is connected to the
up/down counter through two AND gates. When the saturation signal is 1, the output of
the two AND gates all become 0, which disables the accumulation of the up/down
36
Conventional
Algorithms
Kp
Sampler
e(t)
A/D
e(kT)
Digital
Integrator
Ki
uout(kT)
(kT )+
u max
+ u (kT)
in
D/A and
ZOH
u max
Saturation
Signal
uout(t)
uin < umax and uin > umax
(a) conditional anti-windup integration scheme
Kp
uin(kT)
Sampler
e(t)
A/D
e(kT)
Ki
Digital
Integrator
umin
(kT )+
uout(kT)
u max
D/A and
ZOH
u max
uout(t)
Ka
umax
(b) Back-calculation anti-windup integration scheme
Kp
u in(kT)
Sampler
e(t)
A/D
e(kT)
Ki
+
-
Digital
Integrator
(kT )+
u max
Ka
uout(kT)
umax
D/A and
ZOH
+
-
(c) Hybrid anti-windup integration scheme

Figure 4.5 Traditional anti-windup strategies for digital integrator
37
uout(t)
Kp
Randomization
Block
Sampler
e(t)
A/D
e(kT)
Ki
UP/Down
Counter
Up
uin(kT)
(kT )
+ +
uout(kT)
u max
u max
Down
Saturation
Signal
uout(t)
uin (kT ) < umax and uin (kT ) > umax
Figure 4.6 Proposed stochastic anti-windup integration scheme (I)
38
D/A and
ZOH
Kp
Randomization
Block
Sampler
e(t)
A/D
e(kT)
Ki
UP/Down
uin(kT)
Counter
Up
(kT )+ +
u max
Down
uin (kT ) > umax

uout(kT)
D/A and
u max
ZOH
uin (kT ) < umax
Figure 4.7 Proposed stochastic anti-windup integration scheme (II)
39
uout(t)
Kp
Sampler
A/D
e(kT)
Randomization
Block
Ki
R
Up
uin(kT)
(kT )
+ +
umax
Down
uin ( kT ) < u max
UP/Down Counter
Figure 4.8 Proposed stochastic anti-windup integration scheme (III)
40
uin ( kT ) > umax

uout(kT)
u (t)
D/A and out
umax
ZOH
counter. The integration process will work as normal when the saturation signal is 0 for
the linear region. So this scheme has the same anti-windup function as the conditional antiwindup strategy where the integration action switches off when the saturation happens. In
the proposed scheme II shown in Fig. 4.7, when the output of the PI controller exceeds the
upper limit of the saturator, the AND gate sends out 0 to the up port of the counter and
the down port continues to receive the coming pulses and so the integral term will decrease
which will try to bring the PI controller back to the linear region. The saturation taking
place at the lower limit will cause the increase of the integral term and prevent the
accumulation of errors. The last proposed scheme shown in Fig. 4.8 provides a tuning
parameter to adjust the anti-windup performance. The output of the PI controller is
randomized to a bit-stream and connected with the saturation signals with AND gates. In
this way, when saturation happens, the up and down ports all have pulses coming, but the
randomization process decides the rate of the increase or decrease for the integral term
when saturation happens. The constant C in the randomization process becomes a free
tuning parameter that can be adjusted to get the optimized performance. If the output of the
integral is defined as , the derivative of the integral state of each proposed strategy is
derived in Table. 4.1 where Ki, shown in Fig. 4.6, Fig. 4.7 and Fig. 4.8, is the integral
constant, C is the constant appearing in the randomization process as shown in Fig. 4.4, Kup
= 1 - uin / C and Kdown =1+uin / C.
Table 4.1 Integral state of the proposed stochastic anti-windup PI controller
Stochastic
PI
Controllers
Proposed
Scheme I
Proposed
Scheme II
Proposed
Scheme III
A ( = Ae )
uin =
uout
uin > uout
uin < uout
Ki
Ki
K i C (1 e / C ) / 2
K i C (1 + e / C ) / 2
Ki
K i C1 2(1 e / C1 ) K up (1 + e / C1 )
41
K i C1 [2(1 + e / C1 ) K down (1 e / C1 )]
4
Kp
15b
15b
15b
Input
Ki
A/D
Conversion
15b
15b
1b
MSB
15b
1000000000000000
1: positive
0: negative
1000000000000000
16b
16b
16b MUX
Comparator
A
2:1
sel
A>B
16b
Comparator
A
A>B
B
N-bit Up/Down Counter
2:1
sel
15b
15b
Saturation
Limit
1b
MUX
1b
MUX
15b
16b
DOWN
LFSR
PSEUDO
RANDOM
GENERATOR
15b MUX
UP
15b
1b
MSB
1b
1000000000000000
16b
2:1
sel
15b
2:1
sel
Comparator
A
B>A
1b
B
15b
15b
15b
MUX
2:1
1b 1: positive
MSB 0: negative
sel
MUX
2:1
sel
1b
MSB
1b
MSB
1b
Figure 4.9 Digital design scheme of stochastic anti-windup PI controller I
42
2:1
sel
15b
1b
MSB
15b
15b
Output
MUX
D/A
Conversion
1: positive
0: negative
Kp
15b
15b
15b
Input
Ki
A/D
Conversion
15b
15b
1b
MSB
15b
1000000000000000
16b
1: positive
0: negative
1000000000000000
16b
16b
MUX
Comparator
A
2:1
sel
A>B
16b
B
Comparator
A
A>B
B
MUX
2:1
sel
15b
15b
Saturation
Limit
1b
MUX
1b
MUX
15b
16b
DOWN
LFSR
PSEUDO
RANDOM
GENERATOR
15b
UP
15b
1b
MSB
1b
1000000000000000
16b
2:1
sel
15b
2:1
sel
Comparator
A
B>A
1b
B
15b
15b
15b
MUX
2:1
1: positive
1b
0: negative
MSB
sel
MUX
2:1
sel
1b
MSB
1b
MSB
1b
Figure 4.10 Digital design scheme of stochastic anti-windup PI controller II
43
2:1
sel
15b
1b
MSB
15b
15b
Output
MUX
D/A
Conversion
1: positive
0: negative
Kp
15b
15b
15b
Input
Ki
A/D
Conversion
1b
MSB
15b
15b
1: positive
0: negative
15b
1000000000000000
16b
1000000000000000
16b
16b
MUX
Comparator
A
2:1
sel
A>B
16b
B
Comparator
A
A>B
B
MUX
2:1
sel
15b
15b
Saturation
Limit
1b
MUX
1b
MUX
15b
16b
DOWN
LFSR
PSEUDO
RANDOM
GENERATOR
15b
UP
15b
1b
MSB
1b
1000000000000000
16b
2:1
sel
15b
15b
15b Comparator
A
A>B
B
2:1
sel
15b
Comparator
A
B>A
1b
B
15b
15b
2:1
sel
MUX
2:1
sel
1b
MSB
1b
MSB
1b
Figure 4.11 Digital design scheme of stochastic anti-windup PI controller III
44
2:1
sel
15b
1b
MSB
MUX
1: positive
1b
0: negative
MSB
Output
MUX
D/A
Conversion
1: positive
0: negative
4.3 Digital implementation of proposed stochastic anti-windup controller

Fig. 4.9 illustrates the developed digital design scheme of the proposed stochastic
anti-windup PI controller I. The other two proposed controllers as shown in Fig. 4.10 and
Fig. 4.11 have the same structures except the feedback to the up/down counter. The
scheme is implemented in a Xilinx FPGA chip using ISE 7.01 software for design,
simulation and programming. The controller is written in the VHSIC (Very High Speed
Integrated Circuit) Hardware Description Language (VHDL).
45
CHAPTER 5
STOCHASTIC NEURAL NETWORK
5.1 Introduction
Artificial Neural Network (ANN) is the interconnection of artificial neurons and
tends to emulate the biological neural network of human brain [36]. The ANN based
intelligence controller is particularly suitable for power electronics and drives which are
nonlinear, complex, multivariable with parameter variation problem or even unknown and
thus is an important complementary to conventional techniques. There are many
advantages applying neural networks in power electronics. [37,38]
The neural network controllers or estimators normally have the immunity from
input harmonic ripple and fault tolerance characteristics due to distributed network
intelligence.
The ANN is able to implement nonlinear input-output mapping.
The ANN supports extremely fast parallel computation.
The ANN could ignore the complexity of the dedicated signal processing function
and perform the desired result.
In contrast to other techniques, neural networks can modify their behavior in

response to the environment changes.
Currently, ANNs have been applied to many power electronic areas including
PWM techniques, adaptive P-I closed loop control, delayless harmonic filtering, model
reference adaptive control, optimal control, vector control, drive feedback signal
processing, on-line diagnostics, estimation of distorted waves, etc. [6] However, ANNs are
currently still limited in the research arena for the power electronics applications which
require the hardware real-time implementation. DSP, ASIC and FPGA are the most
popular hardware devices to implement the control system in power electronics. Since
DSPs are von Neumann machines operating in step-by-step manner [9] and the instructions
46
in a DSP cannot work in parallel [37], ANN which is full of parallel calculations is
inherently not suitable for DSP. The ASIC and FPGA provides the advantages for the realtime control algorithms where ANNs play an important role because the hardware structure
can be customized to optimize the speed and to reflect the parallelism of the algorithm, but
there is also a problem. The hurdle is the unavailability of application-specific ICs (ASICs)
and FPGA with adequate processing elements at an attractive price [39]. Most ANN
applications have complicated neural network structures and require large amounts of
hardware sources. But until now, the large and economical ASIC and FPGA chips are still
pending the new development of related research area and are not available for the current
stage and this mainly disturbs the development of ANN applications. The stochastic neural
network technique presents a new approach to solve the above problem and is able to make
the ANNs suitable for current ASIC and FPGA devices. The stochastic neural network
controller combines the advantages of both the ANNs and stochastic arithmetic. These two
algorithms fit each other extremely well. The stochastic technique provides the ability to
simplify the system and allows implementation of an unusually large number of basic
computation elements on a single integrated circuit. The ANN could benefit a lot from this
characteristic. Besides the advantages of ANN as introduced in the previous part, the
stochastic arithmetic also provides some extra benefits [24]:
It allows the ability of fault tolerance.
It provides the function to reduce the system to a very low computation hardware
area and could easily be implemented using one FPGA or ASIC device because of
the simple communications over one wire per signal.
The simple hardware implementation allows high clock rate and the different clock
rates endow the capability to trade off computation time and accuracy without
having to involve in program or hardware changes.
Stochastic neural network was first proposed by Gaines [23] in the field of
computing in 1969. To the present, most of stochastic neural network research is focused
on the development of novel algorithms [7,8,24,40]. Little research is available on the realtime hardware implementation and it also lacks the applications of the developed
47
algorithms to other areas. To date, Dinu is the first person to introduce the concept of the
stochastic neural network in power electronics [9].
5.2 Principles of stochastic neural network

In general, a neural network system consists of lots of neurons which are the basic
elements of neural network. Artificial neurons usually contain three math operations:
signed multiplication, signed addition and the nonlinear activation function. Generally, the
multiplication and activation function occupy most of digital resources. So the proposed
neural network structure will apply stochastic implementation to these two operations
while leaving the rest for the traditional method. This approach has considered the trade off
between the accuracy and the number of employed digital logical elements since the
stochastic arithmetic unavoidably introduces noise and variance compared to the traditional
math operations.
5.2.1 Artificial neuron

Neurons are the most basic structures in the human brain. The biological neural
network in human body consists of billions of neurons and generates the thinking process.
Similarly, the artificial neurons interconnect together to perform the artificial neural
network (ANN) which tends to emulate the nervous system of the human brain.
(a)
(b)
Figure 5.1 (a) Biological neuron (b) Artificial neuron [6]
48
Comparator
A
A>B
B
Y
1
Z
Pseudo
Random
Engine
1
2
D-flip-flop
Px Py
Px
AND
A
A>B
B
Derandomization
X Y
Py
A) Stochastic unsigned Multiplication
101100100010110010101101001011 p x p y = p out
1
3 010010100001010010010100001100
AND
b) Example of
1 1 1
=
2 3 6
1 000000100000010010000100001000
6
1 1
2 3
Figure 5.2 An example of stochastic unsigned multiplication

The concept of the biological neuron is shown in Fig. 5.1 (a) and this information
inspires the structure of the artificial neuron shown in Fig. 5.1 (b). Both the biological
neurons and artificial neurons have the similar function. They are the basic processing
elements in the neural network systems that receive and combine signals from other nearby
neurons. The artificial neuron is analog summer-like network where the inputs signals pass
through synaptic weights (or gains) and gather in the summing node. After that, the
summed signal will pass through a nonlinear activation or transfer function to generate the
output. Most times, a bias signal is also added in the summing node.
5.2.2 Stochastic signed multiplication
Multiplication is the most frequently used operator in a neural network system.

Thus the implementation of digital multiplication is an important issue in the neural
network applications. And it is also most advantageous for stochastic arithmetic to
implement the multiplication of two stochastic binary streams. For the unsigned
representation where x=p in the range of [0,1], multiplication is simply achieved by an
AND gate. Let the two input variables be x and y. The output of multiplication is z. The
AND gate has output of 1 only when the two input are both 1s. So it is obvious that
49
p x p y = p z x y = z . Fig.5.2 presents the structure and an example of stochastic
unsigned multiplication. The signed multiplication is also convenient to achieve with only
one XNOR gate.
From the described equations, the process of the multiplication will not generate
additional errors to the result, so the error of the multiplication is decided by its inherent
variance. The binary stochastic pulse streams can be considered as a Bernoulli sequence.
The mean and variance 2 of each independent bit are:
=p
(5.1)
2 = p (1 p)
(5.2)
For a n-bit Bernoulli sequence, the probability of finding k bits 1 is:

P{k } =
n!
p k (1 p) n k
(n k )! k!
(5.3)
When n is large, the error and distribution will become hard to calculate using
(5.3). So the central limit theorem is utilized to simplify the problem and the following
equation can be derived:

a
1 t 2 / 2
n X np
e
dt
P
a
(5.4)
where X = x i and n
i =0
If we define:
x
( x) =
e t
/2
dt
(5.5)
and
( x) = 1 ( x)
(5.6)
Then applying (5.4) and (5.5) to (5.3):,we have the following probability:
a
a
n X np
1 t 2 / 2
1 t 2 / 2
P a
a
e
dt
e
dt = 2 (a) 1
n
2
2
50
(5.7)
Probability
0.95
0.9
0.85
0.8
0.1
0.08
2500
2000
0.06
1500
0.04
Maximum Error
1000
0.02
500
Figure 5.3 Probability distribution of N and maximum p
Let us define error as:
p = X p
(5.8)
Therefore from (5.6), (5.7) and (5.8), we have

a
p p
2 (a) 1
n
From (5.3), we can get max =
(5.9)
1
1
when p = . The distribution is shown in Fig. 5.3
2
2
where Z-axis is the probability for the corresponding N (X-axis) and Maximum Error
51
allowed (Y-axis). AS shown in the figure, when N is large, the maximum error reduces and
its related probability increases which can improve the accuracy. So it is possible to
increase the number of N to improve the performance.
5.2.3 Stochastic approach of sigmoid activation function
Besides the multiplication, the next stage for the neural processing is the nonlinear
activation function. The results of these continuous sigmoid-like activation functions are
limited in the range of [0,1] and for a large input which is out of the threshold, the result
could be considered as 1 or 0. For a small number of neurons in the systems, the
FPGA based lookup-table to map the activation functions can be implemented directly
with fast operating speed. However, when the number of neurons increases, the
implementation appears to be a problem since the size of the required lookup table for the
parallel calculation becomes unaffordable. B.R. Gaines [23] described the chain structure
of the generalized Adaptive Digital Element (ADDIE) with the related transition equations.
Several detailed structures for the approximations of the sigmoid like activation functions
are proposed with the computational elements based on state machines.
Fig. 5.4 illustrates the algorithm and digital implementation approach of tansig
activation function where p is the probability of "1' appearing in the stochastic pulse
streams, and the relation between x and p is X = 2 p 1 where X in the range of [-1,1].
The state machine structure of the tansig shown in Fig. 5.4 (a) is engineered by Bradley
and Card [24]. The counter in Fig. 5.4 (b) is a saturating up/down counter which has two
inputs of increment and decrement and will not increase beyond its maximum value or
decrease below its minimum value. Each value stands for different states in Fig. 5.4 (a).
The equation of the tansig function is:
1 e 2 x
tan sig ( x) =
1 + e 2 x
(5.10)
The state machine structure of Fig. 5.4 (a) is based on the theory of Markov chains
and is used to approximate (5.10). The input x (real number) to the tansig function is first
transformed to the binary stochastic pulse streams which is a single bus signal with only '1'
52
S1
S2
Output = 1
Output = 0
p
S3
S 2( N 1)
S2(N1) 1
S 2 N 2
S 2 N 1
S2N
(a) State Machine based tansig

activation function
N-bit Up/Down
Counter
UP
2N
UP
p ('1' ) =
2N-1
x +1
2
2N-1
Comparator
A
2N-1-1
A>B
DOWN
p (output ='1' ) =
2N-1-1
1
DOWN
(b) Digital Logic Implementation of

stochastic tansig function
Stan
( C) Used symbol for the state machine

based tansig activation function
Figure 5.4 Stochastic approach of tansig activation function
53
output + 1
2
and '0'. This signal is used to control the state of the counter and the output is also the
binary stochastic pulse streams which follows X = 2 p 1 and requires to be converted
back to real number. Part of the analysis below has been described in [24], [41]-[43] and
this paper further discusses the approximation process and performance with error analysis.
The probability of each state satisfies the following equations:
P ( s 1 ) = P ( s 2 ) ( 1 p ) + P ( s 1 ) (1 p )
P ( s 2 ) = P ( s 3 ) (1 p ) + P ( s 1 ) p
........
P ( s i ) = P ( s ( i + 1 ) ) (1 p ) + P ( s ( i 1 ) ) p
(5.11)
........
P ( s 2 N ) = P ( s 2 N ) p + P ( s ( 2 N 1) ) p
By solving (5.11), the relation between P ( s i ) and p( s i 1 ) is:

P(si ) =
p
P( s ( i 1) )
1 p
(5.12)
The sum of all these probabilities is 1:
2N
P( s i ) = 1
(5.13)
Combine (5.12) and (5.13), the probability of each state could be derived as:
2N
2 N 1
P(s i ) = P(s 1 ) (
i =0
p i
) =1
1 p
p
)
1 p
P(s 1 ) =
p 2N
1 (
)
1 p
1 (
(5.14)
p
1 (
)
p i 1
1 p
P(s i ) = (
)
p 2N
1 p
1 (
)
1 p
The probability of 1 in the output sequence is the sum of probabilities of the
states which are bigger than or equal to s 2 N 1 .
54
1 (
)
p
1 p
i 1
)
P (output ) = (
p 2N
i = 2 ( N 1) 1 p
1 (
)
1 p
2N
p 2 N 1
p 2N
)
(
(1 p )
1 p
=
p 2N
1 (
)
1 p
(5.15)
Suppose x is the input data and y is the output data, apply X = 2 p 1 and the
approximation equation shown in (5.17):
x = 2 p 1
(5.16)
y = 2 P(output ) 1
N
1 + x 2 N 1
)
e 2 x
1 x
(5.17)
1
0.9
0.8
F(x, N=2)
F(x, N=3)
F(x, N=4)
0.7
Output of F(x) and G(x)
F(x, N=5)
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
x
Figure 5.5 Approximation: F(x)= (
55
0.6
0.7
0.8
N
1 + x 2 N 1
)
Vs G(x)= e 2 x
1 x
0.9
Using (5.15), (5.16) and (5.17), the result of y is:
y = 2 P(output ) 1
1 + e 2
1 e
2N x
= tan sig (2 N 1 x)
(5.18)
Fig. 5.5 illustrates approximation performance of (5.17) with different N. As shown

in the figure, with the N number increases, the approximation performances improve. Fig.
5.6 shows the maximum error with different N. From that it can be obviously seen that
when N is large, the error is small and could be ignored.
Fig. 5.7 illustrates the performance of the state machine based tan sigmoid
activation function approximations with different N. The clock rate is 1Mhz, much slower
than the commercial FPGA chip which is above 100Mhz. It is obvious that the
performance improves when N increases and this verifies the above analysis. From
0.03
Maximum error of G(x)-F(x)
0.025
0.02
0.015
0.01
0.005
4
N
Fig.5.6 Approximation maximum error (G(x)-F(x)) with N
56
the figure, the random noise is still exist which could be improved with a faster clock rate.
Fig. 5.8 presents the developed digital design scheme of the proposed stochastic
tan-sigmoid activation function. The feedback derandomization block is required to

transform the stochastic output to the physical output. The scheme is implemented in a
Xilinx FPGA chip using ISE 7.01 software for design, simulation and programming. Fig.
5.9 is the experimental result of stochastic tansig versus actual tansig using FPGA. The
result is similar with Fig. 5.7 , which proves the effectiveness of approximation method.
The number of implementation errors is small. Fig. 5.10 shows the amount of errors of the
hardware implementation of stansig function that is reducing rapidly with the increase of
counter size. From both the simulation and experiment results, the approximation is able to
replace the traditional tansig activation function and thus displays the possibility to be
applied in the hardware neural network applications.
1
0.8
tansig(8x)
0.6
0.4
Output
0.2
stan(N=4)
0
-0.2
tansig(4x)
-0.4
-0.6
stan(N=2)
tansig(2x)
-0.8
-1
-1
stan(N=3)
-0.8
-0.6
-0.4
0
x
-0.2
0.2
0.4
Figure 5.7 tansig( 2 N 1 x) vs. stan(N,x)
57
0.6
0.8
n 1
n1
Saturating Bit 1 : x >= 2 or nx<= 2
Represent 0 : 2n 1 < x < 2 1
A / D 1b
15 b
1000000...0000
16b
1000000...0000
16b
15b
1b
: positive
MSB 1
0 : negative
MUX
+
16b 2 : 1
sel
Comparator
A
16b BA>B 1b
N-bit Up/Down
Counter
UP
MSB
1b
16b
Feedback derandomization
block
MUX
sel
2 :1 1b
DOWN
16-Bit Up/Down
Counter
UP
1b
16b
DOWN
1b
Comparator
A
A>B
B
LFSR
PSEUDO
RANDOM
GENERATOR
Figure 5.8 Digital design scheme of stochastic tan-sigmoid activation function generator
58
Stochastic tansig
( N=3)
1
0.5
0
-0.5
Tansig( 8x )
-1
10
Time ( s)
Figure 5.9 FPGA implementation result
0. 06
0.05
Approxi mation er ror
0. 04
0. 03
0. 02
0. 01
0
4
N
Figure 5.10 Stansig Approximation error with increased N
59
Table. 5.1 Comparison of look-up table and stan activation function using FPGA complier
Number
if bits
For
data
Stan(8,x)
8
Stan(8,x)
16
Tansig(4x) 8
One
activation
function
LCs LCs
utilized
75
2%
136 3%
417 11%
Two parallel
activation
functions
LCs LCs
utilized
142 3%
258 6%
816 21%
Table. 5.1 shows the result of the FPGA implementation of stan and tansig
function. Both are achieved using VHDL language in MaxplusII. The download FPGA
chip is EPF10K70RC240-4 (Altera). It can be seen that the stan function saves much more
logic cells and thus in one single chip, many more neurons can be preformed.
60
CHAPTER 6
STOCHASTIC MOTOR DRIVE CONTROLLER
6.1 Introduction
The electrical motors convert electrical energy into mechanical energy and are
widely used in industrial applications such as fans, pumps, elevators, electric vehicle,
paper and textile mills and subway transportation, wind generation systems, servos and
robotics, computer peripherals, steel and cement mills, ship propulsion, etc [44]. These
applications range from very precise, high-performance position-controlled drives to
variable-speed drives and the power rating varies from a few watts to many thousands of
kilowatts [45]. Normally, the electrical motors are classified as DC motor and AC motor.
The DC motor use DC power supply as its energy source and thus is easy to get high
performance for variable speed applications with simple control algorithms. However, it
has the disadvantages of high cost, high rotor inertia and maintenance problems with
commutators and brushes. Nowadays, with the development of modern motor control
theory and digital controllers, the AC motor becomes more and more popular and
important.
Fig. 6.1 shows a general block diagram for the control of motor drives. Different
processes and loads determine the detailed control requirements. For example, position
Power
Source
Power
Electronic
Converter
Motor
Gating Signals
Sensors
Controller
Figure 6.1 General block diagram of motor drive control
61
Process /
Load
control is needed for elevator applications while speed control are required for electrical
vehicle applications.
The induction motor, particularly the cage type is most commonly used among all
types of ac machines in industry due to its advantages of cost, reliability and robustness.
Many control algorithms have been developed in the past. Fig. 6.2 shows a typical fieldoriented control scheme of the induction motor for variable-speed applications. Compared
with the traditional scalar control techniques which is simple to implement but has the
inherent coupling effect that gives sluggish response and causes instability problems, the
vector control technique shown in the following figure which was introduced in the
beginning of 1970s provides the solution to these problems and demonstrates that an
induction motor can be controlled like a separately excited dc motor.
The implementation of these complicated control algorithms of the induction is
always a challenging task and almost impossible for analog controllers. Todays digital
Induction
Motor
AC
Currents
voltages
3 2
SPWM
v dss
r r
Flux Controller
Speed Controller
+
-
ids
iqs
+
+
-
Te
Current Controller
v ds
Current Controller
v qs
cos e
sin e
vqss
i dss
iqss
VR
ESTIMATOR
iqs
VR 1
ids
idss
r cos e sin e Te
iqss
Figure 6.2 Block diagram of field oriented controlled induction motor drive showing
FGPA based torque and flux estimator
62
controllers provide the possibility to implement these complex control functions with fast
response speed. This chapter presents the implementation and results of a high
performance induction motor drive controller using FPGA and stochastic arithmetic.
Section 6.2 presents the stochastic speed controller analysis. Section 6.3 presents two
methods to estimate the feedback signals of an induction motor. One applies stochastic
arithmetic to replace the traditional math operations and the other applies the stochastic
neural network structure. Section 6.4 shows the system design of the proposed stochastic
motor drive controller. Section 6.5 presents the verification using simulation, hardware-inthe-loop and experimental results. Section 6.6 concludes this chapter.
6.2 Stochastic speed controller analysis

PI controllers are the most commonly used controllers among motor drive control
applications. Fig. 6.3 shows the system diagram of the proposed stochastic PI controller
applied to the speed control of induction motor drives. The speed controller is either in
saturation mode or linear mode, which is assumed to be stable. It is desired to characterize
the domain of attraction when the system is saturated. The particular goal is to find a
mathematical relationship that defines the range of the two input signals r* and T L for
which the system is stable, i.e., lim e(t ) = 0 . Fast sampling is assumed here, so that the
t
analog analysis in this section is valid for the digital PI controllers. The analysis is focused
on the Proposed Scheme I. The analyses for Proposed Schemes II and III are much more
difficult and remain to be developed.
r +
TL
Stochastic
uout
1
e Antio-Windup uin Imax
+KT
Imax
- PI Controller
JS+ B
I, II, III
- Imax uin Imax
uin
u out = I max
uin > Imax
- I
max uin < Imax
Figure 6.3 Block diagram of proposed anti-windup PI speed controller
63
The variable-speed motor drive in Fig. 6.2 may be modeled as a first-order system
since fast current control is assumed. The speed-control system therefore is written as
1
r =
r +
T
KT
u out L
J
J
where, referring to Fig. 6.3, m =
(6.1)
J
. From Fig. 6.3 the output of the PI controller uin is
B
represented by
u in = K p e +
(6.2)
By applying the method introduced in [33], a characterization of the domain for the
attraction of Proposed Scheme I can be derived as following. First, recognize that
e = r* r . It follows using (6.2) that
e=
KT
T
1
uout + r* + L
J
m
J
(6.3)
From Table. 4.1, = 0 , and hence u in = K p e + C , where C is a constant and is

the value of the integral state when saturation occurs. Now, consider the Lyapunov
function,
V (e ) =
1 2
e
2
(6.4)
Then, in order to ensure stability, V (e) 0 must be satisfied. Differentiating (6.5)

yields,
.
V (e) = e e =
e2
1
KT
T
K
1
1
T
uoute + r*e + L e = e2 T I max sgn(uin )e + e r* + L (6.6)
J
J
m
m
J
J
m
Hence, it is desired that
1
1
K
T
V ( e) = e
e T I max sgn( K p e + C ) + r* + L
J
J
m
m
Assume C << K p e . Then (6.7) is satisfied if
64
(6.7)
KT
K
1 * TL
1
I max
e + T I max
r +
J
J m
J
m
(6.8)
Equation (6.8) is valid only when the system is saturated. To characterize e when
the system is saturated, one can first characterize e when the system is linear (unsaturated);
all other values of e will then correspond to saturation. If the system is linear, then
u in = K p e + => K p e + I max =>
( I max + )
(I )
e max
Kp
Kp
(6.9)
and hence in the saturation region,

e>
( I max C )
(I + C )
and e < max
Kp
Kp
(6.10)
where the constant integral state C is determined by the load torque and time instant
when saturation occurs.
The final characterization for the domain of attraction, obtained using (6.8) and
(6.10), is
1 ( I max + C ) K T
1 * TL
1
I max
r +
m
Kp
m
J m
J
(I C ) KT
+
max
I
J max
K
p
(6.11)
6.3 Stochastic estimator design

The feedback signals including torque, flux and unit vectors are important for
motor drives and normally required by the control systems. The processing and estimation
of these signals are complex and occupy large digital resources of the digital controller.
This problem either prevents dedicated control algorithms for high performance or results
in high cost. In this section, stochastic arithmetic principles are introduced to solve this
problem and two different approaches are presented. The first method replaces the
traditional math operators with stochastic operators to save digital resources. The second
method applies stochastic neural network to estimate these feedback signals and has the
advantages of fast parallel computation, immunity from input harmonic ripple and fault
tolerance characteristics due to distributed neural network intelligence [37].
65
6.3.1 Torque and flux estimation using stochastic arithmetic
The estimation of torque and flux is normally obtained from the induction motors
voltage and current signals. (6.12) shows the traditional mathematic method for the torque
and flux estimation from the voltage and current information.
v dss = 2 / 3v a 1 / 3(vb + vc ), v qss = 1 / 3 (vb vc )
idss = 2 / 3ia 1 / 3(ib + ic ), iqss = 1 / 3 (ib ic )
dss = (v dss Rs idss )dt , qss = (v qss Rs iqss )dt

Te = 3P / 4( dss iqss qss idss )
(6.12)
where v a , vb and v c are the phase voltages of the induction motor. ia , ib and ic are the
phase currents of the motor. Stationary frame d-q transformation is applied to the formula.
dss and qss are the flux components of the induction machine. Te is the electric torque of
the induction machine.
Compared to the current DSP-based torque and flux estimators [46-48], the
proposed stochastic approach provides a low cost, high performance and high flexibility
solution. The stochastic arithmetic has a number of benefits compared with the normal
arithmetic operations and can be implemented using FPGA devices easily. The stochastic
estimator and controller will save computation hardware significantly with some extent of
fault tolerance. The hardware implementation is simple especially for complicated
applications and the performance is stable and robust. In addition, the designer could make
the trade off between computation time and accuracy without hardware changes. The
accuracy of the results depends on the clock rate of FPGA device. The stochastic
implementation of torque and flux estimation using FPGA provides a low cost, faster and
easier approach for induction machines to derive the feedback signals for high performance
control and monitoring purpose.
Based on the stochastic arithmetic introduced in Chapter 3, the algorithm of the
stochastic flux and torque estimation is shown in Fig 6.4. The idea is to integrate the
stochastic arithmetic to (6.12) and thus simplify the digital circuits in the implementation
via FPGA. First, the currents and voltages are converted into the stationary d-q frame; and
66
va
vb
vc
ia
ib
ic
ADC
ADC
ADC
ADC
ADC
ADC
2 1
vdss = va (vb +vc )
3 3
1
vqss =
(vb vc )
3
vdss
vqss
s
s
2 1
ds
i = ia (ib + ic )
3 3
s
1
qs
s
iqs =
(ib ic )
3
s
ds
Stochastic
arithmetic
vdss Rs iqss
vqss Rs idss
Randomization
Stochastic Torque
estimator
Stochastic
integrator
Stochastic
integrator
dss
qss
Stochastic flux
estimator
Adjust
gain
Adjust
gain
Randomization
Stochastic arithmetic
3P
(
4
s
ds
i qss
s
qs
i dss )
qss dss
Derandomization
Te
Figure 6.4 The simplified block diagram of stochastic based torque and flux estimator
67
these signals are then normalized and transformed to the stochastic representation.
Stochastic signed representation is employed in which the input data are limited to the
range of [-1,1], and the relation between input x and the probability p is X = 2 p 1 . With
the one-bus stochastic pulse streams as the inputs, the stochastic subtraction and
integration with simple architectures replace the normal subtraction and integration. The
integration result, which has been automatically converted to the real number, is the output
of flux with proper gain sets according to (6.12). The torque estimation is similar. The
mixed circuit structure of stochastic multiplication and subtraction is applied. A
derandomzation block, which transforms the stochastic pulse stream to the real number, is
required for the torque estimation that is different from the flux estimation.
Fig. 6.5 shows the digital implementation of the stochastic flux estimator. K1 is the
normalized gain to set the data to the range of [-1,1]. The randomization is achieved with
one pseudo random generator and one n-bit comparator. A gain of 0.5 is set for the signed
representation and it can be implemented by a shift operation in the FPGA device. The
logic circuits of stochastic signed subtraction and integration are also shown in Fig 6.5. K2
is the adjust gain which is corresponding to the input gain K1 and the clock rate of the
computation.
The same randomization structure is adopted in the digital implementation of the
stochastic torque estimator (Fig 6.6). The stochastic signed multiplication can be achieved
with an XNOR gate and the stochastic signed subtraction is consisted of two AND gates,
one OR gate and one NOT gate. The stochastic signed multiplication approach is proved as
the followings:
Let the two input variables be x and y. The output of multiplication is z. In the
signed representation,
x = 2 p x 1
y = 2py 1
z = 2 p z 1
(6.13)
Then the reverse of (6.13) is the following:
68
Input Adjust
Adjust
Input Data
Data
Data
Data to
to
[-1,1}
[-1,1}
Randomization
Randomization
Pout =
Stochastic
Stochastic
signed
signed
subtraction
subtraction
1 + X input
2
Stochastic
Stochastic
Integration
Integration
Recover Output
Output
Recover Data
gain
Data
gain
Comparator
0.5
A
A>B
B
vdss
i
s
ds
++
k1
Normalized
gain
D-flip-flop
s
ds
k1
Rs
D-flip-flop
Normalized
gain
++
k1
D-flip-flop
Normalized
gain
k1
Normalized
gain
0.5
Comparator
A
A>B
0.5
B
Comparator
A
A>B
1
Z
Rs
++
D-flip-fllop
0.5
Comparator
A
A>B
0.5
B
Comparator
A
A>B
1
Z
1
Z
dss
Up
Dow n
Up/Down
Counter
qs
s
qs
++
1
Z
K2
Adjustable
gain
Up
Up/Down
Dow n Counter
K2
qss
Adjustable
gain
Pseudo
Random
Stream
Engine
Figure 6.5 Digital implementation of stochastic flux estimator
69
Input Adjust
Adjust
Input Data
Data
Data
Data to
to
[-1,1}
[-1,1}
Stochastic
Stochastic
signed
signed
Multiplication
Multiplication
Randomization
Randomization
Pout =
1 + X input
2
Stochastic
Stochastic
signed
signed
subtraction
subtraction
Derandomization
Output
Derandomization
sample
difference
Output
between gain k2 and Data
Data
N-bit counter
Comparator
0.5
A
B
dss
Comparator
++
k1
k1
1/2
1
Z
Normalized gain
s
qs
A>B
Rs
++
Normalized gain
A>B
D-flip-flop
1/2
1
Z
B
Comparator
A
Clock
A>B
D-flip-flop
reset
N-bit
counter
qs
Te
Adjustablegain
k2
Normalized gain
Comparator
++
k2
Normalized gain
i dss
K2
1/2
1
Z
Rs
A
A>B
D-flip-flop
B
Comparator
++
1/2
1
Z
D-flip-fllop
A>B
B
Pseudo
Random
Stream
Engine
Figure 6.6 Digital implementation of stochastic torque estimator
70
px =
x +1
2
py =
y +1
2
pz =
z +1
2
(6.14)
The output of An XNOR gate states:

p z = p XNOR = p x p y + (1 p x ) (1 p y ) =
xy + x + y + 1 xy x y + 1 xy + 1
+
=
4
4
2
(6.15)
Compare (6.14) and (6.15), it is obvious that: z = x y

The stochastic signed multiplication and subtraction are connected in serial to
construct the equation of torque in (6.12). An N-bit counter is used for the
derandomization to calculate the probability of the bit '1' that appears in the stochastic
random pulses.
Generally, the stochastic arithmetic can reduce logic gates after randomization
since all inputs become one-bit stream and only one or two buses are needed for the
calculation, therefore, only limited logic gates are required for the mathematic calculations.
The random engine shown in Fig. 6.5 and Fig. 6.6 can be constructed using D-flip-flops.
6.3.2 stochastic neural network estimator
This section introduces the principle of estimation of torque, flux and unit vector.
In a vector-controlled induction motor drive system, the unit vector signals are also require
to be realized in real time for the DQ rotating frame. The unit vector could be calculated by
the following equations:
v dss = 2 / 3v a 1 / 3(vb + vc ), v qss = 1 / 3 (vb vc )

idss = 2 / 3ia 1 / 3(ib + ic ), iqss = 1 / 3 (ib ic )
dss = (v dss Rs idss )dt , qss = (v qss Rs iqss )dt

s
qm
= qss Lls iqss ,
s
dm
= dss Lls idss
71
qrs =
Lr s
L
s
qm Llr iqss , drs = r dm
Llr idss
Lm
Lm
Te = 3P / 4( dss iqss qss idss )
r = ( qrs ) 2 + ( drs ) 2
drs
cos e =
,
r
qrs
sin e =
r
(6.16)
where v a , vb and v c are the phase voltages of the induction motor, ia , ib and ic are the
phase currents of the motor, v dss and v qss are the stator voltages in d-q stationary frame, dss
s
s
and qm
are the airgap
and qss are the stator flux linkage in d-q stationary frame, dm
flux linkage in d-q stationary frame, drs and qrs are the rotor flux linkage in d-q
stationary frame, Te is the electric torque of the induction machine and cos e and sin e
are the unit vector.
Figure 6.7 presents a control structure for the digital realization of a field-oriented
induction motor. A stochastic neural network estimator is implemented to estimate the
feedback signals of the induction motor. They are integrated with traditional control blocks
including dq- transformation and a three-phase PWM generator to implement a variable
speed control.
The structure of the neural network estimation of induction motor's feedback
signals is derived based on [49] and shown in Fig. 6.8. The training of neural network is
using the back propagation method. The developed neural network estimator includes two
independent neural networks. The first one that estimates qrs and drs contains two-layers
with three neurons in the first layer and two neurons in the second layer. The second neural
network applies the results from the first one and estimates electric torque, total flux, cos e
and sin e . The stochastic neural network estimator is developed in Fig. 6.9. The stochastic
multiplication and stochastic tansig (Stan) activation function are introduced to replace the
traditional digital signed multiplication and look-up table based tansig activation function.
72
r
r
External Speed
Command
r +
i ds
Flux Controller i
PI
Speed
Controller
ds + -
vds
Current Controller
PI
qs
2 3
e
d - q
v qs
PI
as-bs-cs
va
PWM
Gate Signal
Generation
vb
vc
i qs
cos e
s
i ds
d - q
i qs
d - q
ids
s
iqs
sin e
r
Te
Stochastic
Neural
Network
Estimator
dss
v ds
qss
Stochastic vqss
Integration s
ids
ids
iqs
Figure 6.7 Proposed stochastic neural network estimator for field-oriented induction motor drive
73
iqs
Activation function
Tansig
W21
W22
Activation function
Activation function
qss
W11
W12
Activation function
Activation function
Purelin
Activation function
i qss
Tansig
qrs
Tansig
Purelin
Activation function
Activation function
Tansig
Tansig
Activation function
Tansig
sin e
Activation function
Purelin
Purelin
idss
Activation function
Activation function
dss
cos e
Tansig
drs
Activation function
Purelin
Activation function
B12
Tansig
Activation function
B11
Purelin
Tansig
B22
Activation function
Tansig
B21
Figure 6.8 Conventional approach of neural network estimator of the induction motor's feedback signals
74
Te
denotes stochastic signed multiplication
Stan
W12
idss
Derandomization
dss
W21
R
R
i qss
Stan
Stan
Activation function
Purelin
qrs
Activation function
R
Purelin
Stan
drs
Derandomization
qss
denotes stochastic approach of tansig
Derandomization
W11
W22
Stan
Stan
Stan
Activation function
Stan
Stan
Stan
Purelin
Activation function
Derandomization
R denotes randomization process
Purelin
Activation function
Purelin
Activation function
B12
R
B11
cose
sin e
Te
Purelin
B22
R
Stan
B21
Figure 6.9 Proposed stochastic ANN approach of neural network estimator of the induction motor's feedback signals
75
6.4 system design

Figure 6.10 presents a new control structure for the digital realization of a fieldoriented induction motor. The stochastic arithmetic is applied to the shaded control blocks
for efficient hardware implementation. A stochastic neural network estimator is
implemented to estimate the feedback signals of the induction motor. A novel stochastic PI
controller with anti-windup function is developed as a high performance speed controller
as descried in previous sections. Stochastic digital integrators are introduced to replace the
traditional digital integrators. They are integrated with traditional control blocks including
dq- transformation and a three-phase PWM generator to implement a variable speed

control.
The proposed control algorithms including the stochastic anti-windup PI control
and stochastic neural network estimation schemes were implemented by a Spartan-3 FPGA,
XC3S400, from Xilinx, Inc. The XC3S400 has around 400,000 logic gates, 896
configurable logic blocks (CLBs) and 264 input/output blocks (IOBs). The control IC
design is developed using ISE Foundation 7.1, from Xilinx, Inc. ISE supports VHDL
programming and schematic entry editor with design implementation software. Its timing
simulation software also provides an easy and fast solution for circuit problems during the
early design stage. The hardware realization is shown in Fig. 6.11.
The implementation consists of four circuit modules: a vector control loop,
feedback signal estimation, coordinator transformation and PWM control. In the vector
control loop, the speed and flux are decoupled and each has a cascaded control loop. The
flux controller and two current controllers use the same stochastic PI model with different
PI parameters. The stochastic anti-windup PI model is applied to improve the speed
performance. The estimation module generates signals including flux, torque and unit
vector. A stochastic integrator and stochastic neural network estimator are employed to
save digital resources. A pseudo random engine using linear feedback shift registers (LFSR)
is built to provide a uniformed random stream for these stochastic modules. All these five
stochastic models share one random engine.
76
r
r
External Speed
Command
+
-
ids
Flux Controller i
PI
Stochastic
Anti-windup
PI Controller
ds + -
I max
vds
Current Controller
PI
I max
qs
2 3
e
d - q
qs
PI
as-bs-cs
va
PWM
Gate Signal
Generation
vb
vc
iqs
cos e
ids
iqs
d - q
d - q
ids
s
iqs
sin e
r
Te
Stochastic
Neural
Network
Estimator
dss
vds
qss
Stochastic vqss
Integration s
ids
ids
iqs
Figure 6.10 Proposed control structure for field-oriented induction motor drive applying stochastic theory
77
iqs
COORDINATOR
TRANSFORMATION
VECTOR CONTROL LOOP

SPEED
REG
CURRENT
LIMITATION
REG
PI PARAMETERS
REG 1
UNIT
VECTOR
REG
Flux Controller
FLUX
COMMAN
D REG
Current Controller
ADDER
SATURATOR
ADDER
STOCHASTIC
INTEGRATOR
PULSE
COUNTER
ADDER
SATURATOR
STATIONARY FRAME
TO SYNCHRONOUSLY
ROTATING FRAME
TRANSFORMATION
VOLTAGE
LIMITATION
REG
PI PARAMETERS
REG4
SYNCHRONOUSLY
ROTATING FRAME TO
STATIONARY FRAME
TRANSFORMATION
Current Controller
ADDER
DEAD
TIME
REG
STOCHASTIC
INTEGRATOR
PI PARAMETERS
REG3
SPEED
COMMAND
REG
SWITCHING
FREQUENCY
CONSTANT
REG
MUTIPLITER
MUTIPLITER
ADDER
UNIT
VECTOR
REG
PI PARAMETERS
REG 2
PWM
CONTROL
2 PHASES
TO
3 PHASES
TRANSFORMATION
SINUSOIDAL
PWM
GENERATOR
MUTIPLITER
STOCHASTIC ANTI -WINDUP

PI CONTROLLER WITH SATURATOR
ADDER
ADDER
SATURATOR
STOCHASTIC
INTEGRATOR
LFSR PSEUDO RANDOM ENGINE

CURRENT
REG
( STATIONARY
FRAME )
FLUX
REG
UNIT
VECTOR
REG
STOCHASTIC
NEURAL
NETWORK
ESTIMATOR
TORQUE
REG
FEED- FORWARD
NEURAL NETWORK
PARAMETERS
REG
STATOR
FLUX REG
(STATIONARY
FRAME )
MUTIPLITER
STOCHASTIC
INTEGRATOR
ADDER
VOLTAGE
REG
( STATIONARY
FRAME )
3 PHASES
TO
2 PHASES
TRANSFORMATION
STATOR
RESISTANCE
REG
FEEDBACK SIGNAL
ESTIMATION
Figure 6.11 The hardware realization of proposed control algorithms using FPGA XC3S400
78
3-PHASE
CURRENT
REG
3-PHASE
VOLTAGE
REG
6- bit gate
control signal
FPGA Spartan -3 Board (XCS 200)

ids
r +
r
Stochastic
Anti-Windup
PI Controller
Imax
Flux and
current
Controller
iqs
Imax
vds
Current vqs
Controller
iqs
2 3
e
e
d -q
sine
as-bs-cs
va
PWM
Gate Signal
Generation
vb
vc
cose
s
16b
vds
ids
d -q
iqs
e
e
vqss i s
d - q 16b
ds
A
s
Unit
iq s
D
Vector 16b C
16 b
2
3 Voltages
as-bs-cs Currents
RTDS
16 b
Figure 6.12 Hardware-in-the loop test setup using FPGA and RTDS
79
d -q
r
Position
encoder
6.5 Verification
6.5.1 Hardware in to loop verification for stochastic speed controller
The proposed anti-windup PI speed controllers were applied to the speed control of
an induction motor drive using the hardware-in-the-loop test bench shown in Fig. 6.12.
The motor parameters are the presented in Appendix. The power components were
simulated using real time digital simulation (RTDS), while the proposed controller was
implemented with FPGA. The parameters of each PI controller were tuned using try and
see method to obtain a small settling time and a small maximum overshoot.
Fig. 6.13 shows the experimental results of the three proposed anti-windup PI
speed controllers and the conventional PI controller without anti-windup, respectively. A
step command of 1000 rpm was given and then reduced to 250 rpm. The developed torque
current command was limited to 2.21A. The proportional parameter Kp is 0.0132 and the
integration parameter Ki is 0.105. As shown in Fig. 6.13 (a), the lack of an anti-windup
mechanism led to the continuous increase of the integral output as long as the current
command was saturated, which resulted in a large overshoot (0.071) and a long settling
time (0.621s). As shown in Figs. 6.13 (b), 6.13 (c) and 6.13 (d), the proposed anti-windup
PI control algorithms were used to hold or reduce the integral state when saturation
occurred. The control parameters C, C1 and C2 were chosen to be 215, 215 and 214. The
results were that the controlled performances of the three proposed algorithms yielded
improved performance. In particular, the maximum overshoot of the three proposed
methods were, respectively, 3.9%, 3.3% and 2.9% while the settling times were,
respectively, 0.107s, 0.133s and 0.141s. From these results, none of these methods had
both the lowest maximum overshoot and the lowest settling time. Hence, it is not possible
to say that one method was clearly better than the others.
Fig. 6.14 shows that the performance of the proposed anti-windup PI controller I is
comparable to that of the traditional anti-windup PI controller shown in Fig. 4.5 (a).
Therefore the proposed algorithms maintain the high control performance of the
conventional anti-windup methods.
80
wr
wr_command
1250
Speed[rpm]
Speed[rpm]
1250
1000
750
500
wr
wr_command
1000
750
500
250
250
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
1.5
2.0
Time [sec]
(a) Traditional PI controller without anti-windup technique
3.5
4.0
4.5
5.0
wr
1250
wr_command
1000
Speed[rpm]
Speed[rpm]
3.0
(b) Stochastic anti-windup PI controller I
wr
1250
2.5
Time [sec]
750
500
250
wr_command
1000
750
500
250
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
1.5
Time [sec]
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time [sec]
(c) Stochastic anti-windup PI controller II
(d) Stochastic anti-windup PI controller III
Figure 6.13 HIL experimental results of step speed response of proposed controller and
conventional controllers
Maximum Overshot
3.9%
Tr=0.107s
1000
Speed[rpm]
Speed[rpm]
1250
750
500
1250 Maximum Overshot

1.5%
1000
Tr=0.121s
750
500
250
250
0
0.0
0
0.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6
0.0
1.8
0.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6
1.8
Time [sec]
Time [sec]
(a) Proposed stochastic anti-windup PI controller I (Fig. 3(d))
(b) conditional anti-windup PI controller (Fig. 3(a))
Figure 6.14 HIL experimental results of performance comparison of proposed anti-windup

controller and conventional anti-windup controllers
Table. 6.1 illustrates the digital resources used by the conventional and proposed
anti-windup PI controllers for the variable-speed motor drive applications The applied
81
FPGA chip is Spartan3 xc3s200 (Xilinx) and the used hardware language is VHDL
language (ISE 7.01). It shows that the proposed methods I, II and III, respectively, save
logic cells by 23.1%, 29.9% and 31.0%.
Table 6.1
Comparison of digital resources used by conventional and proposed antiwindup PI controllers

Spartan3 xc3s200
Conventional Anti-windup PI
Proposed Stochastic Anti-windup PI
Controllers
Controllers
Used Number of Slices Types
Used Number of Slices
Types
Condition
Backcalculation
Hybrid
100
107
I
II
69
75
121
III
93
6.5.2 Verification of estimators

6.5.2.1 Simulation and Experimental Results of proposed torque and flux estimator
6.5.2.1.1 Simulation diagram and results using Matlab/Simulink
The proposed stochastic based torque and flux estimator is first verified using
Matlab/Simulink. The parameters used in the Simulink model are the same as shown in the
Appendix. Fig. 6.15 presents the Matlab/Simlink model for the induction motor fieldoriented control scheme with stochastic estimator. The top part includes the math model of
an induction motor and its related vector-control algorithm. The details of the stochastic
based flux and torque estimator is presented in the down part of Fig. 6.15.
The Signal Processing Blockset in the Simulink is used to build the logic gates
circuits as illustrated in Fig 6.5 and Fig 6.6. The simulation results of the stochastic
stationary flux estimation and the traditional method are compared (Fig 6.16). The X-axis
represents the d part component of the flux and the Y-axis represents the q part component
of the flux. In a period, the two components make a circle as shown in the figure. The
results of the two methods are similar, however, the stochastic-FPGA has the advantages
of low cost and easy implementation.
82
vao*
Vao*
Van
Vbo*
Vbn
Vco*
Vcn
van*
Id
vbo*
vco*
wr_cmd
wr*
control
Command
vbn*
out_Te
sin
PWM converter
Iq
cos
vds
out_wr
we
cos(wet)
Tl
sin(theta)
ib
ic
2_3
out_idr
vqs
sin(wet)
ia
ids
out_ids
vcn*
cos(theta)
iqs
out_iqs
vqs
vds
TL
Ian*
out_iqr
Induction Motor d-q- model
Icn*
abc-Syn
van*
theta
vdss
vdss
vbn*
Current and wr
controller
vcn*
Iqss
Subsystem3
we
wr
Idss
Ibn*
fdss
flux_d
idss
fqss
vqss
vqss
flux_q
torque
compare
Subsystem2
te
iqss
Subsystem
1
fdss
-K-
In1Out1
Gain8
-K-
vdss
Out1
In1Out1
In2
Rs
-K-
Gain4
Gain3
In1Out1
signed_sub
In1Out1
integral
-K-
In1Out1
-KGain6
signedadd
In1Out2
In1Out1
3
te
deran
observer
Out1
NOT
In2
In1
Out1
In1Out1
In2
Rs
In1Out1
In1
random7
In1Out1
Gain5
Gain7
Out1
In2
-K-
random3
iqss
4
In1
random6
Gain1
Multiplication
Gain9
random2
vqss
Out1
In2
In1
Gain2
random1
idss
In1
random5
In1Out1
signed_sub1
In1Out1
Multiplication1
NOT1
Gain10
integral1
random8
2
random4
fqss
Figure 6.15 Matlab/Simulink Model for the field-oriented control motor and estimator
Fig 6.18 presents the simulation results of the torque estimation with different step
time, and Fig. 6.17 presents the maximum estimation error with different step time. It can
be seen that the performance of the proposed method is improved at higher clock rate. This
is due to the statistical theory: more samples make the result more accurate. Therefore, as
the clock rate increases, the estimated probability comes to be closer to the real probability
value and thus reduces the error. From the simulation, when the clock reaches 100MHZ
83
FLUX Estimation
0.6
data1
data2
0.5
0.4
0.3
0.2
FLUX qs
0.1
0
-0.1
DSP Calculated
FLUX
-0.2
-0.3
-0.4
-0.5 Stochastic Calculated
Flux
-0.6
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Flux ds
Figure 6.16 Flux estimation and comparison vs. the traditional method
0.22
0.2
0.18
average error (N*m)
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02 -6
10
10
-7
time (s)
10
-8
Figure 6.17 The torque estimation error versus FPGA clock rate
84
Torque (N*m)
Step Time t =
2
1
0
-1
DSP Estimated
Torque
Stochastic Estimated
Torque
-2
-3
Torque (N*m)
106
0.05
0.1
0.15
0.2
0.25
Time (s)
0.3
0.35
0.4
0.45
0.5
0.35
0.4
0.45
0.5
0.35
0.4
0.45
0.5
(a)
7
Step Time t = 10
2
1
0
-1
-2
-3
0
DSP Estimated
Torque
Torque
0.05
0.1
0.15
0.2
0.25
0.3
Time (s)
(b)
Torque (N*m)
3
2
8
Step Time t = 10
1
0
-1
-2
-3
0
DSP Estimated
Torque
Torque
0.05
0.1
0.15
0.2
0.25
0.3
Time (s)
(c)
Figure 6.18 Comparison between stochastic and DSP torque estimation with different
clock steps
clock (step time 108 ), the estimation performance should satisfy the industry requirements.
In addition, the commercialized FPGA chips today normally support several hundreds
MHZ clock rate.
85
6.5.2.1.2 Experiment setup and results
The experimental setup is shown in Fig. 6.19. The PC has been installed dSPACE
to achieve vector control for the machine. The FPGA board EPF10K70RC240-4
(ALTERA) is used to implement torque and flux estimation. The results is plotted in PC
through I/O module.
PC (dSPACE1103)
Inverter Module
I/O Module
1 hp Induction Machine
FPGA Board
Sensors
Figure 6.19 The experimental setup
The stochastic arithmetic is implemented using the FPGA board. VHDL is

employed to implement the process of flux and torque estimation showed in Fig. 6.5 and
Fig. 6.6 by generating random number series, performing stochastic arithmetic and finally
transforming the stochastic calculation result back from the normal data. Fig. 6.20 shows
the simulation results of the flux estimation from maxplusII using VHDL. rn1, rn2 and rn3 are
the three pseudo random engines. The random engine is normally designed via pseudo
random number theory that is able to generate similar random numbers. These random
streams perform like true random number with a relatively long period and could be
recognized as the same statistic characteristics with the true random numbers in normal
86
Figure 6.20 Maxplus II VHDL simulation of dss = (v dss Rs idss )dt and
qss = (vqss Rs iqss )dt
conditions [7]. Data_ina and data_inb represent two normalized voltage and current signals.
Data_o is the output from the stochastic integrator. Data of Fig. 6.20 is the one bit
stochastic output of the calculation. b1 is the stochastic representation of voltage signal
while b2 is the stochastic representation of current signal. b3 is the stochastic representation
of value 0.5 which is used for the addition and subtraction calculation. The reset is the
control signal that starts the calculation.
The results from the FPGA device are plotted in the PC through I/O module. The
comparison between FPGA (using VHDL and stochastic arithmetic) and DSP (using
digital signal processor and traditional method) is shown in Fig. 6.21. The results are
similar, however the VHDL provides more advantages in the design process and design
cost. The accuracy of the VHDL results depends on the bits representing the incoming
data. 8-bits is used in current stage. In the future, it may be replaced by 12-bits or 16-bits
data representations, the results therefore can be further improved.
87
Flux Estimation
0.6
DSP Calculated
Flux
data 1
data 2
0.4
Stochastic Calculated
Flux
Flux qs
0.2
0
-0.2
-0.4
0
Flux ds
-0.2
-0.4
0.4
0.2
0.6
(a) Flux estimation

2
Torque (N * m)
1.5
Stochastic Estimated Torque
1
0.5
DSP Estimated
Torque
0
-0.5
-1
0.05
0.1
0.15 Time (s) 0.2
0.25
0.3
0.35
0.4
(b) Torque estimation

Figure 6.21 Experimental result of the stochastic-FPGA (VHDL coded) and DSP
88
6.5.2.2 Verification of stochastic neural network estimator
After the control was implemented by FPGA, a hardware-in-the-loop (HIL) test

setup was built in the laboratory to test the control performance. In HIL test setup, the
developed FPGA controller is physically integrated with an induction motor drive
simulated using the RTDS simulator, to test the control performance in real time. The
advantages of using HIL platform for the proposed controller are:
Reducing development time, as the controller is designed and tested at the same
time.
Developing and testing of the controller in the absence of a real plant to avoid the
unnecessary losses resulted by any bugs in the control.
Realistic selection of sampling time and integration time step by interacted with the
simulated system.
The use of HIL technologies to design and test control systems is growing recently
[50-54]. Currently there are several kinds of real-time simulation platforms [55-60] in
academia and industry. The RTDS is selected in this research due to its super computation
capability and availability in Florida State University. The RTDS is a commercial digital
power system simulator capable of continuous real time operation. It performs
electromagnetic transient power system simulations with a typical time-step of 50
microseconds utilizing a combination of custom software and advanced DSP hardware
[58]. Currently, 14 RTDS racks are installed at center for advanced power systems (CAPS)
which can simulate any major electrical power system component including power
electronics and complex control systems. More than 300 digital and analog I/O channels
provide sufficient capability to incorporate external hardware into the real-time simulation.
The test setup is shown in Fig. 6.22. The voltage, current and speed signals of an
one hp induction machine (see Appendix) are generated by RTDS and sent to the FPGA
board through A/D converters. The FPGA board provides gating signals to control the
inverter. Since RTDS runs at time step of 50 us, it is impossible to identify the PWM
gating signals that has a switching frequency higher than 1 kHz. A GPC card is installed
between RTDS and FPGA to allow PWM signals up to 50 kHz. The inverter is simulated
89
Gating
Signals
FPGA Spartan-3 Board (XC3S400)
GPC
Card
PWM
Control
Feedback
Signal
Estimation
DQ
Transformation
Vector
Control Loop
A/D
A/D
Rotor
Speed
Three
Phase
Voltage
DC Source
Three
Phase
Current
Small Time Step Model
Large Time Step Model
RTDS
Figure 6.22 Hardware-in-the-loop test setup using FPGA and RTDS
90
in RTDS with small time step of 2 us. The motor runs at 50 us time step and the FPGA
uses a 50 MHz oscillator.
Fig. 6.23 presents the torque estimation performance of proposed stochastic neural
network estimator obtained from HIL platform. Fig. 6.24 presents the flux estimation
performance of proposed stochastic neural network estimator obtained from HIL platform.
Fig. 6.25 and Fig. 6.26 present the unit vector estimation performance of proposed
stochastic neural network estimator obtained from HIL platform. Comparing with the
actual feedback signals, the estimated torque, flux, cosine wave and sine wave follow the
desired value with acceptable errors. The developed torque current command is limited to
2.21A.
6.6 Conclusion
An FPGA-based control IC for the field-oriented control of an induction motor
drive has been proposed in this chapter. The most important difference from previous
proposed motor drive control ICs is that it is based on stochastic arithmetic to implement
neural network algorithm and digital PI algorithm with anti-windup function. These
advanced algorithms need much silicon area and are normally hard to be achieved in the
motor control IC design. The main advantage of the proposed method is that the required
digital resources for these algorithms are significantly reduced and the whole control
2
1.5
torque (Nm)
Stochastic neural network

estimated Torque
Actual Torque
1
0.5
0
-0.5
0
0.05
0.1
0.15
0.2
0.25 0.3
time (s)
0.35
0.4
0.45
0.5
Figure 6.23 HIL results of NN estimator performance for the induction motors torque
91
0.8
flux (Wb)
0.6

estimated Flux
0.4
Actual Flux
0.2
0
0
0.05
0.1
0.15
0.25 0.3
time (s)
0.2
0.35
0.4
0.45
0.5
Figure 6.24 HIL results of NN estimator performance for the induction motors flux
1.5
cosine
1
0.5
0

estimated cos(e )
Actual cos(e )
-0.5
-1
0
0.05 0.1
0.15 0.2
0.25 0.3
time (s)
0.35
0.4
0.45
0.5
Figure 6.25 HIL results of NN estimator performance of unit vector: cosine wave
92
1.5
1

estimated sin ( e )
sine
0.5
0
-0.5
-1
0
Actual sin ( e )
0.05
0.1
0.15
0.2
0.25 0.3
time (s)
0.35
0.4
0.45
0.5
Figure 6.26 HIL results of NN estimator performance of unit vector: sine wave
algorithm can be implemented into a low complexity inexpensive FPGA chip. This
approach simultaneously exploits the high-speed of hardware implemented complex
algorithms and the capabilities of traditional control algorithms. The proposed control IC is
verified using an FPGA XC3S400. Due to the advantages of debugging, design period and
real time testing, a hardware-in-the-loop (HIL) test platform using Real Time Digital
Simulator (RTDS) is built in the laboratory and the HIL experimental results show that the
proposed FPGA-based control IC can achieve the high performance of adjustable speed
induction motor drives. Given that a low-cost and high-performance implementation can
be achieved, it is believed that such control IC will be extended to many other industry
applications involving complex algorithms.
93
CHAPTER 7
STOCHASTIC NEURAL NETWORK WIND SPEED
ESTIMATOR
The proposed stochastic neural network controller presents a low-cost and highperformance hardware implementation of neural network applications. Besides the motor
drive controller, this proposed neural network control Integrated Circuits (IC) could also be
extended to many other industry applications involving neural network algorithms. This
chapter will present another example of this stochastic neural network structure that works
as a wind speed estimator for a variable speed wind turbine system.
7.1 Introduction of sensorless small wind turbine generation systems

Today, wind power has met a strong growth and becomes an important component
in the world energy market. The capital cost of small wind turbine electrical generation
systems is continuous to decrease with the improvements of manufacturing techniques and
thus the small wind turbine system becomes a very competitive nonpolluting renewable
energy source. Compared with the traditional constant rotational speed wind energy
generation system, the variable rotational speed wind energy generation system provides
higher power efficiency, has a larger wind speed range and even improves the quality of
produced electrical power. However, the control algorithms of variable speed wind turbine
systems are more complicated and thus require more powerful digital controllers.
Fig. 7.1 describes a small variable-speed wind generation system where the
maximum wind power extraction control strategy is applied. To achieve variable speed
control and maximum power output generation, the turbine rotor speed should be
controlled at maximum power coefficient point. In conventional strategies, the wind
velocity is measured to derive the demand shaft speed to control the generator speed. To
94
Diodes
Rectifier
wr
Power
Vb
Vc
Ib
Ic
pulses
Pulse
Tt
wind
IGBT Inverter
PMSG
Turbine
3- Phase load
Power
wr*
wr
ANN estimator
PI
Figure 7.1 Small Wind Turbine System

provide the adequate information of the wind velocity, many anemometers at some
distance away from and surrounding the wind turbine are required to set up. These devices
increase the cost and reduce the reliability of the overall system. Recently the mechanical
sensorless peak power tracking control method has been reported in the literature and can
be summarized into two approaches. The first one is proposed by Bhowmik [61] to use
power coefficient polynomial to estimate wind velocity. The second method has been
reported by Tan [62] and Bose [49] by applying a 2-D look-up table of power coefficient
and power-mapping method to estimate the wind velocity directly or indirectly. In the 1st
method, an iterative algorithm is employed to determine the polynomial roots of power
coefficient online. Since the polynomial of power coefficient may be derived at 7th order
[63], real-time calculation of the polynomial roots will result in complex and timeconsuming calculation, hence reducing system performance. The mapping-power
technique may occupy a lot of memory space. If the memory space is saved by reducing
the size of look-up table, the control accuracy will be affected. Another issue with powermapping method is only the sub-optimum solution can be achieved due to the control delay
caused by inherent slow searching mechanism.
95
In this chapter, artificial neural network (ANN) principles are applied to implement
a novel wind velocity estimator. The proposed stochastic neural network structure is also
introduced to the FPGA implementation of designed wind speed estimator. By employing
this FPGA based stochastic neural network estimator, highly precise and fast calculation
may be instantly implemented with several stored weight and bias vectors, therefore the
complicated algorithm involving the time-consuming calculation is achieved in a simple
and cheap way without losing accuracy.
7.2 Design of the ANN wind velocity estimator

The operation principle of a wind turbine energy generation system and the neural
network wind speed estimation has been described in [64-65]. This section will briefly
introduce the design process of the wind speed neural network estimator.
7.2.1 Principle of sensorless small wind turbine system
The wind power generated by a wind turbine is inherently dependent on the wind
speed. The following equation gives the dependence of the power generated by the wind
turbine system. The output mechanical torque of the wind turbine and the tip speed ratio
is expressed as follows.
Pm =
1
C p ( )Vw3
2
rm r
Vw
(7.1)
where Pm is output mechanical power of the wind turbine, is air density, Cp is the power
coefficient, is wind turbine rotor swept area, Vw is wind velocity, rm is radius of the rotor,
r is rotor speed of the turbine and generator, and is called as tip speed ratio.
The power coefficient and tip speed ratio is normally featured by the manufacture
and performs as a non-linear function. Fig. 7.2 shows a typical power coefficient curve
with tip speed ratio. Based on (7.1) and Fig. 7.2, the wind turbine output power can be
derived as a function of wind velocity and turbine rotor speed as shown in Fig. 7.3. This
figure implies the rotor speed corresponding to a certain wind velocity for the maximum
output power. So the maximum mechanical power tracking control is achieved by
96
0 .4
0 .3 5
power coefficient Cp
0 .3
0 .2 5
0 .2
0 .1 5
0 .1
0 .0 5
0
-0 .0 5
4
5
6
T ip s p e e d ra tio
10
Figure 7.2 Power coefficient vs speed ratio

controlling the generator rotor speed to be the optimum speed profile corresponding to the
actual wind velocity. Therefore, wind velocity must be known first.
10000
Wind Turbine Power
8000
6000
15
4000
2000
10
0
5
-2000
0
10
20
30
40
50
60
70
80
Wind
Speed
Rotor Speed Wr (rad/s)
Figure 7.3 Wind Turbine Power Curves vs rotor speed and wind velocity
97
7.2.2 Neural network estimation principle

The artificial neural networks (ANNs) are based on the model of the human brain
and contain artificial neurons. These neurons may use differentiable transfer function to
generate their output. The ANNs do not need to analyze the mathematical model of the
system and are capable of learning the desired mapping between the inputs and outputs
data of the system. The ANNs are the approximation of the transfer function of the system
and hence required full range of the data. Normally the ANNs could solve many problems
with the same architecture, as the ANNs have no relation with the system model.
A neuron contains four components: Inputs, Weighted summer and bias, Activation
Function and Outputs as shown in Fig. 7.4. The input signal X1, X2, X3 Xn are
normally continuous signals. These signals flow through the weights and then accumulate
together. The summed signal then flows to the output through the activation function
which normally is non-linear.
Most common transfer functions the neurons uses are log-sigmoid transfer
function, tan-sigmoid transfer function and the linear transfer function. The first two
functions generate outputs between 0 and 1 as the neurons net input goes from negative to
positive infinity. For a multilayer network system, if the last layer has sigmoid neurons,
then the output are limited to a small range, so if a large dynamic range of output data are
required, the linear output neurons are used to get any value.
Figure 7.4 A typical structure of artificial neuron
98
PWM
RECTIFIER
Wind
Turbine
Model
Wind Speed
Estimated
Wind Speed
Wr
PWM
INVERTER
Power
UTILITY
Grid
NN Based
Wind Speed
Estimator
Figure 7.5 Wind turbine model with NN wind speed estimator

Feed-forward networks are the most common neural network structure and often
have one or more hidden layers of sigmoid neurons and an output layer of linear neurons
are then followed. Multiple layers of neurons with nonlinear transfer functions provide the
network the ability to learn nonlinear and linear relationships between input and output
vectors. The output will have a large range of values based on the linear output layer.
The wind speed estimation algorithm is based on formula (7.1). (7.1) is a high order
non-linear equation and so is very hard to reverse the equation to get the wind velocity
based on the rotor speed and wind turbine power. However, feed-forward neural network
algorithms are applied here to solve this problem. From Fig 7.5 that implicates the wind
turbine system, both the rotor speed Wr and the wind turbine power Pm could be obtained
through the simulated system. With these two inputs, the feed-forward neural network will
provide the ability to reverse the formula (7.1) and then get the estimated wind speed.
Fig. 7.6 shows the neural network structure for the wind speed estimation. It is a
two-layer neural network. The wind rotor speed and the power are the input and the wind
speed is the target. The network uses the tan-sigmoid neurons for the first layer to perform
the non-linear part of the system and the second layer is a linear neuron which will provide
a dynamic range of output. The feedback loop will adjust the weights and biases of the
neural network to reduce the estimation error.
99
Layer 1 using Tan-sigmoid

Layer 2 using pure-line
Figure 7.6 Neural Network Structure of the wind speed estimator
7.2.3 Neural Network Training Procedure

The neural network is trained by a back-propagation training algorithm which was
first proposed by Rumelhard, Hinton and Williams in 1986. A two-layer neural network
structure is used. The first layer is the tan-sigmoid with 5 neurons and the second layer is
the purelin layer with one neuron.
With the equation introduced above, the proposed training scheme for neural
network of estimating wind velocity Vw is shown in Fig. 7.7. In this scheme, (7.1) is
employed to yield sample data set to train the neural network. 100 of the rotor speed r is
averagely sampled during 10~100 rad/sec, while 100 of wind velocity Vw is averagely
100
(7.1)
Pm =
Vw
Pm
1
C p ( )V w3
2
Pm
Vw
ANN
Figure 7.7 Proposed training scheme for neural network of estimating wind velocity
sampled during 3~10 m/sec. Combining the above sample data, 10,000 data pairs {r(i),
Vw(j) | i=1,100, j=1,100} can be arranged. With the sample data pairs {r(i), Vw(j)},
10,000 data of mechanical power {Pm (i, j)| i=1,100, j=1,100}may be obtained from
(7.1). The rotor speed and power data are combined as new 10,000 data pairs (r(i), Pm(i,
j) | i=1,100, j=1,100) which are used as input sample data, while the wind velocity
sample data may be extended as 10,000 date set {Vw(i, j) | i=1,100, j=1,100}with
Vw(i, j)= Vw(i) which are used as target data to train the neural network. In order to obtain
fast convergent training results, zero power points (singular points) in the sample sets
should be removed. Hence, the sample elements should be less than 10,000. Then, inputtarget pairs are used to train a two-layer network as shown in Fig. 7.8 which is configured
with five tan-sigmoid neurons in the hidden layer, and one linear neuron in the output
layer. Table 7.1 shows the training result of the corresponding weights and biases. The
number of rows and columns are all decided by the neural network structure. Tansig
activation is applied to perform the non-linear factor.
101
W1
W2
Activation function
Tansig
Activation function
Tansig
Wr
Pm
Activation function
Activation function
Tansig
Purelin
Vw
Activation function
Tansig
Activation function
Tansig
B1
B2
Figure 7.8 Wind velocity estimation ANN with five tan-sigmoid neurons and one linear
neuron
Table 7.1 weights and biases of the neural network wind speed estimator
0.0002146
0.70319
0.09362
1.7864
- 0.75037
0
.
055186
W 1 = - 0.08856
- 0.00008172 B1 = - 1.0267
0.66107
0.010959
0.00004973
7
0.74697
0.055117
- 1.7228
W 2 = [-331.7105 - 16.4371 - 548.4516 44.3448 - 16.4045]

B 2 = [- 243.9466 ]
After 500 training epochs, the sum-squared error E is less than 1.510-4. Sum
squared errors of 500 epochs are shown in Fig. 7.9 [64]. The small error shows the
accuracy of the wind speed neural network estimator. Since the traning data covered most
possible data range, so this training result should be effictive for a wide range of conditions.
102
10
10
Training-Blue
10
10
10
10
10
Performance is 0.00014953, Goal is 0
-1
-2
-3
-4
50
100
150
200
250
500 Epochs
300
350
400
450
500
Figure 7.9 Training error of the proposed neural network

7.2.4 Simulation results of the proposed neural network wind speed estimator
To verify the performance of the neural network based wind speed estimator,
Matlab/Simulink is used to simulate the whole system. Based on the wind turbine
characteristics, the model of the wind generating system is built to verify the estimator.
1
Wr_wind
K*u
K*u
W1
Matrix
Gain1
2
Pm
netsum1
logsig
netsum2
1
purelin
-CB1
-CConstant2
Figure 7.10 Matlab/Simulink model of the wind speed estimator
103
Wspeed_es
Figure 7.11 The wind turbine system with the NN wind estimator
12
Estimated Wind speed
11
Wind Speed (m/s)
10
Wind Speed
10
20
30
40
50
60
70
t(s)
Figure 7.12 Matlab/ Simulink Simulation result: Estimated wind speed vs actual wind
speed
Fig 7.10 is the Matlab/Simulink implementation of the wind speed estimator, all the
weights are coming form the training results of the neural network toolbox based on the
104
computer-calculated data. Figure 7.11 presents the simulation of the wind turbine system.
The mathematic wind turbine model and many approximations are used.
Fig 7.12 shows the simulation results of the wind speed estimation using Matlab/
Simulink.
7.2.5 Hardware-in-the-loop experiment verification of the proposed neural network
wind speed estimator using RTDS and dSPACE
The real time digital simulation (RTDS) is powerful for simulate the whole wind
turbine system and also provide the certainty of the implementation of the NN based wind
speed estimator in real cases. Fig 7.13 presents the wind turbine system used in this
experimental verification and Fig 7.14 shows the hardware-in-the-loop simulation using
RTDS to provide the same characters of the system shown in Fig 7.13. The wind turbine
model is simulated in RTDS using its mathematical model to perform the characteristic of
wind energy generation system. The wind speed estimator is implemented using dSPACE
as shown in Fig. 7.15.
Induction
Machine
PWM
RECTIFIER
PWM
INVERTER
UTILITY
GRID
Vdc
Wr
Controller
Iqs*
Power
Tracking
Control
Wr* +
Current
Controller
Vdc*
+
Ids*=0
PI
Controller
Figure 7.13 A voltage-feed double PWM conveter wind generation system based on
variable speed cage machine
105
20 hp
Dynamometer
Torque
controller
RTDS Implementation
Wind Turbine Model
Vw
TM =
Inverter
hardware
TM *
IM
1
rmC p ( )V2
2
Mximum Power Tracking Control
TM
Cp ()
rm r
V
1:2.5
GM
r*
Load
controller
Converter
hardware
Grid connect
Figure 7.14 Experimental verification of the above system using RTDS
106
Figure 7.15 dSPACE implementation of NN based wind speed estimator

The wind data generating and the neural network wind speed estimation algorithms
are developed using Matlab/Simulink through the PC. After the software simulation, the
algorithms will be compiled and downloaded to the dSPACE microcontroller. The
dSPACE has the hardware connections with the RTDS system. The RTDS will read the
wind speed from the dSPACE and provide the power and the wind turbine rotor speed to
the dSPACE which will then calculate the estimated wind speed based on the NN wind
estimation block built in the dSPACE. The estimated wind speed will be used to feed
forward and provide the maximum power generating and control the rotor speed to run the
wind turbine system.
The system is running on the 20hp dynamometer model and all the outputs are
captured by RTDS. The wind model provides different kinds of wind curves to test the NN
based wind speed estimator. The experimental results are recorded by RTDS and then
translated into matlab to plot all the figures.
107
Figure 7.16 Hardware verfication of the NN based wind speed estimator

The first experiment is to use the simple sine wave to simulate the wind speed. The
result is shown in Fig 7.17. The estimator could trace the sine wave quite well, but there is
still some noises exist which could be solved by a low pass filter. Also, because of the
digital implementation, delay also exists.
Fig. 7.18 shows the refined NN based estimators result with the low pass filter
which comes to much close to the wind speed trace.
Fig 7.19 shows the common wind speed model which is based on [65] and also
simulated and generated by dSPACE. The estimated wind speed is actually used to control
the maximum power tracking and control the wind turbine rotor speed. The wind model
here used varies in a limited bandwidth. Fig. 7.20 shows the result for a fast changing
wind. Since the neural network used to train the estimator is a static network which means
that it could not provide the dynamic characteristics of the system and also will lose its
ability to estimate the speed when the wind changes dramatically.
108
12
wind speed
10
actual wind
speed
8
estimated
wind speed
---------0
20
40 t(s) 60
80
100
120
Figure 7.17 A simple sine wave to simulate the effect of the wind speed estimator
12
11
estimated wind speed
with low pass filter
wind speed
10
----------
8
actual wind
7 speed
20
40 t(s) 60
80
100
120
Figure 7.18 A simple sine wave to simulate the effect of the wind speed estimator with low
pass filter
109
11
actual wind
speed
wind speed
10
estiamted
wind speed
--------
10
20 t(s) 30
40
50
60
Figure 7.19 Wind speed vs estiamted wind speed using RTDS
11
10
actual
wind speed
wind speed
estimated wind speed

with low pass filter
-------------
10
20
t(s) 30
40
50
Figure 7.20 fast wind speed vs estimated wind speed using RTDS
110
60
W1
Randomization
W2
Randomization
Stan
Stan
Wr
Randomization
Activation function
Stan
Pm
Purelin
Randomization
Stan
Stan
B2
B1
Derandomization
Randomization
Derandomization
Figure 7.21 Stochastic ANN wind velocity estimator
111
Vw
7.3 Stochastic Neural Network wind speed estimator design

To implement the neural network structure in Fig 7.8, stochastic multiplication and
stochastic activation function are applied to replace the corresponding operations. As
shown in Fig 7.21, the stochastic multiplication and stochastic approach of tansig
activation function are applied to replace the traditional digital implementation of
multiplication and tansig function. Randomization processes are also accepted for the
inputs and weights.
7.4 Experimental Results using FPGA and RTDS

The experimental setup of the wind turbine system using a real-time digital
simulator (RTDS) is shown in Fig. 7.22 [66]. A 20 hp dynamometer is used to emulate the
wind turbine. The entire turbine model has been implemented in RTDS, which provides
the shaft torque request TS-0 and the generator speed request G-0 to the dynamometergenerator set. An FPGA device Sparatan3-XC3S200 from Xilinx implements the ANNbased wind-speed estimation. A 50 MHz oscillator is applied to the FPGA, so the time step
for the stochastic stream is 0.02 s. Around 20,000 bits are used for each derandomization
process in this application. The calculation time of each point is 0.4 ms, so the output
sample rate to estimate wind speed can reach as high as 2.5 KHz. The experimental results
of wind speed estimation of a random varied wind speed profile are shown in Fig 7.23 (a)
and (b). Fig 7.23 (a) is derived by using the developed stochastic-ANN-FPGA
implementation and (b) by using a traditional look-up table-ANN-FPGA implementation.
The stochastic estimator uses 16-bit resolution for randomization, multiplication and tansig
of N = 4. The traditional estimator has 256 points in the look-up table for the tansig
function, and each data point in the loop-up table has a 10-bit resolution. The digital source
utilization of the FPGA device is 75% using the stochastic method and 98% with the lookup table. Although the stochastic method introduces approximation errors, the stochastic
method is more accurate than the look-up table, as shown in Fig. 7.23, because the similar
digital resource utilization limits the size of the look-up table and the resolution for the
traditional method. However, a higher resolution can be achieved for the stochastic method
112
Wind velocity
profile v
W- P
Neural
Network
Estimator
Generator shaft
power PS
1 + s
E
Estimated wind
velocity vE
8.4
94.25
RTDS
Generator
speed
Speed
control
mode
CAPS utility
feed 208 V
Torque
control
mode
request G-0
0
Emulator shaft
Aerodynamic
torque request
torque
2
x
request
TS-0
TA
.
+
K
0.4
10
TJ
r rm
C
(
)
JT
=
T
Turbine and
vW
gear friction
0
T
Turbine F
s
and gear
Turbine
1 + sJ
kF
inerti
speed r
a
Source
selector
Low power HIL test setup
Turbine
speed r
vE-NNE
Bandwidth
limit
1
FPGA
7.9
Gear
box
ratio
0.4
M
Shaft
torque
G
TS
Generator shaft speed G
Figure 7.22 Experimental setup for a varied-speed wind turbine system using a hardware-in-loop real-time digital simulation
113
and a fast clock rate provides a small approximation error.
7.5 Conclusion
The proposed stochastic-ANN-FPGA implementation for wind energy generation
14
12
10
8
6
4
2
0
-2
Windvelocity (m/s)
Windvelocity(m/s)
applications saves digital logic resources and enables large parallel neural network
Stochastic NN
Wind Velocity
Estimation
Actual Wind
Velocity
14
12
10
8
6
4
2
0
-2
Estimation
Error
5
6
Time(s)
(a)
10
10
Traditional NN
Wind Velocity
Estimation (8-bit)
Actual Wind Estimation
Velocity
Error
5
6
Time(s)
(b)
Figure 7.23 (a) Experimental result of wind speed estimation using stochastic-ANN-FPGA
implementation; (b) Experimental result of wind speed estimation using look-up table ANN-FPGA implementation
114
structures to be implemented in low-cost FPGA devices with high-fault tolerance

capability. The experimental results of a speed-sensorless control of a small wind-turbine
system confirmed the proposed design method. The computation error of the stochastic
method has been analyzed. We have also considered the trade-off between the accuracy
and the number of employed digital logical elements. Hardware-in-loop experimental test
flat is applied in this application which perform a fast and economical method to test the
proposed controller and estimator.
115
CHAPTER 8
CONCLUSION
8.1 Summary
The conclusions of this dissertation work can be summarized as follows:
1. The stochastic arithmetic is applied to reduce the involved digital computation
elements for FPGA implementation of complex power electronics control
algorithms. The performances are verified using FGPA based controllers.
2. New stochastic anti-windup PI controllers are proposed and implemented. The
proposed methods have advantages of large dynamic range, easy digital design,
minimization of the scale of digital circuits, reconfigurability, and direct
hardware implementation.
3. An
alternative
stochastic
neural
network
structure
and
its
digital
implementation are proposed. The stochastic arithmetic including the

multiplication and activation function is described along with error analysis for
the hardware implementation of neural network.
4. The stochastic anti-windup PI controllers are designed as the speed controllers
of an induction motor to improve the speed control performance. The
performance is successfully verified using control in the loop test setup.
5. A stochastic neural network estimator is proposed and implemented for a feedforward neural network to estimate the feedback signals in an induction motor
drive. This approach has considered the trade off between the accuracy and the
number of employed digital logical elements since the stochastic arithmetic
unavoidably introduces noise and variance compared to the traditional math
operations. The performance is successfully verified using control in the loop
test setup.
6. A novel hardware controller for motor drives is proposed and developed using
FPGA. The proposed stochastic based algorithm enhances the arithmetic
116
operations of FPGA, saves digital resources, and allows the neural network
algorithms and classical control algorithms easily interfaced and implemented
into a single low complexity inexpensive FPGA. The performance is
successfully verified using control in the loop test setup.
7. The proposed stochastic neural network structure is applied to a neural-network
based wind-speed sensorless control of a small wind turbine system. A low cost
FPGA wind speed estimator is developed and implemented. It provides an
unique approach for the real-time hardware solutions of ANN controller in
power electronics field. The neural network wind speed estimator has been
verified successfully with wind turbine test bed installed in the CAPS (Center
for Advanced Power Systems).
8.2 Future work

8.2.1 Implement real experimentation verification of stochastic motor drive controller
The proposed stochastic speed controller and stochastic NN estimator have been
verified using control-in-the-loop test setup. The real experimentation will be achieved in
the future, which will provide a more powerful conclusion.
Out
SET
CLR
SET
CLR
SET
CLR
SET
CLR
SET
CLR
SET
CLR
reset
clk
Figure 8.1 Hardware Implementation of a single bit pseudo-random engine

8.2.2 Improve random engine design
117
The design of random engine will significantly affect the accuracy of control
algorithms. The adopted implementation for the n-bit pseudo random engine contains a set
of n linear feedback shift registers (LFSR). Each LFSR acts as a pseudo-random bit
generator and its digital circuit is redrawn in Fig. 8.1 where a number of D-type flip-flops
are cascaded and a feedback loop is closed through an XOR gate. The length of each onebit pattern needs to be even otherwise the probability of 0.5 required for each bit stream is
impossible to obtain. The total length will be maximized if the only common integer
divisor of the bit patterns is number two since the length of the combined N-bit pattern is
the smallest common multiple of the lengths of the individual bit patterns.
The future research will develop new methods to achieve effective randomization
using a minimum number of digital gates. This could be implemented by changing the
seeds of the pseudo random engine during the operation time. A small pseudo random
sequence is applied to build up the time varying seeds of the random engine. Since each
pair of seeds could generate one different pattern of pseudo random streams, this method
could increase the repeating cycle without adding a lot of LFSRs.
8.2.3 Implement ANN digital hardware with on-line training characteristics
The dissertation demonstrated the validity of FPGA implementation of stochastic
feed forward ANN after it is trained off-line. NN has better adaptability to a nonlinear
operating condition if it can be trained on line since the weights and biases of ANN are
adaptively modified during the operating process. The most popular training algorithm for
a feed forward ANN is back-propagation due to its stability, robustness, and efficiency.
The back propagation algorithm involves a great deal of multiplication and derivation so it
results in a rather complex circuitry to be implemented in real time. The all-digital
implementation takes up much larger chip areas than the analog ones. However, there are
no ideal analog circuits to implement the back-propagation or its modified versions, which
are gradient decent algorithms. The reason for this is that these gradient descent algorithms
are very sensitive to the nonlinearities and offsets, which are common characteristics of
analog multipliers and adders. The stochastic technology can simplify the traditional
arithmetic operation to provide an effective approach to achieve all-digital implementation
118
of on-line training as well as the network with smaller chip areas. Therefore a relatively
simple and inexpensive ANN hardware solution may be produced.
119
APPENDIX A
MOTOR NOMENCLATURE AND PARAMETERS
Nomenclature:
B Friction coefficient
J Moment of inertia of total system
K Proportional gain of the PI controller
K T Torque constant
Integral state of the PI controller
T I Integral time constant of the PI controller
T L Load Torque
m Mechanical time constant (= J/B)
u out Output of the Limiter
u in Input of the Limiter
wr Motor rotor speed
wr* Motor rotor speed command
Parameters of induction motor:
Power Rating
1 hp
Number of poles
2
Stator resistance
2.99
3.46 10 3 H
Stator inductance
Rotor resistance
1.58
1.37 10 3 H
Rotor inductance
Magnetizing inductance 60.41 10 3 H
Base frequency
60 Hz
Moment of inertia
0.0012kg m 2
120
APPENDIX B
WIND TURBINE PARAMETERS
Power
5.9 kW
Wind velocity range 315 m/s
Total inertia JT
7 kgm2
Air density
1.2 kg/m3
Blade radius rM
2m
Total friction kF 0.1 Nms/rad
Tip speed ratio opt 6.72 for maximum power
Reduction gear
1:2.5
121
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BIOGRAPHICAL SKETCH
Da Zhang was born in Xian, China in October 1979. He received his bachelor
degree majored in Electrical Engineering from Zhejiang University in Hangzhou, China in
July 2001. He received his Master of Science degree in the Department of Electrical and
Computer Engineering at the Florida State University in August 2003. He began his Ph.D
study in the Department of Electrical and Computer Engineering at the Florida State
University in September 2003. He is a research assistant at the Center for Advanced Power
Systems (CAPS) of Florida State University. His research is specialized in the fields of
Power Electronics and digital control.
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The Florida State University

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A Stochastic Approach to Digital Control Design

THE FLORIDA STATE UNIVERSITY

A STOCHASTIC APPROACH TO DIGITAL CONTROL

A Dissertation submitted to the

1.1 Background ...........................................................................................

2. STATE-OF-ART FPGA CONTROLLERS REVIEW...................................

2.1 Hybrid DSP and FPGA based digital controller ...................................

3. STOCHASTIC ARITHMETIC ......................................................................

4. NEW STOCHASTIC ANTI-WINDUP PI CONTROLLERS........................

4.1 Introduction of stochastic integrator .....................................................

5. STOCHASTIC NEURAL NETWORK..........................................................

6. STOCHASTIC MOTOR DRIVE CONTROLLER........................................

7.1 Introduction to sensorless small wind turbine generation system ........

8.1 Summary ...............................................................................................

A MOTOR NOMENCLATURE AND PARAMETERS.........................

BIOGRAPHICAL SKETCH ..............................................................................

Table 6.1: Comparison of digital resources used by conventional and proposed

Figure 2.1: Generalized concept of a DSP/FPGA digital controller ...................

Figure 2.2: A concurrent and simple FPGA controller of an AC/DC converter

Figure 2.3: The induction motor field-oriented control scheme implemented

Figure 3.1: The randomization process of an input variable ..............................

Figure 3.2: Single bit random engines ................................................................

Figure 3.3: An improved 8-bit random engine ...................................................

Figure 3.5: Simulation diagram and result of stochastic signed multiplication ..

Figure 3.6: Stochastic unsigned addition ............................................................

Figure 3.7: Stochastic unsigned square ...............................................................

Figure 3.8: Stochastic signed subtraction ...........................................................

Figure 3.9: Stochastic integrator .........................................................................

Figure 3.10: Stochastic square root calculation ..................................................

Figure 3.11: Stochastic unsigned division ..........................................................

Figure 3.12: Stochastic signed division ..............................................................

Figure 3.13: Stochastic unsigned division without saturation problem ..............

Figure 3.14: Feedback loop based derandomizer ...............................................

Figure 4.1: Structure of a proportional-integral (PI) controller ...........................

Figure 4.2: Block diagram of digital integrator ...................................................

Figure 4.4: Randomization process and an example ...........................................

Figure 4.5: Traditional anti-windup strategies for digital integrator ...................

Figure 4.6: Proposed stochastic anti-windup integration scheme (I)...................

Figure 4.7: Proposed stochastic anti-windup integration scheme (II) .................

Figure 4.8: Proposed stochastic anti-windup integration scheme (III) ................

Figure 4.9: Digital design scheme of stochastic anti-windup PI controller I.......

Figure 4.10: Digital design scheme of stochastic anti-windup PI controller II ...

Figure 4.11: Digital design scheme of stochastic anti-windup PI controller III..

Figure 5.1: (a) Biological neuron (b) Artificial neuron .......................................

Figure 5.2: An example of stochastic unsigned multiplication............................

Figure 5.3: Probability distribution of N and maximum......................................

Figure 5.4: Stochastic approach of tansig activation function.............................

Figure 5.5: Approximation: F(x)= (

Figure 5.6: Approximation maximum error (G(x)-F(x)) with N.

Figure 5.7: Tansig( 2 N 1 x) vs. stan(N,x) ..............................................................

Figure 5.8: Digital design scheme of stochastic tan-sigmoid activation function

Figure 5.9: FPGA implementation result.............................................................

Figure 5.10: Stansig Approximation error with increased N...............................

Figure 6.1: General block diagram of motor drive control..................................

Figure 6.3: Block diagram of proposed anti-windup PI speed controller............

Figure 6.5: Digital implementation of stochastic flux estimator .........................

Figure 6.6: Digital implementation of stochastic torque estimator......................

Figure 6.7: Proposed stochastic neural network estimator for field-oriented

Figure 6.8: Conventional approach of neural network estimator of the induction

Figure 6.9: Proposed stochastic ANN approach of neural network estimator

Figure 6.10: Proposed control structure for field-oriented induction motor