procedure, section III discusses the results obtained from the

Design of a Two-Stage Miller Operational

Transconductance Amplifier (OTA)
Using gm/ID Approach
Cristine Jin D. Estrada, Maria Christina D. Jimenez, and Mark Anthony G. Manabat
AbstractDesigning analog CMOS circuits is a demanding
task now that there is a necessity for lower power consumption,
higher speed and other design objectives, and these objectives are
being limited by the specifications and variables. This papers
presents a design of a CMOS Miller operational
transconductance amplifier (OTA) using (gm/ID) methodology.
This eliminates the need for complex device models as in
traditional designs. The method was applied successfully to the
design of a low-power Miller OTA. Main goal of the proponents
was to design a low-power two-stage Miller OTA which was
achieved as presented in the results and analysis.
Index Termsanalog
amplifiers

I.

integrated

circuits,

operational

INTRODUCTION

circuit design is a demanding and challenging

task due to complex relations among the design
objectives like lower power consumption and higher
speed, specifications (bandwidth, gain, etc.) and design
variables such as transistor sizes and bias voltages and
currents. Traditional design methodologies for analog CMOS
integrated circuits are inaccurate for submicron devices where
several iterations are performed. Most of the analog circuit
designs are done manually with the help of simulation
programs [1].
The objective of analog circuit design is to transform
specifications into circuits that satisfy these specifications. It
has been observed from previous studies that when MOS
transistors operate in the weak inversion region, least power
consumption is obtained but because of good values desire for
speed and power, moderate inversion region is often used [1]
[2].
In this report, a CMOS Miller operational transconductance
amplifier (OTA) was designed using transconductance and dc
drain current ratio (gm/ID) methodology in the characterization
of the transistors and simulated using Synopsys cdesigner.
Simulations of circuits are presented in the next sections and
are performed several times until the design objectives are
achieved. The additional goals were: least power consumption,
fastest amplifier, and highest figure-of-merit (FoM). This
report presents the design methodologies, optimization efforts,
results, analysis of results and conclusions.
The report is organized as follows: section I discusses the
introduction and objectives, section II discusses the (gm/ID)
methodology for the characterization, and the design of twostage Miller OTA which uses a gain-bandwidth driven

methodologies presented in the previous sections, section IV

discusses the analysis of the results and section V discusses
the conclusions and ideas.
II.

CIRCUIT MODELING AND DEVICE CHARACTERIZATION

In order for the designer/s to develop a methodology,

characterize the device, model and layout analog circuit, the
designer/s must understand the process and concepts.
Fig. 1 shows the steps of the design process. The first step
is characterization where specifications for the design are
considered and transistor dimensions are calculated.
Simulations of the circuit are performed to determine the
performance of the circuit, several simulations are expected to
achieve the desired parameters and objectives. If the design
objectives are satisfied, last step is lay outing of the design.

NALOG

Design
Specifications

Understanding the
concepts surrounding the
design

Initialization of parameters and

variables

Evaluation and simulation

NO
Are parameters and specifications
achieved?

YES

END
Fig. 1. Steps of the design process

A. gm/ID Based Design Methodology

The gm/ID methodology is used for the characterization of the
transistors. This methodology considers the relationship

between the ratio of transconductance g m and dc drain current

ID. Using gm/ID as the main design parameter, the operating
region of the transistors and its dimensions (width and length)
can be determined.
The choice of gm/ID is based on its relevance for the
following reasons:
It is strongly related to the performance of analog
circuits;
It gives an indication of the device operation
region;
It provides a simple way to determine the
transistors dimensions.
B. Applying the gm/ID Methodology in the Design of
a Miller OTA
In the creation of a two-stage Miller Operational
Transconductance Amplifier (OTA), the intended g m/ID
approach was applied. The schematics of the said amplifier is
shown in Fig. 2.

drain current in M1 and M6, depending on the set

target - low power consumption, high speed, or high
figure-of-merit (FoM).
The proponents chose a gain bandwidth of 10
MHz and a compensation capacitance of around 0.22
of that of the load capacitance CL which is 0.25 pF.

Cc 0.22C L 0.25 pF

(1)

Having set these values, the transconductances

in M6 and M1 can be determined by the relationship:

gm1=2 GBW C c =15.71 S (2)

C
gm6 =4 gm1 L =251.36 S (3)
Cc

( )

B. V*
The value of the voltage nearly close to V DSAT
or V* can be assigned in line with the aimed
transconductance. A high V* meant a large drain
current is intended to flow and vice versa. The basis
of a high V* and low V* is where the optimum
fT*gm/ID is located. Deviating from the optimum value
results to a high or low V*. Table II shows the
summary of the target V* for each transistor.
TABLE II
SUMMARY OF TARGET V* FOR EACH TRANSISTOR

Fig. 2. Two-stage Miller Operational Transconductance Amplifier (OTA)

Schematic

a. Design Specifications
The required design specifications are as follows and
summarized in Table 1.
TABLE I
SPECIFICATIONS

Parameter
Topology
Supply Voltage
Low Frequency Gain
Phase Margin
Load Capacitance

Target
Two-stage Miller OTA
3V
60 dB minimum
> 50
1 pF

SUMMARY

V* TO BE ASSUMED

M0
M1
M2
M3
M4
M5
M6
M7

HIGH
LOW
LOW
HIGH
HIGH
HIGH
LOW
HIGH

C. ID1 and ID6

In accordance to the transconductance of M1
and M6 obtained from (2) and (3), the drain currents
on the same transistors can be computed by taking the
relationship:

I D =0.5 gm V
b. Design phase 1: Initialization of Parameters and Variables
A. GBW, gm1, and gm6
Since the design specifications only declare
about the required supply voltage, low frequency
gain, phase margin and load capacitance, the
proponents have freedom in deciding what values
should be designated for the gain in the first and
second stage, gain bandwidth product (GBW),
compensation capacitor (Cc), transconductance and

(4)

Substituting the values for gm and V*, the

computed ID1 is 1.1 A and ID6 is 17.6 A.
c. Design phase 2: Sizing the CMOS (M1 and M6)
From the graph of V* vs ID/W for each transistor of lengths
0.35m, 0.5 m, 0.65 m, 0.8 m, 1 m, and 1.2 m, I D/W is
obtained from the allocated V*. Width is then computed using
the formula:

W=

ID
I D /W

M1
M2
M3
M4
M5
M6
M7

(5)

where ID is the computed value and I D/W is based from the

graph.
The length and the corresponding computed width, so as the
computed drain current acting as a current source, are then
substituted to a circuit with a voltage controlled voltage source
which purpose is to determine if the gain and drain current in
target is accomplished. This is done in the PMOS in the
common source and NMOS in the differential pair. In biasing
the transistor, also from the circuit with voltage controlled
voltage source (vcvs), it is also noted that the source voltage
to be reflected at the node at the drain is the desired output in
each stage.
d. Design phase 3: Sizing the Current Mirrors (M3, M4, M5,
M7 and M0)
The current mirrors are made in such a way that M3 and M4
have the same sizes and produce a current of 1.1 A. M0 and
M7 are sized with equal dimensions and the current flowing in
them is 17.6 A. If the length of the diode connected transistor
M0 is set to have the same length as that of M5, then the width
of M5 can be sized by a factor of 0.125 which is the ratio of
ID5 and ID0.
III. RESULTS
Table III and Table IV show the required bias points (V*),
currents and transconductances for each transistor.
Open loop gain and phase response plot using AC analysis
to determine the gain, GBW, and phase margin are shown in
Fig. 3a and Fig. 3b. Step response plot for unity gain
configuration using transient analysis to determine the settling
time and slew rate is shown in Fig. 4. Input common mode
range and DC offset to determine the range of input where the
transistors are still in target operating points and the input
required to have 1.5 V at the output is shown in Fig. 5. Lastly,
the output swing plot using transient analysis to determine the
maximum output swing where there is no clipping or
distortion and the corresponding input swing is shown in Fig.
6.
Summary of the obtained width and length for each
transistor is shown in Table V. Summary of the values
obtained from these plots are shown in Table VI.

LOW
LOW
HIGH
HIGH
HIGH
LOW
HIGH

140
140
200
200
200
140
200

86.5051
86.5051
-98.5500
-98.5500
106.357
140.250
135.183

TABLE IV
TRANSCONDUCTANCE AND DRAIN CURRENT
VALUES FOR EACH TRANSISTOR

M0
M1
M2
M3
M4
M5
M6
M7

TRANSCONDUCTANCE
(s)
240.973
13.7164
13.7164
12.04
12.04
22.3123
264.52
274.434

DRAIN
CURRENT (A)
15.6382
0.593269
0.593269
-0.593271
-0.593271
1.18653
-18.5494
18.5494

TABLE V
WIDTH AND LENGTH VALUES FOR EACH TRANSISTOR

M0
M1
M2
M3
M4
M5
M6
M7

WIDTH (m)
4.31
0.58
0.58
0.78
0.78
0.54
10.2
4.31

LENGTH (m)
1.2
1.2
1.2
1
1
1.2
1.2
1.2

TABLE VI
SUMMARY OF OUTPUT VALUES

Gain
GBW
Phase Margin
Settling Time
Slew Rate
Maximum Input
Maximum Output Swing
Power

70.4 dB
10 MHz
64.1
0.5 s
5.84 V/s
0.571857 mV
253 mV and 2.83 V
0.106122 mW

Fig. 3a. Open loop gain and phase response (AC) showing the gain and GBW
in dB

TABLE III
V* VALUES FOR EACH TRANSISTOR

SUMMARY

V* TO BE
ASSUMED

M0

HIGH

ASSUMED
V*
VALUES
(mV)
200

OBTAINED
V* VALUES
(mV)
129.792

Cpar
Co
FND
fp1

23.97 fF
1.02397 pF
26.8 MHz
1915.92 Hz

Fig. 3b. Open loop gain and phase response plot showing the phase margin

IV. ANALYSIS OF RESULTS

Fig. 4. Step response plot for unity gain configuration (transient) showing the
settling time

B. Discrepancies
There are discrepancies or problems that occurred during
the design process.
1. Given that the common source stage is the first to be
devised and then the differential pair, the gain significantly
dropped than what is expected when the differential pair is
connected to the input of the common source. To answer this
problem, the proponents resize the width of M6 to comply
with the output voltage of the differential pair.
2. Another problem encountered is when the current source
representing M0 and M7, and M5 were changed into current
mirrors, again, the gain dropped. And as a solution, the width
of the common source is resized.

Fig. 5. Plot showing the DC offset

Fig. 6. Plot showing the input swing using transient analysis where the
minimum input swing is obtained without clipping or distortion

Fig. 8. Plot showing the output swing using transient analysis where there is
no clipping and distortion
TABLE VII
POLES

Av2
Av1
Cx2

A. Results
Table V lists the transistor sizes. The generated results from
the gm/ID methodology are summarized in Table VI. And lastly,
Table VII shows the summary of the values necessary to
obtain the non-dominant pole and the first pole. With a target
of GBW of 10 MHz, the g m/ID methodology provided a power
consumption of 0.106122 mW. The gain is 70.4 dB and the
phase margin is 64.1 , both of which are higher than the
required minimum low frequency gain and phase margin,
respectively. The maximum sinusoidal input voltage of
0.571857 mV will produce a highest fidelity. The slew rate is a
measure of the transistors speed aside from the GBW. With a
slew rate of 5.84 V/s, it tells how fast the OTA can charge up
a load capacitor. The settling time is 0.5 s.

102
63.55
91.24 fF

C. Reasons
Looking deeper into the design, the gain is reduced because
of the loading effect. The loading effect will make the
impedance low. The gain of the differential stage is g mRD,
where RD is the sum of the channel resistances of one
differential pair and its corresponding PMOS load. If a
connection is to be done on its output, the tendency is that the
effective RD will be pulled down and likewise, the gain. A
possible solution on this matter is not by adjusting the width of
the common source, but the width of the current mirrors M3
and M4. If the widths of M3 and M4 are to be adjusted and
increased, then they will be more conductive and make the
node Vx2 a proper bias for the common source. This
discrepancy can be seen from the currents of M3 and M4
Table IV. Moving on, the lower current mirror is used to

provide bias currents to the differential pair and the common

source. In the differential pair, M5 provides the biasing
current. In DC condition, ID3 = ID4 = ID5/2, however, if input is
connected to the differential pair, then, theres a deviation
from this condition because M1 or M2 will conduct more
current than the other depending on the input. If there is a need
to increase the current on the common source, then, there is a
need to adjust the width of M5 in reference to M0, making the
width of M5 smaller than M0 so that current on the other side
is higher.

to design a low-power (0.106122 mW) two-stage Miller OTA

given the design objectives and specifications.
ACKNOWLEDGMENT
The proponents wish to thank the support of the student
assistants and faculty of the EEE Institute and PIIC.
REFERENCES
[1]

V. CONCLUSION
The analysis and design of a two-stage Miller operational
transconductance amplifier (OTA) were presented. The
relationship between the transconductance efficiency (gm/ID)
and ID/W enabled the proponents to size the transistors
considering the operation regions. The proponents were able

[2]

F. Silveira, D. Flandre, and P. G. A. Jespers, A gm/ID Based

Methodology for the Design of CMOS Analog Circuits and Its
Application to the Synthesis of a Silicon-on-Insulator Micropower
OTA, IEEE Journal of Solid State Circuit, vol. 31, pp. 1314-1319, Sept.
1996.
F. P. Cortes, and S. Bampi, Miller Ota Design Using A Design
Methodology Based on the gm/ID and early-voltage characteristics:
Design Considerations and Experimental Results.

*Design
can
be
ADW/DesignCaseStudy/Labs/mdjimenez/testbench2/

found

in