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Transformations

Acknowledgement:

Materials in this lecture are courtesy of the following sources and are used with permission.

Curt Schurgers

J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.

Prentice Hall/Pearson, 2003.

Layout 101

3-D Cross-Section

p-type substrate

VDD

n-type well

metal/pdiff

contact

SiO2

n+

SiO2

n+

p+

Wp

p+

p+

n+

Lp

N-channel MOSFET

VDD

P-channel MOSFET

IN

OUT

Wn

S

G

Circuit Representation

D

IN

GND

metal

OUT

S

L15: 6.111 Spring 2006

poly

n+

diff

p+

diff

Layout

D

G

contact

frommetal

to ndiff

Ln

between process and circuit designers)

Introductory Digital Systems Laboratory

Custom Design/Layout

5-1 Mux

g64

CARRYGEN

SUMSEL

node1

2-1 Mux

9-1 Mux

ck1

SUMGEN

+ LU

1000um

REG

9-1 Mux

a

sum

sumb

to Cache

s0

s1

LU : Logical

Unit

Multiplexers

Shifter

Adder stage 1

Adder stage 2

Wiring

Loopback Bus

Loopback Bus

Loopback Bus

Wiring

Itanium integer datapath

Courtesy Intel, as reprinted in Rabaey, et al. "Digital Integrated Circuits".

Bit slice 0

Bit slice 1

Sum Select

Bit slice 2

Bit slice 63

Adder stage 3

Hand crafting the layout to achieve maximum clock rates (> 1Ghz)

Exploits regularity in datapath structure to optimize interconnects

L15: 6.111 Spring 2006

Design Iteration

Design Capture

Pre-Layout

Pre-Layout

Simulation

Simulation

Behavioral

Verilog

Verilog(or

(orVHDL

VHDL))

Structural

Logic

LogicSynthesis

Synthesis

Floorplanning

Floorplanning

Post-Layout

Post-Layout

Simulation

Simulation

Circuit

Circuit

Extraction

Extraction

Placement

Placement

Physical

Routing

Routing

Tape-out

Clock Rates

L15: 6.111 Spring 2006

Power Supply Line (VDD)

Delay in (ns)!!

(from ST Microelectronics):

C = Load capacitance

T = input rise/fall time

Ground Supply Line (GND)

Each library cell (FF, NAND, NOR, INV, etc.) and the variations on size

(strength of the gate) is fully characterized across temperature, loading, etc.

L15: 6.111 Spring 2006

2-level metal technology

between rows of standard cells are needed

Width of the cell allowed to vary to accommodate complexity

Interconnect plays a significant role in speed of a digital circuit

L15: 6.111 Spring 2006

(the push button approach)

After

Synthesis

module adder64 (a, b, sum);

input [63:0] a, b;

output [63:0] sum;

assign sum = a + b;

endmodule

After Routing

After

Placement

Macro Modules

25632 (or 8192 bit) SRAM Generated by hard-macro module generator

multipliers, etc.) with a few lines of code

Verilog models for memories automatically generated

based on size

L15: 6.111 Spring 2006

Clock Distribution

Clock skew

D

copyright restrictions.

D

Variations along different paths arise

from:

Device: VT, W/L, etc.

Environment: VDD, C

Interconnect: dielectric thickness

variation

L15: 6.111 Spring 2006

copyright restrictions.

To VDD Grid

To VDD Grid

Ccoup

To VDD Grid

Receiver

Cint

Rd

Cd

Driver

GROUND GRID

Pad

Pad

to be less than the external source

Used with permission.

L15: 6.111 Spring 2006

10

Multiplication (Phase Locked Loop)

up

down

VCO

Divider

PFD

Loop filter

(a standard IP block in most ASIC flows)

Courtesy Michael Perrott. Used with permission.

L15: 6.111 Spring 2006

11

Scan Testing

...

0

1

ScanShift

shift out

0

1

CLK

ScanShift

shift in

ScanShift

shift in

into one giant shift register which can be loaded/

read-out bit serially. Test remaining (combinational)

logic by

(1) in test mode, shift in new values for all

register bits thus setting up the inputs to the

combinational logic

(2) clock the circuit once in normal mode, latching

the outputs of the combinational logic back into

the registers

(3) in test mode, shift out the values of all

register bits and compare against expected

results.

Clk

ScanShift

Vector Loaded

Primary

Inputs

Scan-Flops

Load/Unload Cycles

Load/Unload Cycles

Primary

Outputs

Normal System

L15: 6.111 Spring 2006

12

Behavioral Transformations

There are a large number of implementations of the same

functionality

These implementations present a different point in the

area-time-power design space

Behavioral transformations allow exploring the design

space a high-level

Optimization metrics:

power

2. Throughput or sample time TS

3. Latency: clock cycles between

the input and associated output

change

4. Power consumption

5. Energy of executing a task

6.

L15: 6.111 Spring 2006

area

time

13

Fixed-Coefficient Multiplication

Conventional Multiplication

Z=XY

Z7

X3 Y3

Z6

X3 Y2

X2 Y3

Z5

X3 Y1

X2 Y2

X1 Y3

Z4

X3

Y3

X3 Y0

X2 Y1

X1 Y2

X0 Y3

Z3

X2

Y2

X2 Y0

X1 Y1

X0 Y2

X1

Y1

X1 Y0

X0 Y1

X0

Y0

X0 Y0

Z2

Z1

Z0

Z = X (1001)2

Z7

Y = (1001)2 = 23 + 20

X3

Z6

X2

Z5

X1

Z4

X3

1

X3

X0

Z3

X1

0

X1

X0

1

X0

Z2

Z1

Z0

Z

<< 3

X2

0

X2

14

Canonical signed digit representation is used to increase the number of

zeros. It uses digits {-1, 0, 1} instead of only {0, 1}.

Iterative encoding: replace

string of consecutive 1s

1 1

2N-2 + + 21 + 20

0 0 -1

2N-1 - 20

01101111

-1

-1

-1

10010001

<< 7

<< 4

L15: 6.111 Spring 2006

15

Algebraic Transformations

Distributivity

Commutativity

A

A+B=B+A

(A + B) C = AB + BC

Common sub-expressions

Associativity

A

B

C

(A + B) + C = A + (B+C)

L15: 6.111 Spring 2006

16

A

FG

3 multipliers and 3 adders

1

distributivity

A

B D

FG

I

1

to 2 multipliers and 2 adders

17

Retiming is the action of moving delay around in the systems

Delays have to be moved from ALL inputs to ALL outputs or vice versa

D

D

D

D

D

Cutset retiming: A cutset intersects the edges, such that this would result in two disjoint

partitions of these edges being cut. To retime, delays are moved from the ingoing to the

outgoing edges or vice versa.

D

D

D

Benefits of retiming:

Modify critical path delay

Reduce total number of registers

18

x(n)

h(0)

h(1)

h(2)

Direct form

h(3)

i =0

y(n)

x(n)

(10) h(0)

associativity of

the addition

h(1)

h(2)

h(3)

Tclk = 22 ns

y(n)

retime

(4)

x(n)

h(0)

y(n)

h(1)

D

h(2)

D

h(3)

Transposed form

Tclk = 14 ns

Note: here we use a first cut analysis that assumes the delay of a chain of operators is the sum

of their individual delays. This is not accurate.

L15: 6.111 Spring 2006

19

(Pipelining = Adding Delays + Retiming)

Contrary to retiming,

pipelining adds extra registers

to the system

add input

registers

D

How to pipeline:

1. Add extra registers at

all inputs

2. Retime

retime

D

D

Introductory Digital Systems Laboratory

20

loop

unrolling

y(n)

x(n)

A

y(n)

x(n)

2D

Try pipelining

this structure

distributivity

this structure!

y(n)

x(n)

2D

D

A

associativity

y(n)

x(n)

y(n)

x(n)

A

retiming

2D

D

A

A2

L15: 6.111 Spring 2006

A2

precomputed

Introductory Digital Systems Laboratory

21

GATE

DRAIN

SOURCE

100

Tox

90

BODY

80

Leff

60

50

10000

40

1000

100

10

1000

500

250

130

65

32

Path Delay

1b unusable (variations)

Probability

Atoms

70

Temperature (C)

110

Due to

variations in:

Vdd, Vt, and

Temp

Delay

L15: 6.111 Spring 2006

Introductory Digital Systems Laboratory

22

(Matlab/Simulink to Silicon)

S reg

Mult1

Mac1

X reg

Add,

Sub,

Shift

Mult2

Mac2

(Courtesy of R. Brodersen. Used with permission.)

L15: 6.111 Spring 2006

23

Fingerprinting is a technique to deter people from illegally

redistributing legally obtained IP by enabling the author of the IP to

uniquely identify the original buyer of the resold copy.

The essence of the watermarking approach is to encode the author's

signature. The selection, encoding, and embedding of the signature

must result in minimal performance and storage overhead.

copyright restrictions.

copyright restrictions.

24

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