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Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Nathan Ickes
Rex Min
Yun Wu
Read-Write Memory
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
Non-Volatile
Read-Write
Memory
EPROM
Read-Only
Memory (ROM)
Mask-Programmed
E2PROM
FLASH
2L-K
AL-1
Storage Cell
Row Decode
AK
AK+1
Bit Line
Word Line
2L-K row
by
Mx2K column
cell array
M.2
Amplify swing to
rail-to-rail amplitude
Sense Amps/Driver
A0
AK-1
Column Decode
Input-Output
(M bits)
Register Memory
Negative latch Positive latch
D
0
D
1
Q
CLK
D Q
Q
0
QM
D Q
Clk
CLK
Works fine for small memory blocks (e.g., small register files)
Inefficient in area for large memories density is the key
metric in large memory circuits
BL
WL
VDD
M2
M5
Q
M1
BL
WL
WL
M4
Q
M6
M3
BL
Row Decoder
Address
Pins
Write enable
Chip Enable
Data
Pins
Sense Amps/Drivers
Read
Logic
Write enable
Output Enable
in
out
If enable=0
out = Z
If enable =1
out = in
Column Decoder
enable
Memory Matrix
Tri-state Driver
Address
Chip Enables E1
E2
MCM6264C
Write Enable W
Data
DQ[7:0]
Output Enable G
Memory matrix
256 rows
32 Column
DQ[7:0]
A2
A3
A4
A5
A7
A8
A9
A11
Row Decoder
On the inside:
E1
E2
W
G
(Image
by MIT
OCW.)
A0
A1
A6
A10
A12
Sense Amps/Drivers
Column Decoder
Address
E1
Access time (from enable low)
G
Bus enable time
Data
(Tristate)
Data Valid
Read cycle begins when all enable signals (E1, E2, G) are
active
Address
Address 2
Address 3
E1
G
Bus enable time
Data 1
Data
Data 3
Address
E1
Write pulse width
W
Data setup time
Data
E2 and G are held high
10
Read cycle
Clock/E1
G
W
Address
Data
Data read
Data can be
latched here
VCC
address are
Clock
stable for writes
Control
Prevents bus
(write, read, reset)
contention
Write data
Minimum clock period
Read data
is twice memory
Address
access time
FPGA
Ensures
ext_chip_enable
ext_write_enable
FSM
ext_output_enable
int_data
D
E2
E1
W
SRAM
G
Data[7:0]
ext_data
Address[12:0]
ext_address
11
Multi-Cycle Read/Write
(less aggressive, recommended timing)
clk
VDD
W_b
Control
(write, read, reset)
FSM
G_b
E2
E1
W
G
SRAM
data_oen
int_data
data_sample
write_data
read_data
address
address_load
Data[7:0]
ext_data
Address[12:0]
ext_address
write completes
read, address is stable
address/data stable
12
write completes
read, address is stable
address/data stable
13
1/4
2/4
14
write2: begin
next = write3;
data_oen_int =1;
end
write3: begin
next = IDLE;
data_oen_int = 0;
end
read1: begin
next = read2;
G_b_int = 0;
data_sample = 1;
end
read2: begin
next = read3;
end
read3: begin
next = IDLE;
end
default: next = IDLE;
endcase
end
endmodule
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15
Testing Memories
Approach
Device problems generally affect the entire chip, almost any test will
detect them
Writing (and reading back) many different data patterns can detect data
bus problems
Writing unique data to every location and then reading it back can detect
address bus problems
16
An Approach
Write 0 to location 0
Read location 0, compare value read with 0
Write 1 to location 1
Read location 1, compare value read with 1
Address
Data
Control
Write
Read
Write
Read
Write
Read
Write
2
Read
17
Write 0 to address 0
Write 1 to address 1
To normal
memory interface
write 8-LSBs of
address <counter>
to location specified
by address
<counter>
Increment counter
Comparator
Reset counter
Counter
Read address
<counter>
Report success
Compare data
read with 8-LSBs
of <counter>
Increment counter
SRAM
Does not
match?
Report failure
Data
Address
Control
Matched?
Enable
memory
test
18
Row Decoder
Address
Pins
Write
Logic
Memory
matrix
Data
Pins
Read
Logic
Sense Amps/Drivers
Column Decoder
Output Enable
long flow-through
combinational path creates
high CLK-Q delay
Write Enable
Chip Enable
R2
W3
R4
W5
CE
WE
CLK
Address
Data
L7: 6.111 Spring 2006
A1
A2
Q1
A3
Q2
D3
A4
A5
Q4
D5
19
ZBT (zero bus turnaround) memories change the rules for writes
On a write, data is set up after the clock edge
(so that it is read on the following edge)
Result: no wait states, higher memory throughput
R1
R2
W3
R4
W5
CE
WE
CLK
Address
Data
A1
A2
A3
Q1
Q2
Write to A3
requested
A4
D3
Data D3
loaded
A5
Q4
Write to A5
requested
D5
Data D5
loaded
20
Row Decoder
Address
Pins
ZBT
Write
Logic
Memory
matrix
Write Enable
Chip Enable
As an example, see
Data
Pins
Synchronous SRAM
Read
Logic
Sense Amps/Drivers
Column Decoder
Output Enable
pipelining
pipelining register
register
R1
R2
W3
R4
W5
CE
WE
CLK
Address
Data
L7: 6.111 Spring 2006
A1
A2
one-cycle
latency...
A3
Q1
A4
Q2
A5
D3
Q4
D5
(ZBT write to A5)
21
10 V
S
5V
0V
20 V
Avalanche injection
5V
S
5V
0V
2.5 V
Removing programming
voltage leaves charge trapped
[Rabaey03]
5V
Programming results in
higher V T .
EPROM Cell
Image removed due to
copyright restrictions.
22
Vcc (5V)
Data
Charge
pump
Chip Enable
Output Enable
Write Enable
L7: 6.111 Spring 2006
Programming
voltage (12V)
FSM
Introductory Digital Systems Laboratory
EPROM omits
FSM, charge
pump, and write
enable
23
DRAM uses
Special
Capacitor
Structures
BL
Write "1"
Read "1"
WL
M1
CS
GND
VDD
BL
CBL
VDD/2
sensing
VDD /2
[Rabaey03]
24
Row
Col
RAS
CAS
Data
WE
(Tristate)
RAS-before-CAS
for a read or write
CAS-before-RAS
for a refresh
25
Write Enable
Address[12:0]
Data[7:0]
~E1
~G
EPROM
[12:0]
to as memory
mapped peripherals
[12:0]
Referred
SRAM 2
Address[12:0]
Data[7:0]
~G
~W
~E1
SRAM 1
[12:0]
~G
~W
~E1
Maps
Address[12:0]
Data[7:0]
Memory Map
0xE000
0xDFFF
0xC000
0xBFFF
Y5
~G2B
~G2A
Bus Enable
SRAM 2
SRAM 1
Y6
G1
+5V
Y4
Y3
Y2
Y1
Y0
Data[7:0]
~G
~W
~E1
0xA000
0x9FFF
EPROM
Y7
0x2000
0x1FFF
0x0000
ADC
ADC
Introductory Digital Systems Laboratory
Address[2:0]
Data[7:0]
0xFFFF
138
15
14
13
[2:0]
Address[15:0]
Analog
Input
26
Non-Volatile Memory
Fast
Memory Internals
Has
Device details
Dont
27
28