L16: Power Dissipation in Digital Systems

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 1

 Problem #1: Power Dissipation/Heat

Sun’s
Surface
100000 10000
18KW
Rocket

Power Density (W/cm2)

10000 5KW
1.5KW Nozzle
1000
Power (Watts)

1000 500W Nuclear

Pentium® proc Reactor
100 100
286 486
10 8086 386
8085 8086
8080 10 4004 Hot Plate P6
8008 8008 8085 Pentium® proc
1 4004 386
286 486
8080
0.1 1
1971 1974 1978 1985 1992 2000 2004 2008 1970 1980 1990 2000 2010
Year
Year

Courtesy Intel (S. Borkar)

How do you cool these chips??

heat sink

chip

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 2

 Problem #2: Energy Consumption

The Energy Problem

7.5 cm3
AA battery
Alkaline:
~10,000J

What can One Joule

of energy do?
(Image by MIT OCW. Adapted from Jon
Eager, Gates Inc. , S. Watanabe, Sony Inc.) Mow your Operate a Send a 1
lawn for processor Megabyte
1 ms for ~ 7s file over
802.11b

No Moore’s law for batteries…

Today: Understand where power goes
and ways to manage it
Image by MIT OCW.

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 2

 Dynamic Energy Dissipation

Charging Discharging
VDD E0→1 = CLVDD2 VDD

iDD Ecap = 1/2CLVDD2 RP

RP
2 Ediss,RN =1/2CLVDD2
Ediss, RP = 1/2CLVDD
IN =0 IN =1

RN CL RN
CL

P = CL VDD2 fclk
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 3
 The Transition Activity Factor α0−>1

Current Next Output

Input Input Transition A
Z
00 00 1 −> 1 B

00 01 1 −> 1
00 10 1 −> 1 Assume inputs (A,B) arrive
00 11 1 −> 0
at f and are uniformly
01 00 1 −> 1
01 01 1 −> 1 distributed
01 10 1 −> 1 What is the average
01 11 1 −> 0 power dissipation?
10 00 1 −> 1
10 01 1 −> 1
1 −> 1
α0−>1 = 3/16
10 10
10 11 1 −> 0
11 00 0 −> 1
11 01 0 −> 1
11
11
10
11
0 −> 1
0 −> 0
P = α0−>1 CL VDD2 f
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 4
 Junction (Silicon) Temperature

Simple Scenario Realistic Scenario

TJ
Silicon
TC
Case
Silicon TS
Sink
Tj-Ta= RθJA PD
TA
RθJA is the thermal resistance TJ
between silicon and Ambient
PD RθJC
TJ TC
RθJA RθCS
PD
TS
TA RθSA

Tj= Ta + RθJA PD TA

Make this as low as possible

RθCA = RθCS + RθSA
is minimized by facilitating heat transfer
(bolt case to extended metal surface – heat sink)
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 5
 Intel Pentium 4 Thermal Guidelines

„ Pentium 4 @ 3.06 GHz dissipates 81.8W!

„ Maximum TC = 69 °C
„ RCA < 0.23 °C/W for 50 C ambient
„ Typical chips dissipate 0.5-1W (cheap
packages without forced air cooling)

Image by MIT OpenCourseWare. Image by MIT OpenCourseWare. Adapted

from Intel Pentium 4 documentation.
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 6
 Power Reduction Strategies

P = α0−>1 CL VDD2 f
„ Reduce Transition Activity or Switching
Events
„ Reduce Capacitance (e.g., keep wires
short)
„ Reduce Power Supply Voltage
„ Frequency is typically fixed by the
application, though this can be adjusted to
control power
Optimize at all levels of design hierarchy
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 7
 Clock Gating is a Good Idea!

Clock gating reduces activity Adder Off

and is the most common low-power
technique used today

Global Clock Adder Clock

+
Enable_Adder

Multiplier On

X
Multiplier Clock
Enable_Multiplier
100’s of different clocks in a microprocessor

Clock Gating Reduces Energy, does it reduce Power?

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 8
 Does your GHz Processor run at a GHz?

Processor

Chip
Thermal
Activity
Sensor
Control

ƒ Note that there is a difference between average and peak

power
ƒ On-chip thermal sensor (diode based), measures the silicon
temperature
ƒ If the silicon junction gets too hot (say 125 °C), then the
activity is reduced (e.g., reduce clock rate or use clock gating)
Use of Thermal Feedback
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 9
 Power Supply Resonance

Lboard Lpackage Rgrid

On-die
decap Switching
currents
Board decap
Can write a Virus to Activate
Power Supply Resonance!

Image removed due to copyright restrictions.

Image removed due to copyright restrictions.

Image removed due to copyright restrictions.

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 10

 Number Representation:
Two’s Complement vs. Sign Magnitude
Two’s complement Sign-Magnitude
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2
1101 0010

-4 1100 0011 +3

-3 1011 0100 +4
1010 0101
-2 +5
1001 0110
-1 1000 0111 +6

-0 +7

Consider a 16 bit bus where inputs toggles

between +1 and –1 (i.e., a small noise input)
Which representation is more energy efficient?
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 11
 Time Sharing is a Bad Idea

Time Sharing Increases Switching Activity

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 12
 Not just a 6-1 Issue: “Cool” Software ???
address
CPU
16
float a [256], b[256];
float pi= 3.14;
for (i = 0; i < 255; i++) {
a[i] = sin(pi * i /256);
b[i] = cos(pi * i /256);
}
512(8)+2+4+8+16+32+64+128+256
= 4607 bit transitions
L16: 6.111 Spring 2006
MEMORY address
a[0] 0111111100000000
a[1] 0111111100000001
a[2] 0111111100000010
a[3] 0111111100000011
b[0] 1000000000000000
b[1] 1000000000000001
b[2] 1000000000000010
b[3] 1000000000000011
float a [256], b[256];
float pi= 3.14;
for (i = 0; i < 255; i++) {a[i] = sin(pi * i /256);}
for (i = 0; i < 255; i++) {b[i] = cos(pi * i /256);}
2(8)+2(2+4+8+16+32+64+128+256)
= 1030 transitions
Introductory Digital Systems Laboratory 13
 Glitching Transitions

Chain Topology Tree Topology

A B A B C D

+ C
+ +
+ D +
+ (A+B) + (C+D)

(((A+B) + C)+D)
„ Balancing paths reduces glitching transitions
„ Structures such as multipliers have lot of glitching transitions
„ Keeping logic depths short (e.g., pipelining) reduces glitching

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 14

 Reduce Supply Voltage : But is it Free?

VDD t =0+
G VS D
VDD
+
K 2
V (V −V )
DD 2 DD T CL
-
IN OUT S
V
DD
C ⋅ ΔV C ⋅ VDD 1
Delay =
L
=
L 2
∝ ≈
i
D
k
(V − V )2 (VDD − VT ) 2
VDD
2 DD T

VDD from 2V to 1V, energy ↓ by x4, delay ↑ x2

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 15

 Transistors Are Free…
(What do you do with a Billion Transistors?)

f =1GHz IN f = 500Mhz IN IN f = 500Mhz

VDD=2V VDD=1V VDD=1V

X X X

OUT SELECT

OUT

Pserial = Cmult 22 f Pparallel = (2Cmult 12 f /2) = Pserial/4

Trade Area for Low Power

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 16
 Algorithmic Workload

Image by MIT OCW.

Exploit Time Varying Algorithmic Workload

To Vary the Power Supply Voltage
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 17
 Dynamic Voltage Scaling (DVS)

Fixed Power Supply Variable Power Supply

ACTIVE IDLE ACTIVE

EFIXED = ½ C VDD2 EVARIABLE = ½ C (VDD/2)2 = EFIXED / 4

1.0
Normalized Energy

0.8

0.6 Fixed Supply

0.4
Variable
0.2 Supply

0
0 0.2 0.4 0.6 0.8 1.0
Normalized Workload

[Gutnik97]
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 18
 DVS on a Processor

Energy per Operation

1
0.8

0.6
0.4

0.2
Digitally adjustable DC-DC 0
59.0
converter powers SA-1110 core 88.5 1.5
1.6

118.0 1.4
147.5 1.3
1.2
5 176.9 1.1
206.4 1.0
Frequency (MHz) 0.9 Core Voltage (V)

3.6V
Figure by MIT OpenCourseWare. Adapted
from R. Min, T. Furrer, and A. P. Chandrakasan.
"Dynamic Voltage Scaling Techniques for
Vout SA-1110 Distributed Microsensor Networks." Workshop
Controller
on VLSI (April 2000): 43-46.

Control

μOS

μOS selects appropriate clock frequency

based on workload and latency constraints
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 19
 Energy Efficiency of Software
Processor (StrongARM-1100) FPGA (Xilinx)

0.25

CLB CLB
0.2
Average Current (A)

0.15

0.1

0.05
C LB C LB
0
ARM Instructions

Figure by MIT OpenCourseWare. Adapted from A. Sinha, DAC.

CLB
I/O
45 5%
9%
40
35
30 Clock 21% Interconnect
Power (%)

25
20 65%

15
10
5
0
Cache Cpntrol GCLK EBOX I/O,PLL
Image by MIT OpenCourseWare. Adapted from Kusse 1998, UCB.
Figure by MIT OpenCourseWare. Adapted from Montanaro 1996, JSSC.

Software”
“Software” Energy Dissipation has Large Overhead
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 20
 Trends: Leakage and Power Gating

Total Energy/Switching Energy

VDD VDD

E = CVDD2 -
E = VDDI010 VT/S
0 1
C C

Switching Leakage
(computing) (standby)
Duty Cycle (%)

Low VT
devices are
leaky - Use a
High VT
device is used
to gate
leakage Sleep
current

L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 21

 Trends: Energy Scavenging

MEMS Generator Power Harvesting Shoes

Image removed due to

copyright restrictions.

Courtesy of Joe Paradiso (MIT Media Lab).

Used with permission.

After 3-6 steps, it provides 3 mA

Vibration-to-Electric for 0.5 sec
Conversion
~10mW
~ 10μW
L16: 6.111 Spring 2006 Introductory Digital Systems Laboratory 22