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Chih-Wen Lu
2015/2/23
Chih-Wen Lu
Introduction
The voltage between two terminals of the FET controls the current
in the third terminal.
The FET can be used both as an amplifier and as a switch.
The current-control mechanism is based on an electric field
established by the voltage applied to the control terminal.
The current is conducted by only one type of carrier (electrons or
holes).
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Chih-Wen Lu
Introduction (contd)
Enhancement-Type MOSFET
MOSFET
FETs
Depletion-Type MOSFET
JFET
FETs: Field-Effect Transistors
MOSFET: metal-oxide semiconductor field-effect transistor
JFET: Junction field-effect transistor
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For vGS = Vt the channel is just induced and current is still small.
As vGS exceeds Vt, more electrons are attracted into the channel.
The result is a channel of increased conductance.
In fact, the conductance of the channel is proportional to the excess
gate voltage (vGS Vt). iD is proportional to vGS Vt and to vDS.
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Cox
e ox
tox
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dv x
dx
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dv x
dx
mn E x mn
dt
dx
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CoxW vGS v x Vt mn
dt
dx dt
dx
dv x
mnCoxW vGS v x Vt
dx
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2
L
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1
2
W
iD mnCox vGS Vt
2
L
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k mnCox
'
n
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iD kn'
Saturation region:
where
W
1 2
vDS
GS
t
DS
L
2
1 W
2
iD kn' vGS Vt
2 L
kn' m nCox
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Cox
e ox
tox
3.45 1011
3
2
4.32
10
F/m
8 109
4.32 fF/m m 2
kn mnCox 450 (cm 2 /V s) 4.32 (fF/m m 2 )
450 108 (m m 2 /V s)
194 10-6 (F/V s)
194 m A/V 2
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VGS 1.02 V
46
iD kn (vGS Vt )vDS
L
From which the drain-to-source resistance rDS can be found as
rDS
Thus,
which yields
Thus,
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vDS
iD
small vDS
1 kn (VGS Vt )
L
1000
1
194 106 10(VGS 0.7)
VChih-Wen
V
GS 1.22
Lu
47
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Continuous channel
W
1 2
iD k
vGS Vt vDS vDS
L
2
'
n
Chih-Wen Lu
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iD
W
k
vGS Vt vDS
L
'
n
rDS
vDS
iD
'W
vDS small kn
L vGS Vt
vGS VGS
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VOV VGS Vt
as
rDS
' W
1 kn
L
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VOV
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vGS Vt
Induced channel
and pinched off at the drain end by raising vDS to a value that results
in the gate-to-drain voltage falling below Vt,
vGD Vt
vDS vGS Vt
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vDS vGS Vt
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Boundary
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W
1 2
iD k
vGS Vt vDS vDS
L
2
'
n
1 'W
2
iD kn vGS Vt
2 L
Thus in saturation the MOSFET
provides a drain current whose
value is independent of the drain
voltage vDS and is determined
by the gate voltage vGS according
to the square-law relationship.
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1 'W 2
iD kn vDS
2 L
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Figure Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus
reducing the effective channel length (by DL).
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1
W
iD kn
(vGS Vt ) 2
2 L L
1 W
1
kn
(vGS Vt ) 2
2 L 1 (L / L)
1 W
kn
2 L
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L
2
1
(
v
V
)
t
GS
L
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1, if we
iD kn 1 vDS (vGS Vt ) 2
2 L
L
Usually, / L is denoted ,
L
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1 'W
2
iD kn vGS Vt 1 vDS
2 L
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VA
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iD
ro
'
n
VA
1
ro
ID ID
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Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation,
incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS
and is given by Eq. (4.22).
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vGS Vt Induced-channel
where the threshold voltage Vt is negative.
or, equivalently,
vSG V
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W
1 2
iD k
vGS Vt vDS vDS
L
2
'
p
where vGS, Vt, and vDS are negative and the transconductance
parameter kp is given by
k p' m pCOX
where mp is the mobility of holes in the induced p-channel.
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vDS vGS Vt
Current
1 ' W
2
iD k p vGS Vt 1 vDS
2 L
where vGS, Vt, , and vDS are all negative.
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Vt Vt 0 g 2f f VSB 2f f
2qN Ae s
COX
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1
W
I D mnCox (VGS Vt )2
2
L
1
32 2
400 100 VOV
2
1
which results in
VOV 0.5 V
Thus,
VGS Vt VOV 0.7 0.5 1.2 V
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81
1.2 (2.5)
3.25 kW
0.4
To establish a dc voltage of +0.5 V at the drain,
we must select RD as follows:
VDD VD
RD
ID
2.5 0.5
5 kW
0.4
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1
W
I D mnCox (VGS Vt ) 2
2
L
1
W 2
mnCox VOV
2
L
VOV
2I D
mnCox (W / L)
2 80
0.4 V
200 (4 / 0.8)
VGS Vt VOV 0.6 0.4 1 V
VD VG 1 V
VDD VD
R
ID
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3 1
25 kW
0.080
84
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2
(VGS Vt )VDS 2 VDS
1
VDD VD 5 0.1
RD
12.4 kW
ID
0.395
I D kn
W
L
Since the transistor is operating in the triode region with a small VDS,
the effective drain-to-source resistance can be determined as follows:
VDS
0.1
rDS
253 W
I D 0.395
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VG VDD
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G2
RG 2 RG1
10
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10 10
5 V
88
VGS 5 6I D
Thus ID is given by
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1 W
I D kn (VGS Vt ) 2
2 L
1
1 (5 6 I D 1) 2
2
Chih-Wen Lu
89
18I D2 25I D 8 0
This equation yields two values for ID : 0.89 mA and 0.5 mA. The first
value results in a source voltage of 6 X 0.89 = 5.34, which is greater
than the gate voltage and does not make physical sense as it would
imply that the NMOS transistor is cut off. Thus,
I D 0.5 mA
VS 0.5 6 3 V
VGS 5 3 2 V
VD 10 6 0.5 7 V
Since VD > VG Vt, the transistor is
operating in saturation, as initially assumed.
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90
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1 W
I D k p (VGS Vt ) 2
2
L
1 W 2
k p VOV
2
L
Substituting ID : 0.5 mA and k /p W / L = 1 mA/V2 and recalling that for
a PMOS transistor VOV is negative, we obtain
and
VOV 1 V
VGS Vt VOV 1 1 2 V
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92
6 kW
I D 0.5
Saturation-mode operation will be maintained up to the point that VD
exceeds VG by |Vt|; that is, until
VD max 3 1 4 V
This value of drain voltage is obtain with RD given by
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4
RD
8 kW
0.5
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The circuit for the case vI = 0 V. We note that since QN and QP are
perfectly matched and are operating at equal |VGS| (2.5 V), the circuit is
symmetrical, which dictates that vO = 0 V. Thus both QN and QP are
operating with |VDG| = 0 and, hence, in saturation. The drain currents
can be found from
I DP
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1
I DN 1 (2.5 1) 2
2
1.125 mA
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I DN
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0 vO
(mA)
10 (kW)
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I DN 0.244 mA
vO -2.44 V
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Figure (a) Basic structure of the common-source amplifier. (b) Graphical construction to
determine the transfer characteristic of the amplifier in (a).
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vDS
RD RD
The straight line intersects
the vDS -axis at VDD [since
vDS VDD at iD 0]
and has a slope of -1/RD
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dvO
Av
dvI
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vI VIQ
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Figure Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for
positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the
triode region and might not allow for sufficient
negative
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Lu signal swing.
106
into
gives
1
W
iD ( mnCox )
2
L
2
(
v
V
)
t
I
vO VDD RDiD
1
W
vO VDD RD mnCox (VI Vt )2
2
L
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107
vI VIQ
W
Av RD mnCox (VIQ Vt )
L
VIQ Vt VOV
Av
2(VDD VOQ )
VOV
2VRD
VOV
Chih-Wen Lu
108
W
1 2
(
v
V
)
v
vO
I
t
O
L
2
vO VDD RD iD
iD mnCox
W
1 2
(
v
V
)
v
vO
I
t
O
L
2
The portion of this segment for which vO is small is given aproximately by
vO VDD RD mnCox
W
vO VDD RD mnCox (vI Vt )vO
L
which reduces to
W
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109
rDS
vO VDD
rDS RD
rDS
RD
vO VDD
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rDS
RD
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111
vI 0 V,
vO 10 V
vI 1 V,
vO 10 V
vO VOB
2
9VOB
VOB 10 0
VOB 1 V
VIB 1 1 2 V
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112
VOC
10
0.061 V
1 18 1 (10 1)
ID
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VDD VOQ
RD
10 4
0.333 mA
18
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113
2 0.333
VOV
0.816 V
1
Thus, we must operate the MOSFET at a dc gate-to-source voltage
AV 18 1 (1.816 1)
14.7 V/V
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115
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1
W
I D mnCox (VGS Vt )2
2
L
Figure The use of
fixed bias (constant
VGS) can result in a
large variability in the
value of ID. Devices 1
and 2 represent
extremes among units
of the same type.
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119
VG VGS RS I D
Figure Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic
arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply;
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120
Figure (c) practical implementation using a single supply; (d) coupling of a signal source to
the gate using a capacitor CC1; (e) practical implementation using two supplies.
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122
10 kW
ID
0.5
VS
5
RD
10 kW
RS 0.5
2
I D 12 kn (W / L)VOV
2
0.5 12 1 VOV
VOV 1 V
VGS Vt VOV 1 1 2 V
VG VS VGS 5 2 7 V
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124
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Figure (a) Biasing the MOSFET using a constantcurrent source I. (b) Implementation of the constantChih-Wen Lu current source I using a current mirror.
126
1 W
kn (VGS Vt ) 2
2 L 2
(W / L) 2
I I R EF
(W / L)1
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2VOV
132
gm
kn (VGS Vt )
vgs
L
id kn
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iD
gm
vGS
vGS VGS
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vD VDD RD iD
vD VDD RD ( I D iD )
vD VD RD id
vd id RD g m vgs RD
vd
Av
g m RD
vgs
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vd
Av
g m RD
vgs
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ro
VA
ID
Figure Small-signal models for the MOSFET: (a) neglecting the dependence
of iD on vDS in saturation (the channel-length modulation effect); and (b)
including the effect of channel-length modulation, modeled by output
resistance ro = |VA| /ID.
ro
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VA
ID
1 W 2
I D kn VOV
2 L
Chih-Wen Lu
vd
Av
g m ( RD ro )
vgs
138
VGS Vt VOV
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140
I D 12 0.25(VGS 1.5) 2
VGS VD
I D 0.125(VD 1.5) 2
VD 15 RD I D 15 10 I D
I D 1.06 mA and VD 4.4 V
W
g m kn (VGS Vt )
L
0.25(4.4 1.5) 0.725 mA/V
VA
50
ro
47 kW
I D 1.06
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141
g m vgs ( RD RL ro )
vgs vi
vo
Av g m ( RD RL ro )
vi
0.725(10 10 47) 3.3 V/V
ii (vi vo ) / RG
vi
RG
vo
1
vi
vi
4.3vi
[1 (3.3)]
RG
RG
vi RG 10
Thus, Rin
2.33 MW
ii 4.3 4.3
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142
which results in
vi 0.34 V
In that in the negative direction, this input signal amplitude results in
vGS min 4.4 0.34 4.06 V
the
maximum allowable input signal
peakLuis 0.34 V.
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143
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144
Figure (a) The T model of the MOSFET augmented with the drain-to-source
resistance ro. (b) An alternative representation of the T model.
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145
g mb
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iD
vBS
v constant
GS
vDS constant
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146
g mb g m
where
Vt
g
VSB 2 2f f VSB
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ig 0
RG
Rin RG
vgs vi
vi vsig
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RG
Rin
Rsig
vi vsig
vo g m vgs (ro RD RL )
151
Av g m (ro RD RL )
Avo g m (ro RD )
RG
Rin
Gv
Av
g m (ro RD RL )
Rin Rsig
RG Rsig
Rout ro RD
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Figure (c) Small-signal analysis performed directly on the amplifier circuit with the
MOSFET model implicitly utilized.
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Rin Ri RG
vi vsig
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RG
RG Rsig
vgs vi
Chih-Wen Lu
1
gm
1
Rsig
gm
vi
1 g m Rs
156
vi
g m vi
id i
1
RS 1 g m Rs
gm
g m ( RD RL )
Av
1 g m Rs
vo id ( RD RL )
g m ( RD RL )
1 g m Rs
g m RD
Avo
1 g m Rs
RG
g m ( RD RL )
Gv
RG Rsig 1 g m Rs
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1
Rin
gm
vi vsig
vi vsig
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1
gm
1
Rsig
gm
Chih-Wen Lu
Rin
Rin Rsig
1
vsig
1 g m Rsig
160
1
gm
Rsig
ii
1
gm
Av
Rin
Gv
Av
Av
1
Rin Rsig
1 g m Rsig
Rsig
gm
vi
v
i g m vi
Rin 1/ g m
Gv
g m ( RD RL )
1 g m Rsig
id i ii g m vi
vo vd id ( RD RL ) g m ( RD RL )vi
Rout Ro RD
Av g m ( RD RL )
Avo g m RD
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161
ii isig
Rsig
Rsig Rin
Normally, Rsig
isig
Rsig
1
Rsig
gm
1/ g m
ii isig
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162
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163
Rin RG
vi vsig
RG
Rin
vsig
Rin Rsig
RG Rsig
vi vsig
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164
Av
Avo
RL ro
( RL ro )
1
gm
RL ro
( RL ro )
1
gm
ro
1
ro
gm
Normally ro
1/ g m , Avo
1. Also, in many
discrete-circuit application, ro
Av
RL ,
RL
RL
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1
gm
Chih-Wen Lu
165
RG
RL ro
Gv
RG Rsig ( R r ) 1
L
o
gm
which approaches unity for
RG Rsig , ro 1 / g m , and ro
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RL .
Chih-Wen Lu
166
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167
Rout
ro
gm
Normally, ro
Rout
gm
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1/ g m , reducing Rout to
Figure (d) Circuit for determining the output
resistance
Rout of the source follower. 168
Chih-Wen
Lu
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Csb
Csb 0
VSB
1
V0
Cdb 0
1
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VDB
V0
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172
Figure (c) The equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
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Io
gm
I i s (Cgs Cgd )
I o g mVgs sCgdVgs
Io
T g m /(Cgs Cgd )
g mVgs
gm
fT
2 (Cgs Cgd )
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1 2
W
k vI Vtn vO vO
2
L n
1 W
2
kn' vI Vtn
2 L n
'
n
for vO vI Vtn
for vO vI Vtn
For QP ,
iDP
W
k VDD vI Vtp
L p
'
p
1
2
VDD vO VDD vO
2
for vO vI Vtp
iDP
1 ' W
k p VDD vI Vtp
2 L p
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for vO vI Vtp
Chih-Wen Lu
181
Vtn Vtp
W
' W
k kp
L n
L p
'
n
mn
Wn m p
Wp
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182
Determine VIH
QN: triode region
QP: saturation region
1
W
iDN kn' vI Vtn vO vO2
2
L n
2
1 ' W
iDP k p VDD vI Vtp
2 L p
iDN iDP
1 2 1
2
vI Vt vO vO VDD vI Vt
2
2
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Chih-Wen Lu
183
dvO
dvO
vI Vtn vO vO
dvI
dvI
VDD vI Vt
Substituting vI = VIH
and dvO/d vI = -1
VDD
vO VIH
2
1
VIH 5VDD 2Vt
8
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Chih-Wen Lu
184
VDD VDD
VIH
VIL
2
2
1
VIL 3VDD 2Vt
8
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Chih-Wen Lu
185
NM H VOH VIH
1
VDD 5VDD 2Vt
8
1
3VDD 2Vt
8
NM L VIL VOL
1
3VDD 2Vt 0
8
1
3VDD 2Vt
8
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Chih-Wen Lu
186
Dynamic Operation
2015/2/23
Chih-Wen Lu
Figure Dynamic
operation of a
capacitively loaded
CMOS inverter: (a)
circuit; (b) input and
output waveforms; (c)
trajectory of the
operating point as the
input goes high and C
discharges through
QN; (d) equivalent
circuit during the
187
capacitor discharge.
iDN
1 ' W
2
kn VDD Vt constant
2 L n
tPHL2 :
vO = (VDD Vt) ~ VDD/2)
Qn: triode region
iDN
1 2
W
k VDD Vt vO vO
2
L n
'
n
2015/2/23
Chih-Wen Lu
188
1
vO
C
t t PHL1
i dt V
DN
DD
t 0
t t PHL1
t 0
1 ' W
2
kn VDD Vt dt VDD
2 L n
1 1 ' W
2
CVt
t PHL1
1 ' W
1 ' W
2
2
kn VDD Vt
kn VDD Vt
2015/2/23
Chih-Wen Lu 2
2 L n
L n
189
Calculate tPHL2
dvO
iDN C
dt
iDN dt CdvO
1 2
W
k VDD Vt vO vO dt CdvO
2
L n
'
n
kn' W L n
2C
2015/2/23
dt
dvO
2 VDD Vt
2Chih-Wen
VDD LuVt
vO2 vO
190
kn' W L n
2C
t t PHL 2
dt
2 VDD Vt
kn' W L n
2C
t 0
kn' W L n
2C
dvO
dt
t PHL 2
2 VDD Vt
vO VDD 2
vO VDD Vt
vO2 vO
dvO
2 VDD Vt
2 VDD Vt
dvO
vO VDD 2
2 VDD Vt vO VDD Vt
vO2 vO
2 VDD Vt
vO2 vO
dx
1
ax 2 x ln 1 ax
3VDD 4Vt
t PHL 2 '
ln
n
C
191
tPHL
1.6C
'
kn W L n VDD
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Chih-Wen Lu
192
Chih-Wen Lu
193
At t = 0-, vO = VDD
Energy stored on the capacitor is 0.5CVDD2
At t = 0, vI goes high to VDD, the capacitor voltage is reduced to zero
During the discharge interval, energy of 0.5CVDD2 is removed from C
and dissipated in Qn.
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194
DD
Chih-Wen Lu
196
DP PDChih-Wen
tP
Lu
197