The PIC 18F452 Memory and

Addressing

Copyright University of Colorado, 2005

ASEN 4519/5519
Lecture #4

PIC Architecture

Harvard architecture

Operand address bus

8 bits wide

Program address bus

12 bits wide
2^12 = 4096

15 bits wide
2^15 = 32768

Instruction bus

Operand
Address

Program
Address

12 bits

15 bits

Data bus

Separate program and data

bus
Supports pipelining
Fetch next instruction while
executing current instruction

Program
Memory

CPU
Instruction

16 bits

Data

Operand
Memory
(SFR &
RAM)

8 bits

16 bits wide

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ASEN 4519/5519
Lecture #4

RAM layout
0x000

12 bit address space

0x080
0x100

2^12 = 4096 bytes

Only 1536 +128 are used

Bank 1

RAM divided into 16 banks

each 256 bytes large
PIC18F452 uses 6 banks for
general purpose registers
(GPR) and 128 bits for special
functions registers (SFR).
The SFR are located at the top
of ram

Bank 0

GPR
0x200

Bank 2

GPR
0x300

GPR

Bank 3
0x400

GPR

Bank 4
0x500

GPR

Bank 5
0x600

Addresses 0xF80 to 0xFFF

UNUSED

The lowest 128 bits of RAM

are called access RAM

Addresses 0x000 to 0x080

Banks 6-14 and the lower

half of bank 15 are unused

0xF00
Bank 15

0xF80
0xFFF

Copyright University of Colorado, 2005

Access RAM
GPR

ASEN 4519/5519
Lecture #4

SFR
3

PIC Addressing modes

Literal addressing

For moving constant values

Eg: movlw 0x23 move the literal value 23 (hex) into the working register

Direct Addressing

For moving variables (eg: movwf COUNT move the value of the working into
variable COUNT.
Access bank direct (0x000 to 0x07F)
Bank direct (0xB00 to 0xB7F)

Requires correctly initializing Bank Select Register (BSR)

Indirect Addressing

Variable pointers

Useful for numbers larger than one byte

Utilizes registers

FSR0, FSR1, FSR2 (FSRx, x=0,1,2)

INDEFx, POSTDECx, POSTINCx, PREINCx, PLUSWx, where x=0,1,2 and

Copyright University of Colorado, 2005

ASEN 4519/5519
Lecture #4

Copyright University of Colorado, 2005

ASEN 4519/5519
Lecture #4

Why use the BSR in direct addressing?

Consider the PIC memory architecture

Full RAM address space requires 12 bits to access all RAM
Instructions are only 16 bits wide
Typical byte oriented instruction

Opcode is 6 bits wide, 2^6 = 64 instructions (literal and control

instructions are 8 bits wide). Allows for all 70+ instructions

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Lecture #4

MOVF and MOVWF opcodes

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MOVFF opcode

MOVFF instruction
Utilizes full 12 bit RAM
addresses
Can move to/from anywhere in
RAM
Requires two instruction cycles
to fetch the instruction before
execution

Copyright University of Colorado, 2005

ASEN 4519/5519
Lecture #4

PIC Pipelining
Fetch nth instruction

Fetch (n+1)th instruction

Fetch (n+2)th instruction

Fetch (n+3)th instruction

Execute (n-1)th instruction

Execute nth instruction

Execute (n+1)th instruction

Execute (n+2)th instruction

Fetch n instruction

Fetch first word of

(n+1)th instruction

Fetch second word of

(n+1)th instruction

Fetch (n+2)th instruction

Execute (n-1)th instruction

Execute nth instruction

NOP

Execute (n+1)th instruction

th

During two word instruction fetch the CPU is idle for one cycle
A majority of assembly operations include moving data between the
working register and RAM
Single word instructions increase system performance
Poor coding practices can directly effect performance

Copyright University of Colorado, 2005

ASEN 4519/5519
Lecture #4

Direct memory address construction

If a=1 (banked)
Upper nibble of RAM address is constructed from lower nibble of BSR
Lower byte of RAM address is constructed from instruction address byte
Requires BSR to be set correctly before instruction execution

If a=0 (access direct)

Upper nibble of address is 0x0 for addresses below 0x80
Upper nibble of address is 0xF for addresses above 0x7F (SFR)
Ignores the value of BSR

The value of a in the opcode is set by the compiler based on the

assigned variable location in RAM
It is the responsibility of the programmer to know if banked or access
direct memory transfer will occur and to set the BSR correctly
Banked memory transfer is efficient for moving data within a memory
bank

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10

Indirect addressing modes

Similar to pointers in C
Useful for accessing arrays
A variable (eg NUM=0x200), address of num is 0x00C
LFSR 0, NUM
Loads FSR0 with the value of 0x200 (2 word operand)
FSR0 is a 2 byte register (FSR0H:FSR0L)
The upper nibble of FSR0H is ignored

MOVF POSTINC0, W
Move the value stored at memory location 0x200 to WREG
Increment FSR0, now equal to 0x201

ADDWF POSTINC0, W
Add the value stored at memory location 0x201 to WREG
Keep result in WREG
Increment FSR0, now equal to 0x202
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Indirect addressing registers

3 indirect addressing registers available
FSRx = FSR0, FSR1, FSR2

5 different addressing modes

INDFx Move value at memory location FSRxH:FSRxL to WREG
and leave FSRxH:FSRxL unchanged
POSTDECx Move value at memory location FSRxH:FSRxL to
WREG and decrement FSRxH:FSRxL. (count down in memory)
POSTINCx Move value at memory location FSRxH:FSRxL to
WREG and increment FSRxH:FSRxL. (count up in memory)
PREINCx Increment FSRxH:FSRxL and then move the value at
memory location FSRxH:FSRxL to WREG
PLUSWx Increment FSRxH:FSRxL with the current value of WREG
and then move the value at memory location FSRxH:FSRxL to
WREG. Return FSRxH:FSRxL to its original value. FSRx is
unchanged.
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Lecture #4

12

Reading data from program memory

Operand (data) memory is limited
Static data such as strings or tables should be stored elsewhere
The PIC18F452 provides a mechanism to access static data in
flash program memory
Due to Harvard architecture data must be accessed from the
operand bus
The following three registers are used
TBLPTRH:TBLPTRL table pointer high and low (address 15 bit
bus)
TABLAT table latch (data -8 bit bus)

Access is similar to indirect addressing

TBLPTR provides the address to access in program memory similar
to FSR
TABLAT provides the register for putting the data similar to the
WREG
There are 4 access modes
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Table pointer access modes

TBLRD*
Move the 8 bit value at location TBLPTRH:TBLPTRL to
TABLAT. TBLPTR remains unchanged

TBLRD*+
Move the 8 bit value at location TBLPTRH:TBLPTRL to
TABLAT. TBLPTR is incremented

TBLRD* Move the 8 bit value at location TBLPTRH:TBLPTRL to

TABLAT. TBLPTR is decremented

TBLRD+*
TBLPTR is first incremented then the 8 bit value at location
TBLPTRH:TBLPTRL is moved to TABLAT.
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STATUS register

Status register is a SFR

Bits 0-4 indicate status
of WREG
Not all commands
change status register
Conditional statements
branch on value of
status register bits

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Homework
LAB FRIDAY 09-SEP-05
ITLL Electronics shop
Install Qwikbug and QFPV using ICD module in ITLL
Show board to Bill Pisano to check operation and
workmanship in ITLL
LECTURE MONDAY 12-SEP-05
Read
Peatman Chapter 3 Instruction set

Copyright University of Colorado, 2005

ASEN 4519/5519
Lecture #4

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