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DISCUSSION OF THEORY

Counting is frequently required in digital computers and other digital systems to record
the number of events occurring in a specified interval of time. As with other sequential logic
circuits counters can be synchronous or asynchronous, depending on how they are clocked.
Synchronous counters are a series of flip-flops, each clocked at the same time, causing the
outputs of the stages (flip-flops) to change together. A binary counter is one of the various types
of synchronous counters. Synchronous counters are different from ripple counters in that clock
pulses are applied to the inputs of all flipflops. A common clock triggers all flipflops
simultaneously, rather than one at a time in succession as in a ripple counter. The decision
whether a flipflop is to be complemented is determined from the values of the data inputs, such
as T or J and K at the time of the clock edge. If T = 0 or J = K = 0, the flipflop does not change
state. If T = 1 or J = K = 1, the flipflop complements. By contrast, asynchronous counters are a
series of flip-flops, each clocked by the previous stage, one after the other.
A synchronous binary counter counts from 0 to 2N-1, where N is the number of bits/flipflops in the counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order
position is complemented or toggled with every clock pulse and a flip-flop in any other position
is complemented on the next clock pulse provided all the bits in the lower-order positions are
equal to 1. In a synchronous binary counter, the flipflop in the least significant position is
complemented with every pulse. A flipflop in any other position is complemented when all the
bits in the lower significant positions are equal to 1 .For example, if the present state of a fourbit
counter is A3A2A1A0 = 0011, the next count is 0100. A0 is always complemented. A1 is
complemented because the present state of A0 = 1. A2 is complemented because the present state
of A1A0 = 11.

FIGURE 1: 4-bit Synchronous Binary Up Counter

With synchronous binary counter, the external clock is connected to the clock input of
every individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. Thus, the changes
in the output occur in synchronization with the clock signal. The result of this synchronization
is that all the individual output bits changing state at exactly the same time in response to the
common clock signal with no ripple effect and therefore, no propagation delay. These counters
also have a regular pattern and can be constructed with complementing flipflops and gates.
Moreover, the polarity of the clock is not important, so can be triggered with either the positive
or the negative clock edge. The regular pattern can be seen from the fourbit counter depicted in
Fig. 1.
It can be seen in Fig.1, that the external clock pulses (pulses to be counted) are fed
directly to each of the J-K flip-flops in the counter chain and that both the J and K inputs are all
tied together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they
connected HIGH, logic 1 allowing the flip-flop to toggle on every clock pulse. Then the
synchronous counter follows a predetermined sequence of states in response to the common
clock signal, advancing one state for each pulse. The J and K inputs of flip-flop FFB are
connected directly to the output QA of flip-flop FFA, but the Jand K inputs of flipflops FFC and FFD are driven from separate AND gates which are also supplied with signals
from the input and output of the previous stage. These additional AND gates generate the
required logic for the JK inputs of the next stage.

FIGURE 2: 4-bit Synchronous Counter Waveform Timing Diagram

The chain of AND gates generates the required logic for the J and K inputs in each stage.
The counter can be extended to any number of stages, with each stage having an additional flip
flop and an AND gate that gives an output of 1 if all previous flipflop outputs are 1. Note that
the flipflops trigger on the positive edge of the clock. The polarity of the clock is not essential
here, but it is with the ripple counter. The synchronous counter can be triggered with either the
positive or the negative clock edge. Then as there is no inherent propagation delay in
synchronous counters, because all the counter stages are triggered in parallel at the same time,
the maximum operating frequency of this type of frequency counter is much higher than that for
a similar asynchronous counter circuit.
The result is a 4-bit Synchronous Up Counter. It should be obvious that the count
sequence is an increasing binary count for each input clock pulse. Then the counter is also
referred to as a count up binary counter the resulting output waveform for each stage is shown in
Figure 2.
It can be seen then that the binary state of the counter can be read as a number equals to
the pulses input count. After the counter reaches the count 111, which is the largest count
obtained using four stages, the next input pulse causes the counter to go to 000 and new count
cycle repeats. The 0 to 15 binary counting sequence of Up Counter is shown in the table below.

TABLE 1: Binary Up Counter of Figure 1


STATE TABLE FOR A FOUR- STAGE BINARY UP COUNTER
Input Pulses

QD

QC

QB

QA

10

11

12

13

14

15

16 or 0
Binary Down Counter

In a binary up counter, a particular bit, except for the first bit, toggles if all the lowerorder bits are 1's. The opposite is true for binary down counters. That is, a particular bit toggles if
all the lower-order bits are 0's and the first bit toggles on every pulse. A simple four stage binary
down counter is shown is Figure 3.
Taking an example, A4 A3 A2 A1 = 0100. On the next count, A4 A3 A2 A1 = 0011. A1, the
lowest-order bit, is always complemented. A2 is complemented because all the lower-order
positions (A1 only in this case) are 0's. A3 is also complemented because all the lower-order
positions, A2 and A1 are 0's. But A4 is not complemented the lower-order positions, A3 A2 A1 =
011, do not give an all 0 condition.

FIGURE 3: Four- Stage Binary Down Counter


The implementation of a synchronous binary down counter is exactly the same as that of
a synchronous binary up counter except that the inverted output from each flip-flop is used. All
the methods used improve a binary up counter can be similarly applied here. The Q-output of
each stage is now used as trigger input to the following stage. It still uses the Q-output as
indication the state of each stage as shown in the count table (table 3). Starting with the counter
Q-output of each stage is logical-0, the first input pulse causes stage A to toggle form 0 to 1. The
trigger pulse to stage B being taken from the Q-output of stage A goes from 1 to 0 at this time so
that stage B is also toggled. The Q-output of stage B going from 1 to 0 causes stage C to be
toggled, which then causes stage D to toggle.

As synchronous counters are formed by connecting flip-flops together and any number of
flip-flops can be connected or cascaded together to form a divide-by-n binary counter, the
modulos or MOD number still applies as it does for asynchronous counters so a Decade
counter or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences.
All we need to increase the MOD count of an up or down synchronous counter is an additional
flip-flop and AND gate across it.

TABLE 2: State Table For A Four-Stage Binary Down Counter


Input
Pulse

QD

QC

QB

QA

Decimal Output
Count

0 (or 16)

15

14

13

12

11

10

10

11

12

13

14

15

16

0 (or 16)

15

As shown in Table 2, the count goes to 1111. The next input pulse toggles A. Since the
signal A (used to toggle stage B) now goes input 0 to 1. Stage B and C and D remain the same,
the count now being 1110. Thus, the count has deceased as a result of the input trigger pulse. In
fact, the count will continue to decrease by one binary count for each input trigger pulse applied.
Table 5 shows that the count will decrease to 0000 after which it will go to 1111 to repeat another

count circle. Using four stage the binary down counter provides a full cut off N = 2 n = 24 = 16
count but in decreasing count mode of operation.

EQUIPMENT AND MATERIALS:


9V Voltage Supply
R1

10 K

R2

10 K

R3

100

R4

100

R5

100

R6

100

R7

100

C1

47 F

RG1

LM7805

IC1

NE 555 IC

IC2

74LS93 IC

D1,D2,D3,D4,D5

LED

Jump wires