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Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
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ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
Delay
for n bit
2n
Rea
for n
bit
7n
Area
delay
product
14n2
Ripple
carry
adder
Carry
select
adder
Carry
look
ahead
adder
2.8(n)1/2
14n
39.6(n)3/2
4log2n
4n
16nlog2n
Power
Speed
Consumption
High
Limited
Less
array
than Moderate
Less
other
than Highest
Less
radix-2
than High
1. INTRODUCTION
Power dissipation of VLSI chips is traditionally
a neglected subject. In the past, the device density
and frequency were low enough that it was not a
constraining factor in chips. As the scale of
integration improves, more transistors, faster and
smaller than their predecessors, are being packed
into a chip. This leads to the steady growth of the
operating frequency and processing capacity per
chip, resulting in increased power dissipation.
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(2)
ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
BZFAD
A low-power structure called BZ-FAD (Bypass
Zero, Feed A Directly) for shift-and-add
multipliers is proposed. The architecture
considerably lowers the switching activity of
conventional multipliers. The modifications to the
multiplier which multiplies A by B include the
removal of the shifting the B register, direct
feeding of A to the adder, bypassing the adder
whenever possible, using a ring counter instead of
a binary counter and removal of the partial
product shift. The architecture makes use of a
low-power ring counter proposed in this work.
Simulation results for 32-bit radix-2 multipliers
show that the BZ-FAD architecture lowers the
total switching activity up to 76% and power
consumption up to 30% when compared to the
conventional architecture. The proposed multiplier
can be used for low-power applications where the
speed is not a primary design parameter.
The rest of the paper is organized as follows.
Section II briefly reviews the background
information about conventional shift and add
multiplier. Section III describes the architecture
description of the low power multiplier. Section
IV describes the low power ring counter
architecture. Results are discussed in section V
and conclusion is in the last section.
2. TYPES OF ADDERS
Addition is the most common and often used
arithmetic operation on microprocessor, digital
signal processor, especially digital computers.
Also, it serves as a building block for synthesis all
other arithmetic operations. Therefore, regarding
the efficient implementation of an arithmetic unit,
the binary adder structures become a very critical
hardware unit. Although many researches dealing
with the binary adder structures have been done,
the studies based on their comparative
performance analysis are only a few.
With respect to asymptotic delay time and area
complexity, the binary adder architectures can be
categorized into four primary classes as given
below.
2.1 Ripple Carry Adder(RCA)
The well known adder architecture, ripple carry
adder is composed of cascaded full adders for nbit adder, as shown in figure 2.1.It is constructed
by cascading full adder blocks in series. The carry
out of one stage is fed directly to the carry-in of
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ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
Redefined Equations
g[ i,i+3 ] = gi+3 + gi+2 pi+3 + gi+1 pi+2 pi+3 +
g[i pi+1 pi+2 pi+3
p[ i,i+3 ] = pi pi+1 pi+2 pi+3
Now the modified block diagram for the Carry
Look ahead Adder (8-bit) using levels (of 4-bit
CLA) will be as block diagram below
Figure 5: Wallace Tree Block Diagram
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ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
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ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
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ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
ISSN: 2278-5795
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
DIP Switch
Single 8-way DIP switch [SW 1] is provided to be
used as input to the FPGA. Logic Level applied to
FPGA through SW1 is seen on LEDs LD0 to
LD7.
JUMPERS
Various jumpers are provided for
Selection of clock.
Selection of configuration mode.
KEYS
Two Keys are provided for Keyboard
Interface.
Downloading Cable
For downloading the design from PC, a 9 pin
D-Type male (J7) connector is provided on board.
The trainer can be connected to PC's parallel port
with a cable having 25 pins D-Type (male) to 9
pins D- type (female) connector. This cable is
provided with the trainer.
LEDs
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ISSN: 2278-5795
Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
Conventional 8 BZFAD
Minimum
bit
bit
8.258 ns
6.975 ns
121.094 Mhz
143.362 Mhz
8.426 ns
7.167 ns
period
Maximum
frequency
Minimum
input
time
arrival
Conventional 16 BZFAD 16
Minimum
bit
bit
9.946 ns
6.564 ns
100.540 Mhz
152.352
period
Maximum
frequency
Minimum
Mhz
10.281 ns
7.502 ns
input arrival
time
8.3 Area Utilization
Minimum
Conventional
BZFAD
4 bit
4 bit
5.943 ns
4.918 ns
168.264 Mhz
203.33
period
Maximum
frequency
Minimum
Mhz
6.682 ns
5.160 ns
input
arrival time
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
CONCLUSION
[1] M.Mottaghi
Dastjerdi
,A.afzali
Kusha,m.Pedram BZFAD A Low Power
Low Area Multiplier Based on Shift and Add
Architecture IEEE Trans. Very Large Scale
Integr .(VLSI)Syst., Vol.17, no-2,pp302-306,
Feb. 2009.
[2] O. Chen, S.Wang, and Y.W. Wu,
Minimization of switching activities of
partial products for designing low-power
multipliers, IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 11, no. 3, pp. 418
433, Jun. 2003.
[3] B.Parhami Computer arithmetic algorithms
and Hardware designs 1 st ed.Oxford U.K.
Oxford Univ, Press 2000.
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Prasann D. Kulkarni, et al International Journal of Computer and Electronics Research [Volume 2, Issue 2, April 2013]
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AUTHORS PROFILE
Mr. Prasann D.Kulkarni has
completed B.E in Electronics
and Communication Engg.
From KLSs Vishwanathrao
Deshpande Rural Institute of
Technology,
Haliyal,Uttar
Kannada, Karnataka, India.
Presently he is pursuing M. Tech in Digital
Electronics from KLSs G.I.T, Belgaum,
Karnataka, India and since 2008 he is working as a
lecturer in KLSs Vishwanathrao Deshpande Rural
Institute of Technology, Haliyal, Uttar Kannada,
Karnataka, India. His Research interests are in Low
Power Embedded system design, Fuzzy logic in
neural applications.
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