Birla Institute of Technology and Science Pilani, Hyderabad Campus

Second Semester 2012-13

EEE C364/ECE C364: Analog Electronics, Comprehensive Examination (Closed Book)
Time: 2:00 PM-5:00 PM
Date: 3-5-2013
Max. Marks: 120
Note: Answer all the questions in the same sequence. Assume all operational amplifiers are ideal.
Use the same node names as mentioned in circuit diagram.
1. (i)(a) Using small signal model of the BJT as shown in figure 1(b), Draw the small signal equivalent for the
circuit shown in figure 1(a). (b) With the help of small signal equivalent circuit derive the small signal output
resistance for the circuit shown in figure1 (a).
(2+4)
(ii) Given that the circuit shown in figure 1(c) yields Io = A2V2 A1V1 (1/Ro) VL, then (a) Find the expressions
for A2, A1 and (1/Ro). (b) Find the relation between the resistances that yields Ro = . (c) Using the relation
found in (b), determine the new expressions for A2, A1 and Io.
(9+2+3)

2. (i) For the circuit in figure 2(a)









1
. (a) Determine the expression for Vo in terms of V1 and V2

(b) Using Vo expression from (a) determine the differential gain, common mode gain and CMRR for the
circuit. (c) To improve CMRR a resistance RG is now added between the nodes VA and VB. Determine the
(5+4+4+2)
new expression for Vo in terms of V1 and V2. (d) Calculate the new value of CMRR.
(ii) Circuit shown figure 2(b) simulates a lossy inductor shown in figure 2 (c). Determine the expressions for
Leq and Req.
(5)

3. (i) The transfer function [Vo/Vi(s)] of a low pass filter circuit is given as
1
Vo
K c2
1
1
1 K
= 2
where c2 =
,2k =
+
+
2
Vi s + 2k c s + c
R1 R2 C1C 2
R1C1 R2 C1 R2 C 2

R
(R1 R2 C1C 2 )1 / 2 , K = 1 + B , Find
RA

C1, C2 and RB, such that the circuit behaves as a second order low pass Butterworth filter with a dc gain of 10
and cutoff frequency of 1KHz. Assume R1 = R2 = 1K and RA = 1K.
(5)
(ii) A low pass circuit has cutoff frequency fc = 1 KHz and frequency at which stop band begins fs =2.5 KHz.
The pass band attenuation is 2dB and stop band attenuation is 45dB. Specify the minimum order of the
Butterworth filter that will meet the specifications. What will be the actual stop band attenuation of this
designed filter?
(6)

(iii) Design a switched capacitor based non inverting integrator using switches, capacitors and a single
operational amplifier. Clearly label the clock phases and explain the operation in brief.
(4)
(iv) Design a frequency multiplier circuit which multiplies the input frequency by 3. If the input is cos(t)
then the output should be cos(3t). The components available for design are two multipliers with the scaling
factor of 1(i.e. if x and y are the inputs the output will be x.y), a single operational amplifier and any number
of resistances. Clearly mention the value of resistances used.
(5)
4. For the circuit shown in Figure 4(a) with diodes of cut-in voltage 0.5 V, (i) Determine the range of input
voltage (Vi) for which diode D1 is ON. (ii) Determine the range of input voltage for which diode D2 is ON.
(iii) Determine the different slopes that will occur in the voltage transfer characteristic (Vo v/s Vi curve) of the
circuit along with range of input voltages for which the slopes occur. (iv) Draw the VTC curve for the circuit
with clearly labeled break points and slopes. (v) If a triangular wave shown in figure 4(b) is given as input to
the circuit then draw the output waveform with clearly labeled amplitude and time axis.
(3+3+7+3+4)

5. (i) A square wave generator circuit is shown in the figure 5(a), where k denotes the fraction of resistance R
between nodes VP and VB. The resistance between the nodes VA and VP will be (1-k) R. Assuming the diodes
are ideal with zero cut-in voltage (a) Derive the expression for duty cycle in terms of k. (b)Calculate the value
of duty cycle when k =0, k=1 and k = 0.5. (c) What are the advantages of this circuit over normal Astable
Multivibrator circuit?
(8+3+1)
(ii) Using 7805 Voltage regulator IC, design a current source that will deliver a current of 0.25 A to a 48
load. Draw the circuit and clearly mention the values of resistances used. Also determine the restriction on
input voltage if the drop out voltage is 2 V.
(3)
(iii) For switching regulator circuit shown in the
figure 5(b), derive the expression for output voltage
Vo in terms of input voltage Vi and duty cycle of the
PWM. Calculate the value of output voltage if input
is 5 V and duty cycle of PWM is 60%. (Transistor
acts as ideal switch)
(5)
6. (i) For a 3-bit DAC the reference voltage Vr = 3.2 V and for input codes from 000 to 111 the actual output
values are found to be Vo = 0.2, 0.5, 1.1, 1.4, 1.7, 2.0, 2.6 and 3 all in V. (a) Find the offset error and gain
error in fractions of 1 LSB. (b) After correcting the offset and gain error, find the INL and DNL error in
fractions of 1 LSB at each step. (Answer (b) in form of a table).
(2+8)
(ii) Draw the circuit for 2-bit flash A/D converter, assuming comparators used have offset voltages. If the
missing code for this A/D converter is 0101, then find the relation between offset voltages when the missing
code occurs.
(6)
(iii) If the frequency of the clock is 500KHz, then find the maximum conversion time for (a) 10-bit successive
approximation ADC (b) 8-bit Dual slope ADC.
(2+2)