9.
A Stochastic Jitter Model for Analyzing Digital
Timing-Recovery Circuits
James R. Burnham Chih-Kong Ken Yang
High-Q Design, Los Altos, CA UCLA, Los Angeles, CA
burnham@highqdesign.com yang@ee.ucla.edu
1. ABSTRACT
This paper describes a stochastic jitter model for analyzing the
performance and bit error rate (BER) of digital timing recovery
circuits. The model uses parallel interconnected Markov chains to
simulate the behavior of the system in response to both random
and deterministic jitter. Unlike conventional Markov-chain models
that require the system to be stationary, the parallel-chain model
approximates deterministic changes in conditions with transitions
between sub-chains. To verify the accuracy of the model, an
analysis was performed on a digital delay-locked loop, and the
results compared to measured data. The resulting transition
probabilities and BER predicted by the proposed model are more
than three orders of magnitude more accurate than those predicted
by a conventional Markov-chain model.
Categories and Subject Descriptors
B.7.2 [Integrated Circuits]: Design Aids – Simulation
General Terms
Algorithms, Measurement, Performance, Design, Reliability
Keywords
Jitter, timing margins, timing recovery circuits, mean-time-
between-failures (MTBF), bit-error-rate (BER), stochastic model,
Markov chain, delay-locked loop (DLL)
2. INTRODUCTION
Digital timing recovery circuits (DTRCs), such as delay-
locked loops (DLLs) and phase-locked loops (PLLs), are widely
used feedback circuits that maintain alignment between clock and
data signals [1]. Their performance is often measured in terms of
bit-error-rate (BER) or mean-time-between failures (MTBF),
which provide an estimate of the overall reliability of the system.
Both measures are strongly affected by random and deterministic
fluctuations in signal phase (jitter), and, both can be difficult to
measure directly. This is especially true in systems where the
required MTBF is on the order of a year or more, and errors are
rarely observed.
There are a number of techniques for estimating the BER (or
MTBF) of a system. They generally fall into one of two categories:
deterministic and stochastic. Deterministic techniques typically
Permission to make digital or hard copies of part or all of this work for
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies
bear this notice and the full citation on the first page. To copy otherwise,
to republish, to post on servers or to redistribute to lists, requires prior
specific permission and/or a fee.
DAC’09, July 26-31, 2009, San Francisco, California, USA
Copyright 2009 ACM 978-1-60558-497-3/09/07....10.00
116
Authorized licensed use limited to: University College Dublin. Downloaded on November 20, 2009 at 09:28 from IEEE Xplore. Restrictions apply.
Haitham Hindi
PARC, Palo Alto, CA
haitham.hindi@parc.com
Reference
DLL Integrator Digital Phase
Filter Det.
Digitally-Controlled Delay Line
Input Output
Probability of
Increment
State State State State
1 2 3 N
No Probability of
Change
Delay Decrement
Figure 1: Block diagram and equivalent state-transition diagram
of a basic digital DLL.
involve the use of circuit or system-level simulators to model
behavior under worst-case conditions [2]. These models can be
driven with pseudo-random waveforms to observe the response of
the system over an extended period of time. Unfortunately, it is
rarely possible to simulate long enough time periods to accurately
determine the BER.
Stochastic techniques, such as those based on Markov-chain
models [3,4], offer a more efficient method for estimating the BER
of a system. They can be used to calculate the probability that the
system will occupy a particular state from statistical properties of
the input signals and the deterministic behavior of the system.
These models are based on the assumption that the system is
stationary, and that transitions between states are purely
probabilistic. These restrictions exclude many practical systems,
including those that operate under changing conditions and those
that experience significant levels of deterministic noise and jitter
[5].
In this paper, a model that combines stochastic and
deterministic elements to predict the behavior of a synchronous
system in the presence of noise and jitter is introduced. The model
is based on a series of interconnected recurrent Markov chains,
with each chain representing a distinct set of operating conditions.
A sample analysis of a digital DLL is also presented, including a
comparison to a conventional Markov-chain model.
3. CONVENTIONAL MARKOV-CHAIN
MODEL
To understand the limitations of a conventional Markov-chain
model, it is useful to go through a simple example. A block
diagram of a basic digital delay-locked loop (DLL) is shown
together with the equivalent state-transition diagram in Figure 1. In
this circuit, the digitally-controlled delay line (DCDL) can only
occupy one of N states at any given time, and only one unit (gate)
delay (UD) can be added or subtracted per clock period. The
probability of transitioning to an adjacent state is determined by
properties of the DLL and by the phase difference between the
output and reference.
 n-2 n-1 n0 n1 n2 State 0 Max. Delay

Probability of Occupying State

100 Number 10
Range Spec.
Probability of Occupying State

105
BER
Worst-Case 10
10 Single-Chain
1010 Phase Model

1015
20 Probability
1020
30
1025
6
5
4
3
2
1 0 1 2 3 4 5
30
10
12 10 8 6 4 2
Delay From Input to Reference (unit delays)
Figure 2: Probability of occupying each state in the DLL as the
input signal phase is swept (  = 1 4 UD).
Under ideal conditions, the DLL reaches an equilibrium state
and remains there indefinitely. However, in the presence of noise
and jitter, the output may diverge from the reference far enough to
cause a timing error. The probability of an error occurring can be
determined by modeling the system as a recurrent Markov chain,
and calculating the probability that the phase of the output clock
will vary enough to violate the timing requirements of the system.
To perform this calculation, the probability of occupying each
state in the system must first be determined. From the basic limit
theorem for Markov chains, the equilibrium probability of
occupying each state in the system is
 = lim P •  0 ,
i
where P is a matrix of transition probabilities,  0 is some
arbitrary initial state vector, and each element  n in vector  is
the average or equilibrium probability of occupying the n th state
in the chain [6].
The transition probabilities are calculated from the reference-
clock jitter probability density function (pdf), the timing of the
phase detector (PD), the state number, and the spacing between
states. For a two-state phase detector, which generates an
increment or decrement when the output clock edge transitions
before or after the reference-clock edge, the probability of going
from state n m to state n m + 1 is
p ( nm nm + 1 ) =
where f J ( t ) is the jitter pdf between the reference and input
clocks, m is the state number, and d u is the propagation delay
through the unit delay element in the delay line. The probability of
moving from state n m to state n m – 1 is
p ( nm nm – 1 ) =
Using (1), (2), and (3), the probability of occupying each state
in the DLL is calculated, and the results plotted as a function of
input signal phase in Figure 2. As shown in the plot, the worst-case
input signal phase, where the probability of occupying the largest
number of states reaches a maximum, occurs half a unit delay from
the center of the phase detector window. At the worst-case phase
there is a 10 – 30 probability that the n – 2 and n 2 states will be
occupied. If a delay variation of four unit delays (a five-state
BER Actual
Phase 10
Detector
Window
(=4 UDs)
10
DLL State Number
0 2 4 6 8 10 12
Figure 3: Probability of occupying DLL state when supply levels
periodically spike (freq.= f s 200k , 0.5% duty cycle, =1/4 UD).
range) is sufficient to cause a timing violation, then the BER of the
system is equal to the probability that one of the outer two states
will be occupied ( 2 × 10 – 30 ).
3.1 Limitations of Conventional Model
As mentioned earlier, many practical systems can not be
considered strictly stationary, and are difficult to model with a
conventional Markov chain. An example is a system where a bank
of drivers turns on and off at regular intervals, modulating power
supply levels across the chip. As the supply fluctuates, the
propagation delay of each gate in the DCDL changes, altering the
behavior of the system.
It is possible to approximate a non-stationary system with a
stationary Markov chain by modifying the input signal
i
(1) distributions. For example, when supply levels fluctuate, the
probability density function (pdf) of the input signal phase can be
made bimodal or multimodal to compensate for changes in
propagation delay. Unfortunately, this approximation breaks down
when the supply levels change at rates low enough to be tracked by
the system (which is often the case in practical designs).
To illustrate this point, a conventional Markov-chain model is
used to calculate the probability of occupying each state in a digital
DLL with periodic spikes on the power supply. The spikes occur at
0.0005% of the DLL sample rate ( f s 200k ) and last long enough
to cause a state change (0.5% duty cycle). The calculations are
performed at the worst-case input phase, where the probability of
occupying the adjacent states is highest. For comparison, the
0
probabilities are also calculated separately at each supply level,
– fJ ( t – m  du ) dt, (2) and then normalized and combined into a single histogram. The
combined histogram is then used as a reference to evaluate the
accuracy of the conventional model. Both histograms are plotted in
Figure 3. As shown in the plot, the conventional model
underestimates the BER by nine orders of magnitude.
Another limitation of the conventional model is its inaccuracy
in modeling the behavior of the system in response to certain types

of deterministic jitter. For example, the conventional model can
0 fJ ( t – m  du ) dt. (3)
not distinguish between short, frequent bursts of jitter and long,
infrequent bursts. Yet the system responds quite differently to these
events.
To illustrate the difference, the probability of occupying each
state in a digital DLL with long, infrequent bursts of jitter on the
reference clock is calculated (frequency= f s 100k , duty
cycle=0.1%). In one case the conventional model is used, and in
the other the probabilities are calculated separately for each jitter
level and then combined in proportion to their overall rate of

117
Authorized licensed use limited to: University College Dublin. Downloaded on November 20, 2009 at 09:28 from IEEE Xplore. Restrictions apply.
 4.1 Transition and State Probabilities
Probability of Occupying State
0 Actual
10 Single-Chain
Model Probability
Max. Delay
The transition probabilities in the two-chain model are similar
Range Spec. to those of the single-chain model, except now there are six non-
10
10
zero transition probabilities for each state instead of three. If
BER
p ( n 0 n 1 ) is the probability of transitioning from state n 0 to state
n 1 , and p ( c1 c 2 ) is the probability of transitioning from chain-1

20
to chain-2, then the complete set of transition probabilities for state
10
BER
n 0 are2
{ p ( n0 n – 1 )  p ( c1 c 1 ), (4)

5
4
3
2
1 0 1 2 3 4 5
DLL State Number p ( n0 n 0 )  p ( c 1 c 1 ),
Figure 4: Probability of occupying DLL state when ref. clock p ( n0 n 1 )  p ( c 1 c 1 ),
jitter slowly toggles (1=1/8 UD, 2=1 UD, freq.= f s 200k ). p ( n0 n – 1 )  p ( c 1 c 2 ),
p ( n0 n 0 )  p ( c 1 c 2 ),
6WDWH

6WDWH

6WDWH

6WDWH
Q
6WDWH
1 p ( n0 n 1 )  p ( c 1 c 2 ) }.
The probability of transitioning between states is calculated as
before, by integrating the jitter pdf over the appropriate range for
6WDWH 6WDWH 6WDWH 6WDWH 6WDWH
   Q 1 the system. The probability of transitioning between chains is
determined by the relative and absolute amount of time spent in
Figure 5: Markov-chain model of bimodal system. each chain. The relative amount of time spent in chain i is3
tc
occurrence. In the resulting histograms, plotted together in -----i , (5)
T
Figure 4, the conventional model underestimates the BER by six
orders of magnitude. where t c is the average amount of time spent in the i th chain
i
during a time period T . The absolute amount of time spent in
4. PROPOSED MODEL chain i is proportional to n c , the average number of consecutive
i
sample periods spent in chain i . The overall probability of
An alternative to conventional Markov-chain models that more
remaining in chain i during any single period is then given by
accurately tracks changing conditions and deterministic noise and
jitter is a model based on parallel interconnected Markov chains. p ( ci c i ) = ( 1 – 1 n c ), (6)
i
Each sub-chain in the proposed model is used to represent a
and the probability of transitioning out of chain i is
distinct set of conditions, and the probability of transitioning into a
particular chain is proportional to the amount of time spend under p ( ci ) = 1 nc . (7)
i
the corresponding set of conditions. Each set of conditions can
The probability of transitioning from chain i to chain j is equal to
include different supply levels, temperatures, jitter levels, or other
the probability of transitioning out of chain i multiplied by the
parameters that affect system behavior.
proportion of time spent occupying chain j relative to all chains
The parallel chain approach is mainly useful for modeling
other than i :
changes that occur at rates slow enough to be tracked by the
system. If conditions change at rates too high to be tracked1, then it 1  t cj -
may be necessary to either alter the pdf of the input signals, or use p ( ci c j ) = ------
------------- . (8)
a conservative, worst-case model for the system. The first
approach can be used when the phase of the input signals is
changing rapidly, but the system remains stationary. In this case,
the effect can be approximated by distorting the jitter pdf of the
input signals to create an equivalent distribution. The latter
approach is necessary when the behavior of the system changes in
ways that can not be approximated by simply altering the input
signal phase.
An example of a parallel two-chain model of an N -state
system is shown in Figure 5. For simplicity, the system is limited
to transitions between adjacent states. In this model, each chain
represents the system under a different set of operating conditions,
and states n 1 and n 2 together form the probability of occupying
state n in the physical system. The diagonal arrows represent the
probability that the system will simultaneously change states and
transition to the other chain.
1. This assumes the changes are not correlated with the sample rate
of the system, and will not alias to lower frequencies
118
Authorized licensed use limited to: University College Dublin. Downloaded on November 20, 2009 at 09:28 from IEEE Xplore. Restrictions apply.
nc  T – tc 
i i
The equilibrium probability of occupying each state in the
parallel-chain model is calculated as before, using the transition
matrix and an arbitrary initial state vector. However, the transition
matrix now has M × N rows and columns, where M is the number
of modes (chains) in the model. Also, instead of having three non-
zero transition probabilities for each row, there are now 3  M non-
zero probabilities. The overall probability of occupying a state can
be calculated by summing the individual probabilities for each
mode.
4.2 Limitations of Proposed Model
The parallel Markov-chain approach has several important
limitations. First, conditions may vary over a continuous range,
making it difficult to identify discrete sets. The model is based on
the assumption that changes occur in discrete steps, and that on
2. The transition probabilities are slightly different for the end states.
3. Assume T is long enough to capture the average behavior of the system.
 Probability of Occupying State
100 Max. Delay power supply toggles slowly between two levels. The probabilities
Range Spec. were calculated using a parallel two-chain model, and, for
BER
comparison, using the combined method described earlier. As

10
10 Single-Chain shown in the plot, the probabilities are now much more closely
Model
matched to the expected distribution, and the error in the BER has
Actual been reduced from more than nine orders of magnitude to
10
20 Probability
approximately 10%.
The calculations were repeated with long, infrequent bursts of
10
30 jitter on the reference clock. The resulting histogram is plotted

6
5
4
3
2
1 0 1 2 3 4 5 together with the reference histogram in Figure 7. As expected, the
DLL State Number
probabilities match the reference very closely, with the BER now
Figure 6: Probability of occupying DLL state when supply levels matching to within 5%.
periodically spike (freq.= f s 200k , 0.5% duty cycle, =1/4 UD).
5. MODEL DERIVATION
100
Probability of Occupying State

Single-Chain Actual The proposed parallel-chain model can be derived using

Model
10
10
BER
5
4
3
2
1 0 1 2 3 4 5
DLL State Number
Figure 7: Probability of occupying DLL state when ref. clock jitte
slowly toggles (1=1/8 UD, 2=1 UD, frequency= f s 200k ).
average they repeat over time. If, however, the operating
conditions continually change, then it may be difficult to construct
an equivalent model. The parallel-chain model is still strictly
stationary, and can only approximate non-stationary systems. This
limitation can often be overcome by using enough chains to
capture the average behavior of the system without reproducing
every detail.
Another limitation of both parallel and single-chain models is
that conditions are assumed to vary over a finite range. In other
words, the system is assumed to be trend-stationary [7]. This
limitation is rarely encountered in practical circuits, which tend to
operate under conditions that repeat over time.
Another potential source of error comes from modeling the
transitions between chains as being stochastic, when in fact they
may be deterministic. As a result, only the average behavior is
modeled, and some information on the precise sequence of events
may be lost. For example, if the power supply voltage in an ideal
system is steady for 100 cycles and then drops far enough to cause
a state change for the next 100 cycles, there is a zero probability
that the system will transition for the first 99 cycles, and a 1.0
probability that it will transition on the 100th cycle. However, in
the stochastic model there is a 1/100 probability that the system
will transition during any cycle.
Despite these limitations, in most cases of practical interest the
parallel-chain model is significantly more accurate than a single-
chain model in simulating the effects of changing conditions and
deterministic sources of noise and jitter.
4.3 Digital DLL Example
To compare the accuracy of the single and parallel-chain
models, the examples from section 3.1 are reanalyzed. Figure 6
shows the probability of occupying each state in the DLL when the
Probability Max. Delay simulated results, or it can be fit from measured data after the
Range Spec.
circuit is fabricated. In both cases the structure of each Markov
chain is determined by the circuit architecture, and can be modeled
using a procedure similar to that described in Section 3. The
procedure for determining the number of chains and the
parameters for each chain is more involved, and depends on the
noise and jitter characteristics of the system.
5.1 DLL Model Derivation
In DLLs, noise sources contribute to timing uncertainty, which
then combines with signal jitter to create an overall jitter
distribution. One of the key steps in creating an accurate DLL
timing model is to determine the combined worst-case jitter
distribution for the input and reference signals. This can be done
through simulation, or based on experience with similar circuits.
Once the jitter distribution is known, it can be separated into
stochastic and deterministic components. The deterministic
components then need to be further broken down into those that
are within the tracking bandwidth of the DLL, and those that are
not. For those that are within the tracking bandwidth, the dominant
components are assigned individual Markov chains. Each
component has a mean and variance, as well as a probability of
occurring, which together define the parameters for the chain. The
remaining components, both deterministic and random, are then
combined in a composite jitter distribution that is used to define
the reference clock.
As an example, if a DLL with a tracking bandwidth of 20 clock
cycles experiences 200-cycle bursts of supply noise every 1000
cycles, then the system can be modeled as two parallel chains.
Assuming each burst causes the mean and variance of the
reference clock jitter distribution to increase by 20%, chain-1 will
have nominal mean and variance and a transition probability of
p ( c1 c 2 ) = 1 800 , while chain-2 will have 20% higher mean
and variance with p ( c2 c 1 ) = 1 200 .
5.2 DLL Model Fitting
There are several techniques for fitting parallel-chain models
to measured data. The most rigorous is to measure jitter between
the input and reference clocks under worst-case conditions, and
then follow the procedure above to derive the model. This
technique is reliable, but it requires accurate jitter measurements
made on internal circuit nodes.
A less accurate but more practical way to fit the model is to use
a logic analyzer to measure state transition probabilities (STP) in

119
Authorized licensed use limited to: University College Dublin. Downloaded on November 20, 2009 at 09:28 from IEEE Xplore. Restrictions apply.
 Jitter Probability (normalized)
Trimodal1 1
101 0.9
Probability of DLL State Change

Trimodal2
3
10
Pure Gaussian
105
PD window
(=1UD)
1 0.5 0 0.5
Delay From Input to Reference (unit delays)
Figure 8: Calculated probability of generating a jitter-induced
state change in the DLL.
the DLL while sweeping the phase of the reference clock. The
resulting probability curve shows the response of the DLL to noise
and jitter on internal circuit nodes without requiring sensitive
analog measurements. The STP curve can then be used as a
reference to adjust the model until the measured and calculated
transition probabilities match. Transition probabilities can be
measured over a fairly wide range ( ~10 – 13 -1) in a reasonable
amount of time, and the remaining tail regions typically follow a
predictable (Gaussian) roll-off and can be extrapolated.
In many cases it is possible to identify the dominant
deterministic jitter components in the STP curve and model them
as separate chains. Each deterministic component causes the
probability curve to deviate from an ideal Gaussian shape, and the
distortions can be reproduced by adding parallel chains and
adjusting the phase and variance of each until the probability
curves match. For example, in Figure 8 the variance of the
reference clock jitter in all three curves is identical, but the
trimodal curves have additional modes 1/8 UDs before and after
the nominal phase. The effect of the additional modes is to widen
the main lobe without significantly altering the slope of the tail
regions.
Even if individual components are difficult to identify, it is still
possible to add parallel chains until the overall shape of the STP
curves match. The BER and MTBF are calculated from the
probability of occupying outlying states, which in turn depend on
the tail portions of the STP curves. Thus, as long as the tail
portions of the curves reasonably well matched, the BER and
MTBF should also match.
To illustrate this point, three different transition probability
curves with different main lobes but identical variance are plotted
in Figure 8. The BER of the two trimodal systems are relatively
closely matched ( 1.2  10 – 26 and 1.9  10 – 26 ), despite significant
differences in the main lobes. In contrast, the BER of the purely
Gaussian system is more than seven orders of magnitude lower
( 8.9  10 – 34 ), even though the slope of the tail regions is identical.
The key to accurately calculating BER and MTBF is making sure
that both the slope and the phase of the tail regions of the measured
and calculated STP curves match.
6. EXPERIMENTAL RESULTS
To evaluate the accuracy of the parallel-chain model,
measurements were performed on a clock-alignment DLL
implemented in a large, complex ASIC with numerous sources of
noise and jitter. The measured data was used to derive both single
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-400 -300 -200 -100 0 100 200 300 400
Reference-Clock Jitter Magnitude (ps)
1 Figure 9: Measured cycle-cycle jitter on the reference clock.
Table 1: Cycle-to-cycle jitter distribution statistics.
Jitter Component % of Total Variance ()
Random 97.54% 51 ps
Deterministic 2.46% 291 ps
Total 100% 68 ps
and parallel-chain versions of the model, which were then
compared for accuracy.
6.1 Reference-Clock Jitter
A plot of the jitter distribution between the input and reference
clocks is shown together with a breakdown of the jitter
components in Figure 9 and Table 1. The jitter measurements were
made through a system of debug busses, which contributed
significantly to the measured noise and jitter. Consequently, the
data is not reliable enough by itself to derive a model. However,
some useful information can still be gleaned from the data. In
particular, the distribution appears random with a Gaussian
distribution. But when the data are analyzed 1 , significant
deterministic components are found. Furthermore, the variance of
the deterministic components is significantly larger than that of the
random components. It turns out that most of the deterministic
jitter is caused by relatively large periodic phase steps on the
reference clock, which are infrequent enough that their effect on
the overall jitter distribution appears small.
6.2 Transition Probabilities
The transition probabilities in the DLL are plotted as a
function of reference-clock phase in Figure 10. The asymmetries
visible in the curve were consistently present in the measurements,
and are caused by the large deterministic phase steps described
earlier.
Five distinct modes were identified in the plot, each resulting
in a slight peak in the STP curve and a widening of the main lobe.
Separate chains were assigned to each peak, with the means
roughly aligned with the center of the peak. The variance of the
jitter distribution for each chain was set to 0.3 UDs to fit the slope
of the tail portion of the curve on the left. The mean of each
distribution was then adjusted together with the probability of
transitioning into that chain until the best overall fit was achieved.
For comparison, a conventional single-chain model and a
parallel three-chain model were also fit. In all cases the reference-
clock jitter distribution was assumed to be Gaussian with between
one and five modes. The slope of the tail portion of the single and
three-chain unimodal models matches the measured result, but it
1. The data was analyzed using Tektronix TDSJIT3 jitter software

120
Authorized licensed use limited to: University College Dublin. Downloaded on November 20, 2009 at 09:28 from IEEE Xplore. Restrictions apply.
 0 Max Delay
Mode2 10
Specification

Probability of Occupying State

Probability of a Coarse Increment

10 2 Mode3
Mode1
Single-Chain

20
10 Model
Single-Chain BER
Unimodal Five-Chain
10 4 Mode4 Model
Single-Chain
Quintmodal
40
10
Three Chain
Mode5
10 6 Measured
BER
Five Chain 10
60
1 0 1 2
Delay from Input to Reference (unit delays)
4
3
2
1 0 1 2 3 4
Delay Line State Number
Figure 10: Measured and calculated probability of generating a Figure 11: State probabilities and BER using fitted five-chain
jitter-induced state change in the DLL (PD width = 4 UDs). model and single-chain unimodal model.
wasn’t possible to match both the slope and the width of the main
lobe with fewer than five chains. recovery circuits. The parallel Markov-chain structure overcomes
The parameters used to calculate the five-chain probability limitations in conventional stochastic models that make it difficult
curve are listed in Table 2. The relatively low probability of to model non-stationary systems and systems with substantial
switching between chains implies that the transition rates among deterministic noise and jitter.
the various modes in the reference-clock jitter distribution are The accuracy of the parallel-chain model has been verified by
significantly lower than the sample rate of the DLL. This result is calculating the state probabilities of a digital DLL, and comparing
consistent with the jitter measurements listed in Table 1. The them to the expected results. Two systems were modeled, one that
relatively low transition rate also explains why the single-chain is non-stationary, and one with deterministic jitter. In the first case,
model is less accurate at reproducing the tail regions of the the BER predicted by the parallel-chain model is approximately
probability curve. twelve orders of magnitude more accurate than the conventional
single-chain model, and in the second case the improvement is
Table 2: Parameters used in unimodal five-chain model. almost six orders of magnitude.
Probability of The proposed model was also fit to measured data, and was
Model Type
Chain
Transitioning
Mean Variance
Number (UDs) found to match the transition probabilities to within approximately
Into Chain ()(UDs) 5% over the full range. In contrast, the single-chain model had
1 0.00224 -1.18 0.21 errors as large as four orders of magnitude in the tail regions of the
Five Chain 2 0.032 -0.53 0.21 distribution. The BER predicted by the five-chain fitted model is
Unimodal 3 0.04 0.58 0.21 9.6  10 – 27 under typical operating conditions, which is 32 orders
Gaussian 4 0.004 1.05 0.21 of magnitude higher than that of the conventional model.
5 0.00004 1.66 0.21
8. REFERENCES
6.3 State Probabilities and BER [1] T. H. Lee and J. F. Bulzacchelli, “A 155-MHz clock
Using the five-chain model, the probability of occupying each recovery delay- and phase-locked loop,” IEEE Journal
state in the DLL was calculated, and the result plotted in Figure 11. of Solid-State Circuits, vol. 27, pp. 1736 - 1746, Decem-
ber 1992.
For a maximum delay variation of six unit delays (beyond which a
[2] A. N. Lokanathan and J. B. Brockman, “Efficient worst
timing violation will occur), the BER of the system is 9.6  10 – 27 . case analysis of integrated circuits,” 1995 IEEE Custom
For comparison, the state probabilities were also calculated Integrated Circuits Conference, pp. 237-240, May 1995.
using the single-chain unimodal model. In the resulting histogram, [3] J. R. Burnham, Design and Analysis of jitter-tolerant
also shown in Figure 11, the single-chain model significantly digital delay-locked loops and fixed delay lines, Ph.D.
underestimates the probability of occupying the outer states. For Dissertation, Stanford University, June 2007.
the same maximum delay variation, the BER is 8.8  10 – 59 , or 32 [4] A. E. Payzin, “Analysis of a Digital Bit Synchronizer,”
orders of magnitude lower than that predicted by the five-chain IEEE Trans. on Comm., Vol. Com-31, No. 4, April 1983.
model. [5] V. Stojanovic and Mark Horowitz, “Modeling and Anal-
ysis of High-Speed Links,” 2003 IEEE Custom Inte-
The MTBF calculations described above are based on grated Circuits Conference, pp. 237 - 240, Sept. 2003.
measurements taken under typical conditions. To calculate the [6] D. G. Luenberger, Introduction to Dynamic Systems,
worst-case MTBF, the same model can be used with slight Theory, Models, & Applications: John Wiley & Sons,
modifications to reflect worst-case operating conditions and jitter Inc., pp. 224-245, November 1979.
levels. [7] M. Qi and G. P. Zhang, “Trend Time-Series Modeling
and Forecasting With Neural Networks,” 2008 IEEE
7. CONCLUSION Transactions on Neural Networks, vol. 19, no. 5, pp.
808-816, January 2008.
The stochastic jitter model presented in this paper provides a
useful tool for estimating the BER and MTBF of digital timing

121
Authorized licensed use limited to: University College Dublin. Downloaded on November 20, 2009 at 09:28 from IEEE Xplore. Restrictions apply.