Iijec 2015 01 03 3

IPASJ International Journal of Electronics & Communication (IIJEC)
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ISSN 2321-5984
A Publisher for Research Motivation........
Volume 3, Issue 2, February 2015
REVIEW OF FLASH ANALOGUE TO

DIGITAL CONVERTER
Abidulkarim K. Ilijan
Al-Muthanna University, Iraq College of Engineering
ABSTRACT
This research presents the review of Analog to Digital Convertor (ADC). For ADC there are mainly four different methods,
Flash ADC, Pipelined ADC, Successive Approximation ADC, and Sigma Delta ADC. The Flash ADC is the Fast ADC. For
Designing the ADC, the parameters important are Static and Dynamic. In static parameters Differential Non Linearity Error
(DNLE), Integral Non Linearity Error (INLE) and in dynamic parameters Signal to Noise Ratio (SNR ), Effective Number of
Bits ( EONB ), Spurious-Free Dynamic Range (SFDR), Dynamic Range (DR). The design issues which consist first CMOS
inverter used in CDC architecture, MUX based Decoder and DAC.
Keywords: Analog to Digital Convertor, Differential Non Linearity Error
1. INTRODUCTION
Analog to digital convertor circuit converts analog signal into digital signal. Analog signal is the signal whose
amplitude is continuously changing with respect to time. But in the digital signal the amplitude and time is discrete.
The ADC is characterized by three factor speed, area, and power consumption, the cost of ADC is varying from
application to application. For considering the speed of ADC we have to design the ADC with small voltage supply and
we have to shrink the size of ADC, for this application we are designing Flash ADC with Clocked Digital Convertor
(CDC) configuration which eliminates the resistive network required for generation of internal reference voltage [1-4].
Types of ADC
1. Sigma Delta ADC.
2. Successive Approximation Register (SAR) ADC.
3. Pipelined ADC.
4. Flash ADC.
Comparison between different ADC [5].
Figure 1: Comparison of different ADC [5].

Flash ADC: The flash ADC operates at very high speed with lower resolution [6-10]. It is also called a parallel ADC
due to its parallel operation. Pipelined ADC: The pipelined ADC can operate at a high speed, but it is slower than the
flash [11-15]. It covers a wide range of applications because of its flexible resolution and speed. Successive
Approximation Register ADC: The SAR ADC is suitable for low power and medium-to-high resolution applications
with medium speed [16-19]. Sigma-Delta ADC: The Sigma Delta ADCs are used for high resolution and low speed
applications [20-23].
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2. RESEARCHES
2.1. Introduction to Analog to Digital Converter
Analog to digital converters are the basic building blocks that provide an interface between an analog world and the
digital domain. As it is the main block in mixed signal applications, it becomes a bottleneck in data processing
applications and limits the performance of the overall system. In this chapter we will give the introduction of a number
of A/D converter architectures. We will start from the basic definition of ADC then we will look into different
architecture of ADCs that include Flash, Sigma-Delta, Pipeline, Successive Approximation and Dual Slope ADCs. At
last we will compare the different architectures and will see the impact of CMOS technology on ADC architectures [2427].
2.2. ADC
Analog to Digital Converter (ADC) is a device that accepts an analog value (voltage/current) and converts it into
digital form that can be processed by a microprocessor. Figure 2, shows a simple ADC with two inputs and 8 output
bits. The signal that we want to convert into digital form is applied to input while the reference voltage should be
applied to VREF. The 8 bits at the output represents the input signal in digital form [28].
Figure 2: Ideal Analog to Digital Converter [29].

2.3. ADC Architectures
There are number of architectures available to develop an ADC that depends upon speed, accuracy, resolution etc. The
most common types of ADCs are flash, pipeline, successive approximation, dual slope and sigma-delta [30].
2.3.1. Flash ADC
Flash ADCs are also called parallel ADCs. Due to the parallel architecture it is the fastest ADC among all the other
types and are suitable for high bandwidth applications. On the other hand it consumes a lot of power, has low
resolution, and expensive for high resolution. It is mainly used in high frequency applications and in the other types of
ADC architectures e.g. pipelined and multi bit sigma delta. Few applications of flash ADCs are data acquisition,
satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives. A typical flash ADC
block diagram is shown in Figure 3. It can be seen from the Figure 3, that 2N -1 comparators are required for an "N" bit
converter [31, 32].
The resistor ladder network is formed by 2N resistors, which generates reference voltages for the comparators. The
reference voltage for each comparator is one least significant bit (LSB) less than the reference voltage for the
comparator immediately above it. When the input voltage is higher than the reference voltage of comparator it will
generate a "1", otherwise, the comparator output is "0". If the analog input is in between Vx4 and Vx5, then the
comparators X1 through X4 generates "1"s and all the remaining comparators generate "0".
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Figure 3: Block Diagram of Flash ADC [33].

The comparators will generate a thermometer code of an input signal. It is called thermometer code encoding, because
it is similar to a mercury thermometer, where the mercury column always rises to the appropriate temperature and no
mercury is present above that temperature [34]. This thermometer code will then decode into a binary form by
thermometer-to-binary decoder. The comparators are typically a cascade of wideband and low gain stages. They are
low gain because at high frequencies it's difficult to obtain both wide bandwidth and high gain. They are designed for
low voltage offset, such that the input offset of each comparator is smaller than a LSB of the ADC. Otherwise, the
comparator's offset could falsely trip the comparator, resulting in a digital output code not representative of a
thermometer code. A regenerative latch at each comparator output stores the result. The latch has positive feedback, so
that the end state is forced to either a "1" or a "0" [35].
2.3.2. Sigma-Delta ADC
Figure 4, shows a sigma-delta ADC that uses a 1-bit DAC, filtering, and over sampling to achieve very accurate
conversions.
Figure 4: Block Diagram of Sigma Delta Converter [5].

Low frequency signal is applied to the input of a sigma-delta ADC. 1 Bit DAC will quantize this input signal with high
sampling frequency. The digital decimator filter will reduce the sampling rate and increase ADC resolution. E.g. if the
sampling frequency was 2MHz then the oversampling will reduce the sampling rate to about 8kHz and increases the
ADC's resolution (i.e., dynamic range) to 16 bits [36, 37]. Sigma Delta ADC is famous for its accuracy that is achieved
by the input reference and clock rate.
The flash ADC resistors affect the conversion accuracy that is not the case in sigma delta ADC. The other advantage of
sigma-delta converter is its cost. The limitation of sigma-delta converter is its speed. It is the slowest architecture in all
types of ADC converters. The converter performs over sampling of the input for conversion. This conversion takes
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places in many clock cycles. The other disadvantage of sigma-delta converter is the complexity in designing of the
digital filter that is used to convert duty cycle information into digital word [38].
2.3.3. Pipelined ADC
The pipelined analog-to-digital converter is one of the most popular ADC architecture. It can work from few mega
samples to more than hundreds of mega samples with resolution from 8 bit to 16 bits. Due to its high resolution and
sampling rate range it is widely use in medical and communication applications e.g. CCD imaging, ultrasonic medical
imaging, digital receiver, base station, digital video (for example, HDTV), xDSL, cable modem, and fast Ethernet [39,
40]. Speed, resolution, power and dynamic performance are greatly improved in Pipeline ADC but SAR and integrating
architectures are still used for low sampling rate applications, whereas for high sampling rate (e.g. 1 GHz) flash ADC
is still the choice. The block diagram of 12 bits pipelined ADC is shown in Figure 5.
Figure 5: Pipelined ADC with four 3-bit stages (each stage resolves 2 bits) [41].
Initially sample-and-hold (S&H) circuit, samples and holds the input VIN. The flash ADC in the first stage will convert
this signal into 3 bit digital output. This 3 bits digital code is applied to DAC and the analog output is subtracted from
the original signal, the remainder is then multiplied by 4 and then applied to the next stage. This process will continue
till the last stage (stage 4) and every stage provides 3 bits. After last stage the amplified remainder will feed into 4 Bit
flash ADC that will generate 4 least significant bits.
As every stage generates bits at different instant in time therefore it is required to align all the bits by shift register prior
to applying 12-bit digital output to the digital-error-correction logic. During the interval when one stage completes the
processing of one sample and passes the magnified remainder to the other stage. The next stages are also performing
the same operation because sample and hold circuit is embedded in every stage. This pipelining technique increases the
throughput.
2.3.4. Successive Approximation ADC
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are mostly use in medium to highresolution and low sampling rate applications. These are mostly in the range between 8 to 16 bits. It also provides low
power consumption and small form factor. As its power consumption is low therefore it is the good choice for low
power application such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal
acquisition [42, 43].
SAR ADC actually implements binary search algorithm, therefore its internal circuitry might work at several
megahertz but due to the successive approximation algorithm the sampling rate of ADC is quite small. There are many
ways to implement SAR ADC but its basic structure is shown in Figure 6.
Figure 6: Simplified N-bit SAR ADC architecture [44].
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In this structure track/hold circuit is used to hold the analog input voltage (VIN). The binary search algorithm is
implemented by N-bits register. Initially the value of register is set to mid-scale i.e. MSB set to 1 and all the other
bits are set to 0. The output of DAC (VDAC) becomes half the reference voltage VREF/2, where VREF is the reference
voltage of ADC. The comparator will compare the input voltage, VIN with VDAC. If VIN is greater than VDAC, the
comparator output will be set to 1, and the MSB of the N-bit register remains at '1'. If the input voltage VIN is less
than VDAC, then the comparator output becomes 0. The SAR control logic will change the MSB of the register to '0',
set the next bit to 1 and perform comparison again. This process continues till LSB and once this process is
completed the N-bit digital word is available in the register [45].
2.3.5. Dual-Slope ADC
In order to understand the architecture of Dual slope ADC we first need to understand the concept of single slope ADC.
The single slope ADC is also known as integrating ADC and the main theme of this architecture is to use analog
ramping circuit and digital counter instead of using DAC. The op-amp circuit that is also called an integrator is used to
generate a reference ramp signal that will compare with input signal by a comparator. The digital counter clocked with
precise frequency is used to measure time taken by the reference signal to exceed the input signal voltage [46]. The
Dual-Slope ADC input voltage ( VIN ) integrates for fixed time interval ( TINT ), then it will de-integrate by using
reference voltage ( VREF ) for a variable amount of time ( TDE -INT) as shown in Figure 7 [47].
Figure 7: Dual-slope integration [48].

The behavior of this structure is similar to digital ramp ADC, except that saw-tooth waveform is used as reference
signal rather than stair case signal. Integrating analog-to-digital converters (ADCs) provide high resolution and can
provide good line frequency and noise rejection [49]. As dual slope structure integrates input signal for fixed time
instant therefore input signal becomes average and this will produce output with greater noise immunity. Due to this
fact it is very useful for high accuracy applications. The other advantage of this structure is that it avoids DAC in the
structure that decreases the design complexity. The main limitation of this structure is that it only suitable for low
bandwidth input signals [49].
2.4. ADC comparison
Table 1 shows the range of resolutions, conversion method, encoding method, conversion time, size, advantages and
disadvantages available for flash, sigma delta, successive approximation, and dual slope and pipeline converters. As
one can observe that flash ADC provide the highest speed amongst all the other types of ADC. The speed of sigma
delta converter is comparable with SAR ADC but even it is much slower than flash ADC. From the resolution point of
view successive approximation resolution that is from 8 to 16 bits is comparable with pipelined structure but the fastest
flash has maximum resolution of 6 to 8 bits. Therefore we can conclude that it is always the trade-off between speed,
accuracy and power. The selection of architecture is mainly dependent upon the application.
Table 1: The range of resolutions, conversion method, encoding method, conversion time, size, advantages and
disadvantages available for flash.
FLASH
(Parallel)
Pick This
Architectur
e if
Ultra-High
Speed when
power
consumption
DUAL SLOPE
SAR
Medium to high
resolution (8 to
16bit),
(Integrating
ADC)
Monitoring DC
signals,
high
resolution, low
power
PIPELINE
SIGMA
DELTA
High speeds, few

Msps to 100+
Msps, 8 bits to 16
bits, lower power
High resolution,
low to medium
speed,
no
precision
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you want:
not primary
concern?
5Msps and under,

low power, small
size.
consumption,
good
noise
performance
consumption than
flash.
ICL7106.
external
components,
simultaneous
50/60Hz
rejection, digital
filter
reduces
antialiasing
requirements.
3. DISCUSSION
ADC Parameters:
The parameters of an ADC can be obtained from the data sheet of ADC. The parameters are classified into two
categories.
1) Static Parameters
Figure 8: Staircase transfer function of ADC [5].

i) Differential Non Linearity Error (DNLE)
Figure 9: Differential Non-Linearity error [5].
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ii) Integral Non Linearity Error (INLE)
Figure 10: Integral Non-Linearity error [5].

2) Dynamic Parameters.
1. Signal to Noise Ratio (SNR) The SNR is defined as, it is the ratio of signal power to the noise power. SNR =
(Signal power) / (Noise power) (SNR) dB = (Signal power) - (Noise power) In Ideal Case, (SNR) dB = 6.02N+1.76
Where N= Resolution of ADC. The SNR analysis gives you the noise quantity in the ADC.
2. Effective Number of Bits (EONB) The Effective number of bit is totally depend on the input signal it is defined as,
ENOB = (SNR-1.76) / 6.02 The ENOB will decrease by increasing the input frequency because the noise is totally
depend on the input frequency as frequency increases the noise increases as a result SNR decreases.
3. Spurious-Free Dynamic Range (SFDR). It is ratio of Signal power to the highest amplitude of the harmonic. SFDR
= 20 log (Signal power/ highest amplitude of the second harmonic) SFDR is the most important factor to
distinguishing the input signal from the undesired spur. For analysis of SFDR Fast Fourier Transform plot (FFT) is
required.
4. Dynamic Range (DR). It is defined as, it is ratio of largest output signal change over smallest output signal change.
DR = 20 log(largest output signal change / smallest output signal change ;
Design Issue
1. Clocked Digital Comparator.
2. Transistor Inverter Quantizer (TIQ).
3. CMOS Inverter as Phase Shifter.
4. CMOS Inverter as Quantizer.
5. Transmission Gate.
6. Multiplexer Based Decoder.
7. Digital to Analog Convertor (DAC).
8. Working of ADC-DAC.
Clocked Digital Comparator [50]
For conversion of analog signal into digital signal requires the quantizer, sampler and encoder. In clocked digital
comparator shown in fig. 8, the first stage consist of two inverter the first inverter is acting as the quantizer by settling
the comparator voltages for comparison and the second inverter is acting as the logic level inversion, the need of second
inverter is arises due to the output of first inverter. In ADC and DAC structure the output should be same as the input
signal but the first inverter inverts the input and later on well get the output out of phase so for nullifying the phase
shift we have to add the second inverter.
Figure 11: Clocked Digital Comparator [50].
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Transistor Inverter Quantizer (TIQ) [50]

Comparator structure is most pivotal part in FADC architecture. The role of comparator is to compare the input signal
with reference voltage and gives the respective logic levels (1 and 0) the comparator converts the input signal into only
two logics (logic1 and logic 0) depending on the values of input, if the values of input is greater than threshold value
then itll give logic 1 else itll give logic 0.
Figure 12: Transistor Inverter Quantizer [50].

The TIQ shown in Figure 15, is the first stage of CDC, it is use for generating the internal reference voltage which is
required for comparison, and the internal reference voltage is generated using number of methods like resistive ladder
network, systematically varying the size of transistor. In TIQ the internal reference voltage is generated by systematic
varying the width of NMOS and PMOS we are keeping the length of transistor is same because the length of transistor
is depend on the technology.
CMOS Inverter as Phase Shifter [50]
The inverter provides phase shift, amplification, quantization stages. Let us consider the signal given to the clocked
digital comparator is sine wave then inverter gives the output negative of sine wave, x(t)=A*sin(wt) as input inverter
gives x1(t)=A*sin(wt+pi) further solved this equation by applying some mathematical relationship, sin(A+B) =
sinA*cosB+cosA*sinB x1(t)= A*sin(wt)*cos(pi)+A*cos(wt)*sin(pi) x1(t)= - A*sin(wt) [As cos(pi)=-1 and sin(pi)=0].
CMOS Inverter as Quantizer [5]
The Clocked Digital Comparator compares the input voltage with reference voltage generated by varying the width of
each comparator depending on the value of reference voltage each comparator gives its logic level. The four bit
comparator requires fifteen comparator since they will generate their respective fifteen levels in this way they are acting
as quantizer.
Transmission Gate [50]
The second stage consist of transmission gate, the use of transmission gate is for sampling the signal as we know the
transmission gate work on clock signal if the transmission gate is positive edge enabled clocked then it works only for
positive edges that means it only pass the logic for positive edge and blocked the logic for negative edge thats why we
generally called transmission gate as the switch. The frequency on which clocked operates called as sampling frequency
and the sampling frequency should be more than twice of input frequency, so the clocked digital comparator is acting as
the quantizer and sampler. It can be shown that the Vm point on the VTC of a CMOS inverter, which is shown in Fig.
15, can approximately be given by the following equation;
pW p
V
V
nWn dd Tp Tn
Vm
pW p
1
nWn
Figure 13: Formula for Finding Internal Reference Voltage [50].
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where Vtn and Vtp are the threshold voltages for NMOS and PMOS devices, respectively; and Kn = (W/L)n . mn Cox
Kp = (W/L)p . mp Cox.
Multiplexer Based Decoder [51]:
The multiplexer based decoder circuit uses 2:1 Mux so we required 11 Mux for implementing 15 inputs. The 2:1 Mux
required two input signals with one select line, the select line should vary between two logics 0 to 1 depending on the
select line the Muxll transmit the logic, the truth table of 3 bit thermometer code itself expressing the logic the M.S.B.
bit of binary input equal to middle bit of thermometer code because it follows the twin logic.
Figure 14: Multiplexer Based Decoder [51].

The working principal of multiplexer based decoder is shown in table 1 and in table 2 the M.S.B bit of the output is
equal to the T2 bit of input (Middle bit) and L.S.B. of output is equal to the value of T1 and T2 respectively. In this
design 11 multiplexer are used because in first stage there are 15 inputs for implementing 15 input 7 mux are used in
the second stage 3 mux are used the output of middle multiplexer is acting as select line in the second stage while in
last stage 1 mux is required. Table 2: conversion of 3-bit thermometer code to binary code [51].
Table 2: conversion of 3-bit thermometer code to binary code [51].
Thermometer Code
Binary Code
T3
T2
T1
B2(MSB)
B1
Digital to Analog Convertor (DAC) [50]:

The DAC configuration shown in fig 12 consist of a network of resistor alternating in value of R and 2R. Starting from
bottom of network the 2R resistor is connected to the Vref- the digital input decides which resistor is switched to Vrefand Vref+.
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Figure 15: Digital to Analog Convertor [50].

Working of ADC-DAC [50]:
The fifteen comparator are worked depending on their internal reference voltage as the input signal amplitude crosses
the threshold value of reference voltage respective comparator works thats why they are generating the thermometer
code, as the input signal crosses maximum value of amplitude then all comparator moves to the saturation region they
produces the output equal to logic 1.
After interfacing ADC and DAC together they must produce the output same as the input signal which is shown below,
the threshold voltage are laying in the range from 0.653 to 1.02 volt for this range only the ADC produce the respective
binary bits for below this range the output equal to zero and above this range the output equal to one. In this design the
clocked is use the effect of clocked is showing on the output for positive interval of clocked the logic is generating and
for the negative interval it produces zero output.
The above logic is valid only when the amplitude of input signal starts from zero and reaches toward the maximum
value as the amplitude falls from the maximum value toward zero value the effect of mobility arises. As we know the
mobility of electron is equal to the three times the mobility of whole the output is not same as the input. When the input
is at logic zero the pmos produces the output equal to logic one but if you observe as the pmos conducts itll connect to
the vdd (positive supply) supply it required some delay but in case of nmos when it conducts itll connect it to ground
(negative supply) it will connect to the ground fast as compare to pmos thats why the output is not exactly same as the
input.
4.CONCLUSION
By considering all these we can design the 4 bit Flash ADC and find all the given parameters. Compare these
parameters with the standard parameters.
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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

A Publisher for Research Motivation........

Volume 3, Issue 2, February 2015

REVIEW OF FLASH ANALOGUE TO

Keywords: Analog to Digital Convertor, Differential Non Linearity Error

Figure 1: Comparison of different ADC [5].

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IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Figure 2: Ideal Analog to Digital Converter [29].

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IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Figure 3: Block Diagram of Flash ADC [33].

Figure 4: Block Diagram of Sigma Delta Converter [5].

Volume 3, Issue 2, February 2015

IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Figure 6: Simplified N-bit SAR ADC architecture [44].

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IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Figure 7: Dual-slope integration [48].

Volume 3, Issue 2, February 2015

High speeds, few

IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivation........

Volume 3, Issue 2, February 2015

5Msps and under,

Figure 8: Staircase transfer function of ADC [5].

Figure 9: Differential Non-Linearity error [5].

Volume 3, Issue 2, February 2015

IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

ii) Integral Non Linearity Error (INLE)

Figure 10: Integral Non-Linearity error [5].

Figure 11: Clocked Digital Comparator [50].

Volume 3, Issue 2, February 2015

IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Transistor Inverter Quantizer (TIQ) [50]

Figure 12: Transistor Inverter Quantizer [50].

Volume 3, Issue 2, February 2015

IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivation........

Volume 3, Issue 2, February 2015

Figure 14: Multiplexer Based Decoder [51].

Digital to Analog Convertor (DAC) [50]:

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IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015

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Figure 15: Digital to Analog Convertor [50].

Volume 3, Issue 2, February 2015

IPASJ International Journal of Electronics & Communication (IIJEC)

Volume 3, Issue 2, February 2015