Professional Documents
Culture Documents
&
Design Rules
Kuwait University
Electrical Engineer Department
By Eng. Ahmad Haitham
1
L Edit
L-Edit
Different layers
y are represented
p
by different colors and patterns.
Sample
p of Metal Mask
2
L Edit
L-Edit
L Edit Modules
L-Edit
L Edit The
L-Edit:
Th llayoutt editor
dit
L Edit DRC:
L-Edit
DRC The
Th design
d i rule
l checker
h k
L-Edit
L
Edit Extract:
E t t The
Th layout
l
t extractor
t t to
t
SPICE
L-Edit
L
Edit Window
L-Edit Toolbars
Layer Palette
Graphical menu of the available layers.
layers
Things to Know:
L=2*
8
L-Edit Window
10
L= 0.5 Microns
11
CMOS
Design
g
Rules
13
NMOS Layout:
Layers: Poly,
Poly Active,
Active Nselect
Nselect,, Pselect
Pselect,, Metal,
Metal Active Contact
(W)
3
2 (L)
(L)
L must equal to 2
All contacts must be 2x2
Minimum Metal1
Metal1 width =
=3
3
PMOS Layout:
y
Layers: Poly, Active, Nselect
Nselect,, Pselect
Pselect,, Metal, Active Contact, NWell
3
6
(W)
1
2 (L)
(L)
Minimum spacing from Active to Nwell edge is 6
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17
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20
21
22
23
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Layout
y
Example
p
Draw the layout of a CMOS inverter given the following:
L= 0.5m, Wn= 1.0 m, and Wp= 2.5 m.
25
Stick Diagram
Vdd = 5V
pMOS
Vin
N MOS
26
R
Run
L
L-EDIT
EDIT
by Double click on its icon
27
Design Setup
28
2
29
2
4
Draw Metal1 layers for the VDD &
VSS power supplies.
The minimum width for Metal1=3,
but to distinguish the power supply than
otherMetal1 wiring, make its width=4.
Keep a 2 extension of ploy as shown.
30
4
2
31
NMOS
32
10
33
PMOS
NMOS
34
35
Make 6 by 6 Ploy
4 by
b 4 Metal1
M t l1
2 by 2 Poly Contact
36
37
Why?
Wh
?
To make extra
connection to the
output to use it
later.
38
Click to Port
Click the Metral1 of the object
j yyou
want to give a Name.
39
40
or from here
This action opens a dialog box that allows you to specify the format of
the output.
output
41
L Edit Extractor
L-Edit
L-Edit
L
Edit does not automatically identify the ground to 0 V or
power supply to 3 V. So the generated file must be edited to
identifyy the corresponding
p
g voltages.
g
L Edit Extractor
L-Edit
or from here
43
L Edit Extractor
L-Edit
Enter the name of the
extractor definition file
L-Edit Extractor
Select
Comments: Write Nodes Names
Write Nodes as: Integers
Write
i Node parasitic
i i Capacitance.
C
i
Place device labels on layer:
y Metal1
Then Click Run
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L-Edit
L
Edit Extractor
The following window will appear:
Run PSPICE AD
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Run PSPICE AD
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Cpar1 2 0 7
7.800125f
800125f
Cpar2 3 0 7.73725f
M3 3 4 2 2 PMOS L=0.5u
L 0 5 W=2.5u
W 2 5 AD=5.9375p
AD 5 9375 PD=9.75u
PD 9 75 AS=6.25p
AS 6 25 PS=10u
PS 10
M4 3 4 1 1 NMOS L=0.5u W=1u AD=3.25p PD=8u AS=3.25p PS=8u
* Total Nodes: 4
* Total Elements: 4
* Extract Elapsed
p
Time: 0 seconds
.END
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50
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Transient Analysis
55
Transient Analysis
In the spice file, replace
VIN 4 0 DC 0
.DC VIN 0 3
0.1
By:
VIN 4 0 Pulse ( 0 3 1p 1p 1p 0.5u 1u)
.TRAN
TRAN .02u
02u 2u
56
Transient Analysis
57
Transient Analysis
58
Homework Assignments
1- Redo the design of the layout for CMOS inverter given the
following: L= 0.5m, Wn= 1.5 m, and Wp= 2.5 m. Extract
to spice and plot the voltage transfer characteristics,
characteristics power
dissipaion versus VIN, Vout and VIN versus time and the
average
g ppower dissipation
p
at 4
s ggiven the ppulse of 1s
period.
2- In the same file but in a new cell, draw the layout of the
2_inputs NAND gate that has the same speed of the inverter.
Extract to spice, apply two pulses as inputs, plot both inputs
versus time and Vout versus time to prove that your layout
really present 2_inputs
2 inputs NAND gate
gate.
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Stick Diagrams
Hint:
VDD
Out
A B
GND
NAND22
NAND
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