LAB REPORT

VLSI Physical Design Lab

Submitted by:

Submitted to:
Mr. Vijendra K Maurya

Geetanjali Institute Of Technical Studies

Affiliated to:

Rajasthan Technical University

Kota (Raj.)

INDEX
S.No

Experiment

Date

Remark

Experiment -1
Study of MOS Fabrications
N-MOS Fabrication
The N-MOS transistor consist the P-type Si substrate and N-type of
source and drain. The fabrication of n-MOS transistor consist
various steps.

Step 1 :
A wafer of Si substrate lightly doped P-type impurities and formed
P-type Si substrate as shown below

P-type Si substrate

Step 2 :
The oxidation of silicon surface, by which an oxide layer of about 1
micrometer thickness is created on the substrate

SiO2 (Oxide)

Si-substrate

NAME :
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Step 3 :
The entire oxide surface is covered with several drop of positive
photoresist .The wafer is
spun at about 3000 rpm to be uniformly speed out .

Photoresist
SiO2 (Oxide)

Si-substrate

Step 4 :
A glass mask is used, middle part is transparent and sides are
opaque .The mask put over the positive photoresist. The
photoresist material is exposed to ultraviolet(UV) light, the exposed
area becomes soluble so that they are no longer resistant to etching
solvents and etched away be developing
solution.
UV Light

Glass Mark with feature

Exposed photoresist becomes soluble

Insoluble photoresist
SiO2 (Oxide)

Si -substrate

Step 5 :
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In this step for SiO2 etching, Hydro-fluoric (HF) acid is usually used
because it attacks oxide out not silicon or photo resist. Therefore, the HF
acid etches away the oxide in the opening in the PR and stops at silicon
surface.
Chemical etch (HF acid)

Hardened photoresist
SiO2 (Oxide)

Si -substrate

Hardened photoresist
SiO2 (Oxide)

Si -substrate

Step 6 :
The remaining photo resist can now be stripped from silicon dioxide surface by using another
solvent, leaving the patterned silicon dioxide feature on the surface.

SiO2 (Oxide)

Si -substrate

Step 7 :
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In this step the surface is covered with a thin, high quality oxide
layer which will eventually from the gate oxide of the MOS
transistor.

Thin Oxide
Si - Substrate

Step 8 :
On the top of the thin oxide, a layer of polysilicon (polycrystalline silicon)
is deposited. Polysilicon is used both as gate electrode material for MOS
transistors and also as an interconnect medium in silicon integrated
circuits.

Polysilicon

Thin

Oxide

SiO2 (Oxide)
Si - Substrate

Step 9 :
After deposition, the polysilicon layer is patterned through photolithography process and MOS
transistor gate is formed of polysilicon.
PolySilicon
Thin Oxide

SiO2 (Oxide)
Si - Substrate

NAME :
Si - Substrate

ROLL NO :

Step 10 :
The thin oxide not covered by polysilicon is also etched away, which
expose the bare silicon surface on which the source and drain function are
to be formed.
PolySilicon
Thin Oxide
Si - Substrate

Step 11 :
The entire silicon surface is then doped with the concentration of n-type impurities, either through
diffusion or ion implanation. The doping penetrates the exposed area on the silicon surface,
ultimately creating two n-type region

PolySilicon
Thin Oxide
n
n

n
+

Si - Substrate

Step 12 :
Once the source and drain region are completed, the entire surface is again covered with an
insulating layer of silicon dioxide.

Metal Oxide
ThinOxide

SiO 2

Si - Substrate

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Step 13 :
The insulating oxide layer is then patterned through
photolithography in order to provide contact window, for the drain
and source junction.
Insulating Oxide
ThinOxide

Si - Substrate

Step 14 :
Now the source is covered with evaporated aluminium which will
form the inter - connects.

Metal Oxide
ThinOxide

SiO 2

Si - Substrate

Step 15 :
Finally, the metal oxide layer is patterned through photo-lithography and
etched. Completely the inter connection of the MOS on the surface.

Metal
Oxide
Insulating
SiO2
(Oxide)

Si - Substrate

Experiment -2
Study of CMOS Inverter

NAME :
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Complementary metaloxidesemiconductor (CMOS) is a technology for constructing

integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM,
and other digital logic circuits. CMOS technology is also used for several analog circuits such as
image sensors (CMOS sensor), data converters, and highly integrated transceivers for many
types of communication.

CMOS is also sometimes referred to as complementary-symmetry metaloxide

semiconductor (or COS-MOS. The words "complementary-symmetry" refer to the fact that the
typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and
n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
Two important characteristics of CMOS devices are high noise immunity and low static power
consumption. Significant power is only drawn when the transistors in the CMOS device are
switching between on and off states. Consequently, CMOS devices do not produce as much
waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic.
CMOS also allows a high density of logic functions on a chip. It was primarily for this reason
that CMOS became the most used technology to be implemented in VLSI chips.
The phrase "metaloxidesemiconductor" is a reference to the physical structure of certain fieldeffect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn
is on top of a semiconductor material. Aluminum was once used but now the material is
polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric
materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and
beyond.

NAME :
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Technical details
"CMOS" refers to both a particular style of digital circuitry design, and the family of processes
used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less
power than logic families with resistive loads. Since this advantage has increased and grown
more important, CMOS processes and variants have come to dominate, thus the vast majority of
modern integrated circuit manufacturing is on CMOS processes.
CMOS circuits use a combination of p-type and n-type metaloxidesemiconductor field-effect
transistors (MOSFETs) to implement logic gates and other digital circuits found in computers,
telecommunications equipment, and signal processing equipment. Although CMOS logic can be
implemented with discrete devices (e.g., for instructional purposes in an introductory circuits
class), typical commercial CMOS products are integrated circuits composed of millions of
transistors of both types on a rectangular piece of silicon of between 10 and 400mmThese
devices are commonly called "chips", although within the industry they are also referred to as a
"die" (singular) or "dice", or "dies" (plural).
Composition
The main principle behind CMOS circuits that allows them to implement logic gates is the use of
p-type and n-type metaloxidesemiconductor field-effect transistors to create paths to the output
from either the voltage source or ground. When a path to output is created from the voltage
source, the circuit is said to be pulled up. The other circuit state occurs when a path to output is
created from ground and the output pulled down to the ground potential.
Inversion

CMOS circuits are constructed in such a way that all PMOS transistors must have either an input
from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must
have either an input from ground or from another NMOS transistor. The composition of a PMOS
transistor creates low resistance between its source and drain contacts when a low gate voltage is
applied and high resistance when a high gate voltage is applied. On the other hand, the
NAME :
composition of an NMOS transistor creates high resistance between source and drain when a low
gate voltage is applied and low resistance when a high gate
voltage
ROLL
NO : is applied. CMOS
accomplishes current reduction by complementing every nMOSFET with a pMOSFET and
connecting both gates and both drains together. A high voltage on the gates will cause the
nMOSFET to conduct and the pMOSFET not to conduct while a low voltage on the gates causes
the reverse. This arrangement greatly reduces power consumption and heat generation. However,
during the switching time both MOSFETs conduct briefly as the voltage goes from one state to
another. This induces a brief spike in power consumption and becomes a serious issue at high
frequencies.

V(y)

V(x)

V
OH

V(y)

f
V(y)=V(x)

Switching Threshold
M

VOL

VOL

OH

V(x)

Nominal Voltage Levels

The image on the right shows what happens when an input is connected to both a PMOS
transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of
input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current
that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and
much more current can flow from the supply to the output. Because the resistance between the
supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current
drawn from Q is small. The output therefore registers a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high
resistance) state so it would limit the current flowing from the positive supply to the output,
while the NMOS transistor is in an ON (low resistance) state,
NAME
allowing
:
the output to drain to
ground. Because the resistance between Q and ground is low, the voltage drop due to a current
drawn into Q placing Q above ground is small. This low dropROLL
resultsNO
in :the output registering a
low voltage.
In short, the outputs of the PMOS and NMOS transistors are complementary such that when the
input is low, the output is high, and when the input is high, the output is low. Because of this
behavior of input and output, the CMOS circuits' output is the inversion of the input.

Experiment 3
Problem Statement:-

NAME :
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To design a circuit for an Inverter using MOS circuits and study the input and output transfer
characteristics of the CMOS.
Schematic Diagram:-

Specification:Input Voltage 1.2V

For PMOS
W=2.0u
L=0.12u
For NMOS
W=1.0u
L=0.12u

Result:Wave form as under.

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Conclusion: When input 1 is applied to the CMOS inverter, the output is 0 and when 0 is applied
as input, the output is 1.

Experiment 4

NAME :
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Problem Statement:- To design a circuit for an Inverter using MOS circuits and study the
Voltage transfer characteristics of the transistors.

Schematic Diagram:-

Specification:Input Voltage 1.2V

For PMOS
W=2.0u
L=0.12u
For NMOS
W=1.0u
L=0.12u

Result:-

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Wave form as under.

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Conclusion:When the value of W/L ratio of p-MOS is equal to the value of W/L ratio of n-MOS (i.e.; 2/2)
the threshold voltage (i.e. Vth) is 2.5 V.

Experiment 5
Problem Statement:-

NAME :
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To design a schematic for a NAND gate and verify the truth table.
A(IN)
0
0
1
1

B(IN)
0
1
0
1

Y(OUT)
1
1
1
0

Schematic Diagram:-

Specification:-

NAME :

Input Voltage 1.2V

ROLL NO :

For PMOS
W=2.0u
L=0.12u
For NMOS
W=1.0u
L=0.12u
Result:Waveform as under.

Conclusion:- The truth table of NAND gate is verified.

Experiment 6

NAME :

Problem Statement:-

ROLL NO :

To design a schematic for a NOR gate and verify the truth table
A(IN)
0
0
1
1

B(IN)
0
1
0
1

Y(OUT)
0
0
0
1

Schematic Diagram:-

Specification:Input Voltage 1.2V

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For PMOS
W=2.0u
L=0.12u
For NMOS
W=1.0u
L=0.12u
Result:Waveform as under.

Conclusion:The truth table of NOR gate is verified.

Experiment 7
Problem Statement:-

NAME :
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To design a schematic for a XOR gate and verify the truth table.
A(IN)
0
0
1
1

B(IN)
0
1
0
1

Y(OUT)
0
1
1
0

Schematic Diagram:-

Specification:-

NAME :

Input Voltage 1.2V

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For PMOS
W=2.0u
L=0.12u
For NMOS
W=1.0u
L=0.12u
Result:Waveform as under.

Conclusion:The truth table of XOR gate is verified.

NAME :
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