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1. General description
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs 1OE and 2OE:
74LVC2G241
NXP Semiconductors
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC2G241DP
40 C to +125 C
TSSOP8
SOT505-2
74LVC2G241DC
40 C to +125 C
VSSOP8
74LVC2G241GT
40 C to +125 C
XSON8
74LVC2G241GF
40 C to +125 C
XSON8
74LVC2G241GD
40 C to +125 C
XSON8
74LVC2G241GM
40 C to +125 C
XQFN8
SOT902-2
74LVC2G241GN
40 C to +125 C
XSON8
SOT1116
74LVC2G241GS
40 C to +125 C
XSON8
SOT1203
SOT1089
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74LVC2G241DP
V241
74LVC2G241DC
V41
74LVC2G241GT
V41
74LVC2G241GF
V1
74LVC2G241GD
V41
74LVC2G241GM
V41
74LVC2G241GN
V1
74LVC2G241GS
V1
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC2G241
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74LVC2G241
NXP Semiconductors
5. Functional diagram
1OE
1A
1Y
1
EN1
2OE
2A
2Y
2
EN2
001aah844
Fig 1.
001aah845
Logic symbol
Fig 2.
6. Pinning information
6.1 Pinning
74LVC2G241
1OE
VCC
1A
2OE
2Y
1Y
GND
2A
74LVC2G241
1OE
VCC
1A
2OE
2Y
1Y
GND
2A
001aab570
001aab569
Fig 3.
74LVC2G241
Fig 4.
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74LVC2G241
NXP Semiconductors
74LVC2G241
VCC
1A
2OE
2Y
1Y
GND
2A
1Y
2A
1OE
1A
2Y
GND
1OE
2OE
74LVC2G241
VCC
terminal 1
index area
001aai247
Fig 5.
001aaf057
Fig 6.
1OE
Pin description
Pin
Description
SOT902-2
1A, 2A
2, 5
6, 3
data input
GND
ground (0 V)
1Y, 2Y
6, 3
2, 5
data output
2OE
VCC
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
1OE
1A
2OE
2A
1Y
2Y
[1]
H = HIGH voltage level; L = LOW voltage level; X = dont care; Z = high-impedance OFF-state.
74LVC2G241
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74LVC2G241
NXP Semiconductors
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
VI
input voltage
IOK
Conditions
VI < 0 V
[1]
Max
Unit
0.5
+6.5
50
mA
0.5
+6.5
50
mA
enable mode
[1]
0.5
VCC + 0.5
disable mode
[1]
0.5
+6.5
[1][2]
0.5
+6.5
50
mA
output voltage
VO
Min
Power-down mode
IO
output current
VO = 0 V to VCC
ICC
supply current
100
mA
IGND
ground current
100
mA
Tstg
storage temperature
65
+150
300
mW
Tamb = 40 C to +125 C
Ptot
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP8 packages: above 55 C the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly at 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Conditions
Tamb
ambient temperature
t/V
74LVC2G241
Min
Max
Unit
1.65
5.5
5.5
VCC
5.5
5.5
40
+125
20
ns/V
10
ns/V
5 of 23
74LVC2G241
NXP Semiconductors
Conditions
Min
Typ[1] Max
0.65 VCC
1.7
2.0
0.7 VCC
0.35 VCC V
0.7
0.8
0.3 VCC
0.1
0.45
0.3
Unit
Tamb = 40 C to +85 C
VIH
VIL
VOL
VOH
VI = VIH or VIL
0.4
0.55
0.55
VCC 0.1
1.2
1.9
2.2
2.3
3.8
II
0.1
IOZ
0.1
10
IOFF
VI or VO = 5.5 V; VCC = 0 V
0.1
10
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
0.1
10
ICC
500
CI
input capacitance
pF
74LVC2G241
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Table 7.
Static characteristics continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
0.65 VCC
1.7
2.0
0.7 VCC
0.35 VCC V
Tamb = 40 C to +125 C
HIGH-level input voltage
VIH
VIL
VOL
VOH
0.7
0.8
0.3 VCC
0.1
0.70
0.45
0.60
0.80
0.80
VCC 0.1
VI = VIH or VIL
0.95
1.7
1.9
2.0
3.4
II
20
IOZ
20
IOFF
VI or VO = 5.5 V; VCC = 0 V
20
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
40
ICC
mA
[1]
74LVC2G241
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ten
40 C to +85 C
Conditions
Min
Max
Min
Max
1.0
4.5
8.8
1.0
11.0
ns
0.5
2.8
4.9
0.5
6.3
ns
VCC = 2.7 V
1.0
2.8
4.7
1.0
5.9
ns
0.5
2.6
4.3
0.5
5.4
ns
0.5
2.1
3.7
0.5
4.6
ns
1.5
5.2
9.9
1.5
12.4
ns
1.0
3.1
5.6
1.0
7.0
ns
VCC = 2.7 V
1.5
3.2
5.5
1.5
6.9
ns
0.5
2.7
4.7
0.5
5.9
ns
0.5
2.0
3.8
0.5
4.8
ns
1.0
4.3
8.8
1.0
11.0
ns
1.0
2.7
4.7
1.0
5.9
ns
VCC = 2.7 V
1.0
2.7
4.6
1.0
5.8
ns
1.0
2.5
4.1
1.0
5.1
ns
0.5
1.9
3.3
0.5
4.1
ns
1.0
3.2
11.6
1.0
14.1
ns
0.5
2.2
5.8
0.5
7.6
ns
VCC = 2.7 V
1.0
2.8
4.6
1.0
5.9
ns
1.0
2.6
4.4
1.0
5.7
ns
0.5
2.0
3.4
0.5
4.6
ns
1.0
3.6
12.5
1.0
15.2
ns
0.5
2.0
5.2
0.5
6.9
ns
VCC = 2.7 V
1.5
3.2
4.9
1.5
6.3
ns
1.0
2.8
4.2
1.0
5.4
ns
0.5
2.0
3.3
0.5
4.4
ns
enable time
[2]
[3]
tdis
disable time
[3]
[4]
74LVC2G241
40 C to +125 C Unit
Typ[1]
[4]
8 of 23
74LVC2G241
NXP Semiconductors
Table 8.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter
CPD
[1]
power dissipation
capacitance
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
output enabled
20
pF
output disabled
pF
[5]
[2]
[3]
[4]
[5]
40 C to +85 C
Conditions
12. Waveforms
VI
VM
nA input
GND
tPHL
tPLH
VOH
VM
nY output
VOL
mna230
Fig 7.
Table 9.
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.3 V to 2.7 V
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
4.5 V to 5.5 V
0.5 VCC
0.5 VCC
VOL + 0.3 V
VOH 0.3 V
74LVC2G241
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NXP Semiconductors
VI
1OE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna730
Fig 8.
VI
2OE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
mna731
Fig 9.
74LVC2G241
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74LVC2G241
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tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
RT
CL
RL
001aae235
Test data
Supply voltage
Input
Load
VI
CL
RL
VEXT
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
30 pF
1 k
open
GND
2 VCC
2.3 V to 2.7 V
VCC
30 pF
500
open
GND
2 VCC
2.7 V
2.7 V
50 pF
500
open
GND
6V
3.0 V to 3.6 V
2.7 V
50 pF
500
open
GND
6V
4.5 V to 5.5 V
VCC
50 pF
500
open
GND
2 VCC
74LVC2G241
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NXP Semiconductors
SOT505-2
c
HE
v M A
A2
(A3)
A1
pin 1 index
Lp
L
4
e
detail X
w M
bp
2.5
5 mm
scale
A
max.
A1
A2
A3
bp
D(1)
E(1)
HE
Lp
Z(1)
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8
0
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
12 of 23
74LVC2G241
NXP Semiconductors
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
A
X
c
y
HE
v M A
Q
A
A2
A1
pin 1 index
(A3)
Lp
4
e
detail X
w M
bp
2.5
5 mm
scale
A
max.
A1
A2
A3
bp
D(1)
E(2)
HE
Lp
Z(1)
mm
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
13 of 23
74LVC2G241
NXP Semiconductors
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
4
4
(2)
L1
e1
e1
e1
(2)
A1
D
terminal 1
index area
0
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
e1
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
14 of 23
74LVC2G241
NXP Semiconductors
SOT1089
terminal 1
index area
A
A1
detail X
(4)(2)
e
L
(8)(2)
b 4
5
e1
1
terminal 1
index area
L1
X
0
0.5
scale
Dimensions
Unit
mm
max
nom
min
1 mm
A(1)
0.5
A1
e1
L1
0.35 0.40
0.04 0.20 1.40 1.05
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.27 0.32
0.12 1.30 0.95
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
SOT1089
sot1089_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-09
10-04-12
MO-252
15 of 23
74LVC2G241
NXP Semiconductors
SOT996-2
A1
detail X
terminal 1
index area
e1
C A B
C
v
w
L1
y1 C
L2
X
0
2 mm
scale
max
nom
min
A1
0.05 0.35
2.1
3.1
0.5
0.00 0.15
1.9
e1
0.5
1.5
2.9
L1
L2
0.5
0.15
0.6
0.3
0.05
0.4
v
0.1
0.05 0.05
y1
0.1
sot996-2_po
Outline
version
References
IEC
JEDEC
JEITA
European
projection
Issue date
07-12-21
12-11-20
SOT996-2
16 of 23
74LVC2G241
NXP Semiconductors
SOT902-2
terminal 1
index area
E
A
A1
detail X
e
v
w
b
4
3
C A B
C
y1 C
5
e1
terminal 1
index area
metal area
not for soldering
L1
0
Dimensions
Unit(1)
mm
max
nom
min
2 mm
scale
A
0.5
A1
e1
0.5
L1
0.35 0.15
0.30 0.10
0.25 0.05
0.1
y1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT902-2
---
MO-255
---
sot902-2_po
European
projection
Issue date
10-11-02
11-03-31
17 of 23
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SOT1116
b
4
(4)(2)
L1
e
7
e1
6
e1
5
e1
(8)(2)
A1
terminal 1
index area
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
e1
0.3
L1
0.35 0.40
0.30 0.35
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1116_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-07
SOT1116
18 of 23
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SOT1203
b
2
(4)(2)
L1
e
e1
e1
5
e1
(8)(2)
A1
terminal 1
index area
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
e1
L1
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1203_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-06
SOT1203
19 of 23
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14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
DUT
ESD
ElectroStatic Discharge
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
Change notice
Supersedes
74LVC2G241 v.13
20130408
74LVC2G241 v.12
Modifications:
74LVC2G241 v.12
Modifications:
74LVC2G241 v.11
Modifications:
20120622
74LVC2G241 v.11
For type number 74LVC2G241GM the SOT code has changed to SOT902-2.
20111129
74LVC2G241 v.10
74LVC2G241 v.10
20100806
74LVC2G241 v.9
74LVC2G241 v.9
20080610
74LVC2G241 v.8
74LVC2G241 v.8
20080312
74LVC2G241 v.7
74LVC2G241 v.7
20071005
74LVC2G241 v.6
74LVC2G241 v.6
20060922
74LVC2G241 v.5
74LVC2G241 v.5
20050202
Product specification
74LVC2G241 v.4
74LVC2G241 v.4
20040922
Product specification
74LVC2G241 v.3
74LVC2G241 v.3
20030311
Product specification
74LVC2G241 v.2
74LVC2G241 v.2
20030129
Product specification
74LVC2G241 v.1
74LVC2G241 v.1
20021030
Product specification
74LVC2G241
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Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC2G241
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product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors specifications such use shall be solely at customers
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors
standard warranty and NXP Semiconductors product specifications.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74LVC2G241
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18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.